William/LED-Face-Mask-Rough
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d45e50fcabf29a0e85188083bc6cb1cf252af70f
LED-Face-Mask-Rough/Debug/STM32F429I-DISC1_LEDFaceMask-Rough.list
William Miceli d45e50fcab Microphone input functional and mostly calibrated!
2020-08-27 17:47:13 -04:00

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STM32F429I-DISC1_LEDFaceMask-Rough.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 000001ac 08000000 08000000 00010000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 000042d8 080001ac 080001ac 000101ac 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000010 08004484 08004484 00014484 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08004494 08004494 00020074 2**0
CONTENTS
4 .ARM 00000008 08004494 08004494 00014494 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .preinit_array 00000000 0800449c 0800449c 00020074 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 0800449c 0800449c 0001449c 2**2
CONTENTS, ALLOC, LOAD, DATA
7 .fini_array 00000004 080044a0 080044a0 000144a0 2**2
CONTENTS, ALLOC, LOAD, DATA
8 .data 00000074 20000000 080044a4 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 00000430 20000074 08004518 00020074 2**2
ALLOC
10 ._user_heap_stack 00000604 200004a4 08004518 000204a4 2**0
ALLOC
11 .ARM.attributes 00000030 00000000 00000000 00020074 2**0
CONTENTS, READONLY
12 .debug_info 0000d979 00000000 00000000 000200a4 2**0
CONTENTS, READONLY, DEBUGGING
13 .debug_abbrev 00001d08 00000000 00000000 0002da1d 2**0
CONTENTS, READONLY, DEBUGGING
14 .debug_aranges 00000d20 00000000 00000000 0002f728 2**3
CONTENTS, READONLY, DEBUGGING
15 .debug_ranges 00000c38 00000000 00000000 00030448 2**3
CONTENTS, READONLY, DEBUGGING
16 .debug_macro 0002448d 00000000 00000000 00031080 2**0
CONTENTS, READONLY, DEBUGGING
17 .debug_line 0000a537 00000000 00000000 0005550d 2**0
CONTENTS, READONLY, DEBUGGING
18 .debug_str 000de361 00000000 00000000 0005fa44 2**0
CONTENTS, READONLY, DEBUGGING
19 .comment 0000007b 00000000 00000000 0013dda5 2**0
CONTENTS, READONLY
20 .debug_frame 0000389c 00000000 00000000 0013de20 2**2
CONTENTS, READONLY, DEBUGGING
Disassembly of section .text:
080001ac <__do_global_dtors_aux>:
80001ac: b510 push {r4, lr}
80001ae: 4c05 ldr r4, [pc, #20] ; (80001c4 <__do_global_dtors_aux+0x18>)
80001b0: 7823 ldrb r3, [r4, #0]
80001b2: b933 cbnz r3, 80001c2 <__do_global_dtors_aux+0x16>
80001b4: 4b04 ldr r3, [pc, #16] ; (80001c8 <__do_global_dtors_aux+0x1c>)
80001b6: b113 cbz r3, 80001be <__do_global_dtors_aux+0x12>
80001b8: 4804 ldr r0, [pc, #16] ; (80001cc <__do_global_dtors_aux+0x20>)
80001ba: f3af 8000 nop.w
80001be: 2301 movs r3, #1
80001c0: 7023 strb r3, [r4, #0]
80001c2: bd10 pop {r4, pc}
80001c4: 20000074 .word 0x20000074
80001c8: 00000000 .word 0x00000000
80001cc: 0800446c .word 0x0800446c
080001d0 <frame_dummy>:
80001d0: b508 push {r3, lr}
80001d2: 4b03 ldr r3, [pc, #12] ; (80001e0 <frame_dummy+0x10>)
80001d4: b11b cbz r3, 80001de <frame_dummy+0xe>
80001d6: 4903 ldr r1, [pc, #12] ; (80001e4 <frame_dummy+0x14>)
80001d8: 4803 ldr r0, [pc, #12] ; (80001e8 <frame_dummy+0x18>)
80001da: f3af 8000 nop.w
80001de: bd08 pop {r3, pc}
80001e0: 00000000 .word 0x00000000
80001e4: 20000078 .word 0x20000078
80001e8: 0800446c .word 0x0800446c
080001ec <__aeabi_uldivmod>:
80001ec: b953 cbnz r3, 8000204 <__aeabi_uldivmod+0x18>
80001ee: b94a cbnz r2, 8000204 <__aeabi_uldivmod+0x18>
80001f0: 2900 cmp r1, #0
80001f2: bf08 it eq
80001f4: 2800 cmpeq r0, #0
80001f6: bf1c itt ne
80001f8: f04f 31ff movne.w r1, #4294967295
80001fc: f04f 30ff movne.w r0, #4294967295
8000200: f000 b972 b.w 80004e8 <__aeabi_idiv0>
8000204: f1ad 0c08 sub.w ip, sp, #8
8000208: e96d ce04 strd ip, lr, [sp, #-16]!
800020c: f000 f806 bl 800021c <__udivmoddi4>
8000210: f8dd e004 ldr.w lr, [sp, #4]
8000214: e9dd 2302 ldrd r2, r3, [sp, #8]
8000218: b004 add sp, #16
800021a: 4770 bx lr
0800021c <__udivmoddi4>:
800021c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
8000220: 9e08 ldr r6, [sp, #32]
8000222: 4604 mov r4, r0
8000224: 4688 mov r8, r1
8000226: 2b00 cmp r3, #0
8000228: d14b bne.n 80002c2 <__udivmoddi4+0xa6>
800022a: 428a cmp r2, r1
800022c: 4615 mov r5, r2
800022e: d967 bls.n 8000300 <__udivmoddi4+0xe4>
8000230: fab2 f282 clz r2, r2
8000234: b14a cbz r2, 800024a <__udivmoddi4+0x2e>
8000236: f1c2 0720 rsb r7, r2, #32
800023a: fa01 f302 lsl.w r3, r1, r2
800023e: fa20 f707 lsr.w r7, r0, r7
8000242: 4095 lsls r5, r2
8000244: ea47 0803 orr.w r8, r7, r3
8000248: 4094 lsls r4, r2
800024a: ea4f 4e15 mov.w lr, r5, lsr #16
800024e: 0c23 lsrs r3, r4, #16
8000250: fbb8 f7fe udiv r7, r8, lr
8000254: fa1f fc85 uxth.w ip, r5
8000258: fb0e 8817 mls r8, lr, r7, r8
800025c: ea43 4308 orr.w r3, r3, r8, lsl #16
8000260: fb07 f10c mul.w r1, r7, ip
8000264: 4299 cmp r1, r3
8000266: d909 bls.n 800027c <__udivmoddi4+0x60>
8000268: 18eb adds r3, r5, r3
800026a: f107 30ff add.w r0, r7, #4294967295
800026e: f080 811b bcs.w 80004a8 <__udivmoddi4+0x28c>
8000272: 4299 cmp r1, r3
8000274: f240 8118 bls.w 80004a8 <__udivmoddi4+0x28c>
8000278: 3f02 subs r7, #2
800027a: 442b add r3, r5
800027c: 1a5b subs r3, r3, r1
800027e: b2a4 uxth r4, r4
8000280: fbb3 f0fe udiv r0, r3, lr
8000284: fb0e 3310 mls r3, lr, r0, r3
8000288: ea44 4403 orr.w r4, r4, r3, lsl #16
800028c: fb00 fc0c mul.w ip, r0, ip
8000290: 45a4 cmp ip, r4
8000292: d909 bls.n 80002a8 <__udivmoddi4+0x8c>
8000294: 192c adds r4, r5, r4
8000296: f100 33ff add.w r3, r0, #4294967295
800029a: f080 8107 bcs.w 80004ac <__udivmoddi4+0x290>
800029e: 45a4 cmp ip, r4
80002a0: f240 8104 bls.w 80004ac <__udivmoddi4+0x290>
80002a4: 3802 subs r0, #2
80002a6: 442c add r4, r5
80002a8: ea40 4007 orr.w r0, r0, r7, lsl #16
80002ac: eba4 040c sub.w r4, r4, ip
80002b0: 2700 movs r7, #0
80002b2: b11e cbz r6, 80002bc <__udivmoddi4+0xa0>
80002b4: 40d4 lsrs r4, r2
80002b6: 2300 movs r3, #0
80002b8: e9c6 4300 strd r4, r3, [r6]
80002bc: 4639 mov r1, r7
80002be: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
80002c2: 428b cmp r3, r1
80002c4: d909 bls.n 80002da <__udivmoddi4+0xbe>
80002c6: 2e00 cmp r6, #0
80002c8: f000 80eb beq.w 80004a2 <__udivmoddi4+0x286>
80002cc: 2700 movs r7, #0
80002ce: e9c6 0100 strd r0, r1, [r6]
80002d2: 4638 mov r0, r7
80002d4: 4639 mov r1, r7
80002d6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
80002da: fab3 f783 clz r7, r3
80002de: 2f00 cmp r7, #0
80002e0: d147 bne.n 8000372 <__udivmoddi4+0x156>
80002e2: 428b cmp r3, r1
80002e4: d302 bcc.n 80002ec <__udivmoddi4+0xd0>
80002e6: 4282 cmp r2, r0
80002e8: f200 80fa bhi.w 80004e0 <__udivmoddi4+0x2c4>
80002ec: 1a84 subs r4, r0, r2
80002ee: eb61 0303 sbc.w r3, r1, r3
80002f2: 2001 movs r0, #1
80002f4: 4698 mov r8, r3
80002f6: 2e00 cmp r6, #0
80002f8: d0e0 beq.n 80002bc <__udivmoddi4+0xa0>
80002fa: e9c6 4800 strd r4, r8, [r6]
80002fe: e7dd b.n 80002bc <__udivmoddi4+0xa0>
8000300: b902 cbnz r2, 8000304 <__udivmoddi4+0xe8>
8000302: deff udf #255 ; 0xff
8000304: fab2 f282 clz r2, r2
8000308: 2a00 cmp r2, #0
800030a: f040 808f bne.w 800042c <__udivmoddi4+0x210>
800030e: 1b49 subs r1, r1, r5
8000310: ea4f 4e15 mov.w lr, r5, lsr #16
8000314: fa1f f885 uxth.w r8, r5
8000318: 2701 movs r7, #1
800031a: fbb1 fcfe udiv ip, r1, lr
800031e: 0c23 lsrs r3, r4, #16
8000320: fb0e 111c mls r1, lr, ip, r1
8000324: ea43 4301 orr.w r3, r3, r1, lsl #16
8000328: fb08 f10c mul.w r1, r8, ip
800032c: 4299 cmp r1, r3
800032e: d907 bls.n 8000340 <__udivmoddi4+0x124>
8000330: 18eb adds r3, r5, r3
8000332: f10c 30ff add.w r0, ip, #4294967295
8000336: d202 bcs.n 800033e <__udivmoddi4+0x122>
8000338: 4299 cmp r1, r3
800033a: f200 80cd bhi.w 80004d8 <__udivmoddi4+0x2bc>
800033e: 4684 mov ip, r0
8000340: 1a59 subs r1, r3, r1
8000342: b2a3 uxth r3, r4
8000344: fbb1 f0fe udiv r0, r1, lr
8000348: fb0e 1410 mls r4, lr, r0, r1
800034c: ea43 4404 orr.w r4, r3, r4, lsl #16
8000350: fb08 f800 mul.w r8, r8, r0
8000354: 45a0 cmp r8, r4
8000356: d907 bls.n 8000368 <__udivmoddi4+0x14c>
8000358: 192c adds r4, r5, r4
800035a: f100 33ff add.w r3, r0, #4294967295
800035e: d202 bcs.n 8000366 <__udivmoddi4+0x14a>
8000360: 45a0 cmp r8, r4
8000362: f200 80b6 bhi.w 80004d2 <__udivmoddi4+0x2b6>
8000366: 4618 mov r0, r3
8000368: eba4 0408 sub.w r4, r4, r8
800036c: ea40 400c orr.w r0, r0, ip, lsl #16
8000370: e79f b.n 80002b2 <__udivmoddi4+0x96>
8000372: f1c7 0c20 rsb ip, r7, #32
8000376: 40bb lsls r3, r7
8000378: fa22 fe0c lsr.w lr, r2, ip
800037c: ea4e 0e03 orr.w lr, lr, r3
8000380: fa01 f407 lsl.w r4, r1, r7
8000384: fa20 f50c lsr.w r5, r0, ip
8000388: fa21 f30c lsr.w r3, r1, ip
800038c: ea4f 481e mov.w r8, lr, lsr #16
8000390: 4325 orrs r5, r4
8000392: fbb3 f9f8 udiv r9, r3, r8
8000396: 0c2c lsrs r4, r5, #16
8000398: fb08 3319 mls r3, r8, r9, r3
800039c: fa1f fa8e uxth.w sl, lr
80003a0: ea44 4303 orr.w r3, r4, r3, lsl #16
80003a4: fb09 f40a mul.w r4, r9, sl
80003a8: 429c cmp r4, r3
80003aa: fa02 f207 lsl.w r2, r2, r7
80003ae: fa00 f107 lsl.w r1, r0, r7
80003b2: d90b bls.n 80003cc <__udivmoddi4+0x1b0>
80003b4: eb1e 0303 adds.w r3, lr, r3
80003b8: f109 30ff add.w r0, r9, #4294967295
80003bc: f080 8087 bcs.w 80004ce <__udivmoddi4+0x2b2>
80003c0: 429c cmp r4, r3
80003c2: f240 8084 bls.w 80004ce <__udivmoddi4+0x2b2>
80003c6: f1a9 0902 sub.w r9, r9, #2
80003ca: 4473 add r3, lr
80003cc: 1b1b subs r3, r3, r4
80003ce: b2ad uxth r5, r5
80003d0: fbb3 f0f8 udiv r0, r3, r8
80003d4: fb08 3310 mls r3, r8, r0, r3
80003d8: ea45 4403 orr.w r4, r5, r3, lsl #16
80003dc: fb00 fa0a mul.w sl, r0, sl
80003e0: 45a2 cmp sl, r4
80003e2: d908 bls.n 80003f6 <__udivmoddi4+0x1da>
80003e4: eb1e 0404 adds.w r4, lr, r4
80003e8: f100 33ff add.w r3, r0, #4294967295
80003ec: d26b bcs.n 80004c6 <__udivmoddi4+0x2aa>
80003ee: 45a2 cmp sl, r4
80003f0: d969 bls.n 80004c6 <__udivmoddi4+0x2aa>
80003f2: 3802 subs r0, #2
80003f4: 4474 add r4, lr
80003f6: ea40 4009 orr.w r0, r0, r9, lsl #16
80003fa: fba0 8902 umull r8, r9, r0, r2
80003fe: eba4 040a sub.w r4, r4, sl
8000402: 454c cmp r4, r9
8000404: 46c2 mov sl, r8
8000406: 464b mov r3, r9
8000408: d354 bcc.n 80004b4 <__udivmoddi4+0x298>
800040a: d051 beq.n 80004b0 <__udivmoddi4+0x294>
800040c: 2e00 cmp r6, #0
800040e: d069 beq.n 80004e4 <__udivmoddi4+0x2c8>
8000410: ebb1 050a subs.w r5, r1, sl
8000414: eb64 0403 sbc.w r4, r4, r3
8000418: fa04 fc0c lsl.w ip, r4, ip
800041c: 40fd lsrs r5, r7
800041e: 40fc lsrs r4, r7
8000420: ea4c 0505 orr.w r5, ip, r5
8000424: e9c6 5400 strd r5, r4, [r6]
8000428: 2700 movs r7, #0
800042a: e747 b.n 80002bc <__udivmoddi4+0xa0>
800042c: f1c2 0320 rsb r3, r2, #32
8000430: fa20 f703 lsr.w r7, r0, r3
8000434: 4095 lsls r5, r2
8000436: fa01 f002 lsl.w r0, r1, r2
800043a: fa21 f303 lsr.w r3, r1, r3
800043e: ea4f 4e15 mov.w lr, r5, lsr #16
8000442: 4338 orrs r0, r7
8000444: 0c01 lsrs r1, r0, #16
8000446: fbb3 f7fe udiv r7, r3, lr
800044a: fa1f f885 uxth.w r8, r5
800044e: fb0e 3317 mls r3, lr, r7, r3
8000452: ea41 4103 orr.w r1, r1, r3, lsl #16
8000456: fb07 f308 mul.w r3, r7, r8
800045a: 428b cmp r3, r1
800045c: fa04 f402 lsl.w r4, r4, r2
8000460: d907 bls.n 8000472 <__udivmoddi4+0x256>
8000462: 1869 adds r1, r5, r1
8000464: f107 3cff add.w ip, r7, #4294967295
8000468: d22f bcs.n 80004ca <__udivmoddi4+0x2ae>
800046a: 428b cmp r3, r1
800046c: d92d bls.n 80004ca <__udivmoddi4+0x2ae>
800046e: 3f02 subs r7, #2
8000470: 4429 add r1, r5
8000472: 1acb subs r3, r1, r3
8000474: b281 uxth r1, r0
8000476: fbb3 f0fe udiv r0, r3, lr
800047a: fb0e 3310 mls r3, lr, r0, r3
800047e: ea41 4103 orr.w r1, r1, r3, lsl #16
8000482: fb00 f308 mul.w r3, r0, r8
8000486: 428b cmp r3, r1
8000488: d907 bls.n 800049a <__udivmoddi4+0x27e>
800048a: 1869 adds r1, r5, r1
800048c: f100 3cff add.w ip, r0, #4294967295
8000490: d217 bcs.n 80004c2 <__udivmoddi4+0x2a6>
8000492: 428b cmp r3, r1
8000494: d915 bls.n 80004c2 <__udivmoddi4+0x2a6>
8000496: 3802 subs r0, #2
8000498: 4429 add r1, r5
800049a: 1ac9 subs r1, r1, r3
800049c: ea40 4707 orr.w r7, r0, r7, lsl #16
80004a0: e73b b.n 800031a <__udivmoddi4+0xfe>
80004a2: 4637 mov r7, r6
80004a4: 4630 mov r0, r6
80004a6: e709 b.n 80002bc <__udivmoddi4+0xa0>
80004a8: 4607 mov r7, r0
80004aa: e6e7 b.n 800027c <__udivmoddi4+0x60>
80004ac: 4618 mov r0, r3
80004ae: e6fb b.n 80002a8 <__udivmoddi4+0x8c>
80004b0: 4541 cmp r1, r8
80004b2: d2ab bcs.n 800040c <__udivmoddi4+0x1f0>
80004b4: ebb8 0a02 subs.w sl, r8, r2
80004b8: eb69 020e sbc.w r2, r9, lr
80004bc: 3801 subs r0, #1
80004be: 4613 mov r3, r2
80004c0: e7a4 b.n 800040c <__udivmoddi4+0x1f0>
80004c2: 4660 mov r0, ip
80004c4: e7e9 b.n 800049a <__udivmoddi4+0x27e>
80004c6: 4618 mov r0, r3
80004c8: e795 b.n 80003f6 <__udivmoddi4+0x1da>
80004ca: 4667 mov r7, ip
80004cc: e7d1 b.n 8000472 <__udivmoddi4+0x256>
80004ce: 4681 mov r9, r0
80004d0: e77c b.n 80003cc <__udivmoddi4+0x1b0>
80004d2: 3802 subs r0, #2
80004d4: 442c add r4, r5
80004d6: e747 b.n 8000368 <__udivmoddi4+0x14c>
80004d8: f1ac 0c02 sub.w ip, ip, #2
80004dc: 442b add r3, r5
80004de: e72f b.n 8000340 <__udivmoddi4+0x124>
80004e0: 4638 mov r0, r7
80004e2: e708 b.n 80002f6 <__udivmoddi4+0xda>
80004e4: 4637 mov r7, r6
80004e6: e6e9 b.n 80002bc <__udivmoddi4+0xa0>
080004e8 <__aeabi_idiv0>:
80004e8: 4770 bx lr
80004ea: bf00 nop
080004ec <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
80004ec: b580 push {r7, lr}
80004ee: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
80004f0: f001 fcd8 bl 8001ea4 <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
80004f4: f000 f854 bl 80005a0 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
80004f8: f000 f986 bl 8000808 <MX_GPIO_Init>
MX_SPI4_Init();
80004fc: f000 f90e bl 800071c <MX_SPI4_Init>
MX_TIM6_Init();
8000500: f000 f942 bl 8000788 <MX_TIM6_Init>
MX_ADC3_Init();
8000504: f000 f8b6 bl 8000674 <MX_ADC3_Init>
/* USER CODE BEGIN 2 */
updateWS2812BData();
8000508: f001 f954 bl 80017b4 <updateWS2812BData>
HAL_SPI_Transmit_IT(&hspi4, (uint8_t*) &LEDData, (uint16_t) 66 * 3 * 3);
800050c: f240 2252 movw r2, #594 ; 0x252
8000510: 491e ldr r1, [pc, #120] ; (800058c <main+0xa0>)
8000512: 481f ldr r0, [pc, #124] ; (8000590 <main+0xa4>)
8000514: f003 f8d2 bl 80036bc <HAL_SPI_Transmit_IT>
HAL_ADC_Start(&hadc3);
8000518: 481e ldr r0, [pc, #120] ; (8000594 <main+0xa8>)
800051a: f001 fd9b bl 8002054 <HAL_ADC_Start>
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1) {
if(LEDDesign_PendingChange){
800051e: 4b1e ldr r3, [pc, #120] ; (8000598 <main+0xac>)
8000520: 781b ldrb r3, [r3, #0]
8000522: 2b00 cmp r3, #0
8000524: d002 beq.n 800052c <main+0x40>
LEDDesign_Off();
8000526: f000 fc83 bl 8000e30 <LEDDesign_Off>
800052a: e02c b.n 8000586 <main+0x9a>
}else{
switch (LEDMode) {
800052c: 4b1b ldr r3, [pc, #108] ; (800059c <main+0xb0>)
800052e: 781b ldrb r3, [r3, #0]
8000530: 2b06 cmp r3, #6
8000532: d826 bhi.n 8000582 <main+0x96>
8000534: a201 add r2, pc, #4 ; (adr r2, 800053c <main+0x50>)
8000536: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800053a: bf00 nop
800053c: 08000559 .word 0x08000559
8000540: 0800055f .word 0x0800055f
8000544: 08000565 .word 0x08000565
8000548: 0800056b .word 0x0800056b
800054c: 08000571 .word 0x08000571
8000550: 08000577 .word 0x08000577
8000554: 0800057d .word 0x0800057d
case 0:
LEDDesign_Smile();
8000558: f000 fdba bl 80010d0 <LEDDesign_Smile>
break;
800055c: e013 b.n 8000586 <main+0x9a>
case 1:
LEDDesign_Crazy();
800055e: f000 fd77 bl 8001050 <LEDDesign_Crazy>
break;
8000562: e010 b.n 8000586 <main+0x9a>
case 2:
LEDDesign_SuperCrazy();
8000564: f001 f8a4 bl 80016b0 <LEDDesign_SuperCrazy>
break;
8000568: e00d b.n 8000586 <main+0x9a>
case 3:
LEDDesign_ColorWhite();
800056a: f000 fc89 bl 8000e80 <LEDDesign_ColorWhite>
break;
800056e: e00a b.n 8000586 <main+0x9a>
case 4:
LEDDesign_ColorRed();
8000570: f000 fd2e bl 8000fd0 <LEDDesign_ColorRed>
break;
8000574: e007 b.n 8000586 <main+0x9a>
case 5:
LEDDesign_ColorGreen();
8000576: f000 fceb bl 8000f50 <LEDDesign_ColorGreen>
break;
800057a: e004 b.n 8000586 <main+0x9a>
case 6:
LEDDesign_ColorBlue();
800057c: f000 fca8 bl 8000ed0 <LEDDesign_ColorBlue>
break;
8000580: e001 b.n 8000586 <main+0x9a>
default:
LEDDesign_Off();
8000582: f000 fc55 bl 8000e30 <LEDDesign_Off>
}
}
updateWS2812BData();
8000586: f001 f915 bl 80017b4 <updateWS2812BData>
if(LEDDesign_PendingChange){
800058a: e7c8 b.n 800051e <main+0x32>
800058c: 20000094 .word 0x20000094
8000590: 20000400 .word 0x20000400
8000594: 200003b8 .word 0x200003b8
8000598: 20000091 .word 0x20000091
800059c: 20000090 .word 0x20000090
080005a0 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
80005a0: b580 push {r7, lr}
80005a2: b094 sub sp, #80 ; 0x50
80005a4: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
80005a6: f107 0320 add.w r3, r7, #32
80005aa: 2230 movs r2, #48 ; 0x30
80005ac: 2100 movs r1, #0
80005ae: 4618 mov r0, r3
80005b0: f003 feac bl 800430c <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
80005b4: f107 030c add.w r3, r7, #12
80005b8: 2200 movs r2, #0
80005ba: 601a str r2, [r3, #0]
80005bc: 605a str r2, [r3, #4]
80005be: 609a str r2, [r3, #8]
80005c0: 60da str r2, [r3, #12]
80005c2: 611a str r2, [r3, #16]
/** Configure the main internal regulator output voltage
*/
__HAL_RCC_PWR_CLK_ENABLE();
80005c4: 2300 movs r3, #0
80005c6: 60bb str r3, [r7, #8]
80005c8: 4b28 ldr r3, [pc, #160] ; (800066c <SystemClock_Config+0xcc>)
80005ca: 6c1b ldr r3, [r3, #64] ; 0x40
80005cc: 4a27 ldr r2, [pc, #156] ; (800066c <SystemClock_Config+0xcc>)
80005ce: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
80005d2: 6413 str r3, [r2, #64] ; 0x40
80005d4: 4b25 ldr r3, [pc, #148] ; (800066c <SystemClock_Config+0xcc>)
80005d6: 6c1b ldr r3, [r3, #64] ; 0x40
80005d8: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
80005dc: 60bb str r3, [r7, #8]
80005de: 68bb ldr r3, [r7, #8]
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
80005e0: 2300 movs r3, #0
80005e2: 607b str r3, [r7, #4]
80005e4: 4b22 ldr r3, [pc, #136] ; (8000670 <SystemClock_Config+0xd0>)
80005e6: 681b ldr r3, [r3, #0]
80005e8: 4a21 ldr r2, [pc, #132] ; (8000670 <SystemClock_Config+0xd0>)
80005ea: f443 4340 orr.w r3, r3, #49152 ; 0xc000
80005ee: 6013 str r3, [r2, #0]
80005f0: 4b1f ldr r3, [pc, #124] ; (8000670 <SystemClock_Config+0xd0>)
80005f2: 681b ldr r3, [r3, #0]
80005f4: f403 4340 and.w r3, r3, #49152 ; 0xc000
80005f8: 607b str r3, [r7, #4]
80005fa: 687b ldr r3, [r7, #4]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
80005fc: 2301 movs r3, #1
80005fe: 623b str r3, [r7, #32]
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
8000600: f44f 3380 mov.w r3, #65536 ; 0x10000
8000604: 627b str r3, [r7, #36] ; 0x24
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
8000606: 2302 movs r3, #2
8000608: 63bb str r3, [r7, #56] ; 0x38
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
800060a: f44f 0380 mov.w r3, #4194304 ; 0x400000
800060e: 63fb str r3, [r7, #60] ; 0x3c
RCC_OscInitStruct.PLL.PLLM = 4;
8000610: 2304 movs r3, #4
8000612: 643b str r3, [r7, #64] ; 0x40
RCC_OscInitStruct.PLL.PLLN = 160;
8000614: 23a0 movs r3, #160 ; 0xa0
8000616: 647b str r3, [r7, #68] ; 0x44
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
8000618: 2302 movs r3, #2
800061a: 64bb str r3, [r7, #72] ; 0x48
RCC_OscInitStruct.PLL.PLLQ = 7;
800061c: 2307 movs r3, #7
800061e: 64fb str r3, [r7, #76] ; 0x4c
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
8000620: f107 0320 add.w r3, r7, #32
8000624: 4618 mov r0, r3
8000626: f002 fbb7 bl 8002d98 <HAL_RCC_OscConfig>
800062a: 4603 mov r3, r0
800062c: 2b00 cmp r3, #0
800062e: d001 beq.n 8000634 <SystemClock_Config+0x94>
{
Error_Handler();
8000630: f001 fa60 bl 8001af4 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
8000634: 230f movs r3, #15
8000636: 60fb str r3, [r7, #12]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
8000638: 2302 movs r3, #2
800063a: 613b str r3, [r7, #16]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
800063c: 2300 movs r3, #0
800063e: 617b str r3, [r7, #20]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
8000640: f44f 53a0 mov.w r3, #5120 ; 0x1400
8000644: 61bb str r3, [r7, #24]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
8000646: f44f 5380 mov.w r3, #4096 ; 0x1000
800064a: 61fb str r3, [r7, #28]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
800064c: f107 030c add.w r3, r7, #12
8000650: 2105 movs r1, #5
8000652: 4618 mov r0, r3
8000654: f002 fe10 bl 8003278 <HAL_RCC_ClockConfig>
8000658: 4603 mov r3, r0
800065a: 2b00 cmp r3, #0
800065c: d001 beq.n 8000662 <SystemClock_Config+0xc2>
{
Error_Handler();
800065e: f001 fa49 bl 8001af4 <Error_Handler>
}
}
8000662: bf00 nop
8000664: 3750 adds r7, #80 ; 0x50
8000666: 46bd mov sp, r7
8000668: bd80 pop {r7, pc}
800066a: bf00 nop
800066c: 40023800 .word 0x40023800
8000670: 40007000 .word 0x40007000
08000674 <MX_ADC3_Init>:
* @brief ADC3 Initialization Function
* @param None
* @retval None
*/
static void MX_ADC3_Init(void)
{
8000674: b580 push {r7, lr}
8000676: b084 sub sp, #16
8000678: af00 add r7, sp, #0
/* USER CODE BEGIN ADC3_Init 0 */
/* USER CODE END ADC3_Init 0 */
ADC_ChannelConfTypeDef sConfig = {0};
800067a: 463b mov r3, r7
800067c: 2200 movs r2, #0
800067e: 601a str r2, [r3, #0]
8000680: 605a str r2, [r3, #4]
8000682: 609a str r2, [r3, #8]
8000684: 60da str r2, [r3, #12]
/* USER CODE BEGIN ADC3_Init 1 */
/* USER CODE END ADC3_Init 1 */
/** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion)
*/
hadc3.Instance = ADC3;
8000686: 4b22 ldr r3, [pc, #136] ; (8000710 <MX_ADC3_Init+0x9c>)
8000688: 4a22 ldr r2, [pc, #136] ; (8000714 <MX_ADC3_Init+0xa0>)
800068a: 601a str r2, [r3, #0]
hadc3.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4;
800068c: 4b20 ldr r3, [pc, #128] ; (8000710 <MX_ADC3_Init+0x9c>)
800068e: f44f 3280 mov.w r2, #65536 ; 0x10000
8000692: 605a str r2, [r3, #4]
hadc3.Init.Resolution = ADC_RESOLUTION_8B;
8000694: 4b1e ldr r3, [pc, #120] ; (8000710 <MX_ADC3_Init+0x9c>)
8000696: f04f 7200 mov.w r2, #33554432 ; 0x2000000
800069a: 609a str r2, [r3, #8]
hadc3.Init.ScanConvMode = DISABLE;
800069c: 4b1c ldr r3, [pc, #112] ; (8000710 <MX_ADC3_Init+0x9c>)
800069e: 2200 movs r2, #0
80006a0: 611a str r2, [r3, #16]
hadc3.Init.ContinuousConvMode = DISABLE;
80006a2: 4b1b ldr r3, [pc, #108] ; (8000710 <MX_ADC3_Init+0x9c>)
80006a4: 2200 movs r2, #0
80006a6: 761a strb r2, [r3, #24]
hadc3.Init.DiscontinuousConvMode = DISABLE;
80006a8: 4b19 ldr r3, [pc, #100] ; (8000710 <MX_ADC3_Init+0x9c>)
80006aa: 2200 movs r2, #0
80006ac: f883 2020 strb.w r2, [r3, #32]
hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
80006b0: 4b17 ldr r3, [pc, #92] ; (8000710 <MX_ADC3_Init+0x9c>)
80006b2: 2200 movs r2, #0
80006b4: 62da str r2, [r3, #44] ; 0x2c
hadc3.Init.ExternalTrigConv = ADC_SOFTWARE_START;
80006b6: 4b16 ldr r3, [pc, #88] ; (8000710 <MX_ADC3_Init+0x9c>)
80006b8: 4a17 ldr r2, [pc, #92] ; (8000718 <MX_ADC3_Init+0xa4>)
80006ba: 629a str r2, [r3, #40] ; 0x28
hadc3.Init.DataAlign = ADC_DATAALIGN_RIGHT;
80006bc: 4b14 ldr r3, [pc, #80] ; (8000710 <MX_ADC3_Init+0x9c>)
80006be: 2200 movs r2, #0
80006c0: 60da str r2, [r3, #12]
hadc3.Init.NbrOfConversion = 1;
80006c2: 4b13 ldr r3, [pc, #76] ; (8000710 <MX_ADC3_Init+0x9c>)
80006c4: 2201 movs r2, #1
80006c6: 61da str r2, [r3, #28]
hadc3.Init.DMAContinuousRequests = DISABLE;
80006c8: 4b11 ldr r3, [pc, #68] ; (8000710 <MX_ADC3_Init+0x9c>)
80006ca: 2200 movs r2, #0
80006cc: f883 2030 strb.w r2, [r3, #48] ; 0x30
hadc3.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
80006d0: 4b0f ldr r3, [pc, #60] ; (8000710 <MX_ADC3_Init+0x9c>)
80006d2: 2201 movs r2, #1
80006d4: 615a str r2, [r3, #20]
if (HAL_ADC_Init(&hadc3) != HAL_OK)
80006d6: 480e ldr r0, [pc, #56] ; (8000710 <MX_ADC3_Init+0x9c>)
80006d8: f001 fc78 bl 8001fcc <HAL_ADC_Init>
80006dc: 4603 mov r3, r0
80006de: 2b00 cmp r3, #0
80006e0: d001 beq.n 80006e6 <MX_ADC3_Init+0x72>
{
Error_Handler();
80006e2: f001 fa07 bl 8001af4 <Error_Handler>
}
/** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
*/
sConfig.Channel = ADC_CHANNEL_4;
80006e6: 2304 movs r3, #4
80006e8: 603b str r3, [r7, #0]
sConfig.Rank = 1;
80006ea: 2301 movs r3, #1
80006ec: 607b str r3, [r7, #4]
sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES;
80006ee: 2300 movs r3, #0
80006f0: 60bb str r3, [r7, #8]
if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
80006f2: 463b mov r3, r7
80006f4: 4619 mov r1, r3
80006f6: 4806 ldr r0, [pc, #24] ; (8000710 <MX_ADC3_Init+0x9c>)
80006f8: f001 fe04 bl 8002304 <HAL_ADC_ConfigChannel>
80006fc: 4603 mov r3, r0
80006fe: 2b00 cmp r3, #0
8000700: d001 beq.n 8000706 <MX_ADC3_Init+0x92>
{
Error_Handler();
8000702: f001 f9f7 bl 8001af4 <Error_Handler>
}
/* USER CODE BEGIN ADC3_Init 2 */
/* USER CODE END ADC3_Init 2 */
}
8000706: bf00 nop
8000708: 3710 adds r7, #16
800070a: 46bd mov sp, r7
800070c: bd80 pop {r7, pc}
800070e: bf00 nop
8000710: 200003b8 .word 0x200003b8
8000714: 40012200 .word 0x40012200
8000718: 0f000001 .word 0x0f000001
0800071c <MX_SPI4_Init>:
* @brief SPI4 Initialization Function
* @param None
* @retval None
*/
static void MX_SPI4_Init(void)
{
800071c: b580 push {r7, lr}
800071e: af00 add r7, sp, #0
/* USER CODE BEGIN SPI4_Init 1 */
/* USER CODE END SPI4_Init 1 */
/* SPI4 parameter configuration*/
hspi4.Instance = SPI4;
8000720: 4b17 ldr r3, [pc, #92] ; (8000780 <MX_SPI4_Init+0x64>)
8000722: 4a18 ldr r2, [pc, #96] ; (8000784 <MX_SPI4_Init+0x68>)
8000724: 601a str r2, [r3, #0]
hspi4.Init.Mode = SPI_MODE_MASTER;
8000726: 4b16 ldr r3, [pc, #88] ; (8000780 <MX_SPI4_Init+0x64>)
8000728: f44f 7282 mov.w r2, #260 ; 0x104
800072c: 605a str r2, [r3, #4]
hspi4.Init.Direction = SPI_DIRECTION_2LINES;
800072e: 4b14 ldr r3, [pc, #80] ; (8000780 <MX_SPI4_Init+0x64>)
8000730: 2200 movs r2, #0
8000732: 609a str r2, [r3, #8]
hspi4.Init.DataSize = SPI_DATASIZE_8BIT;
8000734: 4b12 ldr r3, [pc, #72] ; (8000780 <MX_SPI4_Init+0x64>)
8000736: 2200 movs r2, #0
8000738: 60da str r2, [r3, #12]
hspi4.Init.CLKPolarity = SPI_POLARITY_LOW;
800073a: 4b11 ldr r3, [pc, #68] ; (8000780 <MX_SPI4_Init+0x64>)
800073c: 2200 movs r2, #0
800073e: 611a str r2, [r3, #16]
hspi4.Init.CLKPhase = SPI_PHASE_1EDGE;
8000740: 4b0f ldr r3, [pc, #60] ; (8000780 <MX_SPI4_Init+0x64>)
8000742: 2200 movs r2, #0
8000744: 615a str r2, [r3, #20]
hspi4.Init.NSS = SPI_NSS_SOFT;
8000746: 4b0e ldr r3, [pc, #56] ; (8000780 <MX_SPI4_Init+0x64>)
8000748: f44f 7200 mov.w r2, #512 ; 0x200
800074c: 619a str r2, [r3, #24]
hspi4.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_32;
800074e: 4b0c ldr r3, [pc, #48] ; (8000780 <MX_SPI4_Init+0x64>)
8000750: 2220 movs r2, #32
8000752: 61da str r2, [r3, #28]
hspi4.Init.FirstBit = SPI_FIRSTBIT_MSB;
8000754: 4b0a ldr r3, [pc, #40] ; (8000780 <MX_SPI4_Init+0x64>)
8000756: 2200 movs r2, #0
8000758: 621a str r2, [r3, #32]
hspi4.Init.TIMode = SPI_TIMODE_DISABLE;
800075a: 4b09 ldr r3, [pc, #36] ; (8000780 <MX_SPI4_Init+0x64>)
800075c: 2200 movs r2, #0
800075e: 625a str r2, [r3, #36] ; 0x24
hspi4.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
8000760: 4b07 ldr r3, [pc, #28] ; (8000780 <MX_SPI4_Init+0x64>)
8000762: 2200 movs r2, #0
8000764: 629a str r2, [r3, #40] ; 0x28
hspi4.Init.CRCPolynomial = 10;
8000766: 4b06 ldr r3, [pc, #24] ; (8000780 <MX_SPI4_Init+0x64>)
8000768: 220a movs r2, #10
800076a: 62da str r2, [r3, #44] ; 0x2c
if (HAL_SPI_Init(&hspi4) != HAL_OK)
800076c: 4804 ldr r0, [pc, #16] ; (8000780 <MX_SPI4_Init+0x64>)
800076e: f002 ff41 bl 80035f4 <HAL_SPI_Init>
8000772: 4603 mov r3, r0
8000774: 2b00 cmp r3, #0
8000776: d001 beq.n 800077c <MX_SPI4_Init+0x60>
{
Error_Handler();
8000778: f001 f9bc bl 8001af4 <Error_Handler>
}
/* USER CODE BEGIN SPI4_Init 2 */
/* USER CODE END SPI4_Init 2 */
}
800077c: bf00 nop
800077e: bd80 pop {r7, pc}
8000780: 20000400 .word 0x20000400
8000784: 40013400 .word 0x40013400
08000788 <MX_TIM6_Init>:
* @brief TIM6 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM6_Init(void)
{
8000788: b580 push {r7, lr}
800078a: b082 sub sp, #8
800078c: af00 add r7, sp, #0
/* USER CODE BEGIN TIM6_Init 0 */
/* USER CODE END TIM6_Init 0 */
TIM_MasterConfigTypeDef sMasterConfig = {0};
800078e: 463b mov r3, r7
8000790: 2200 movs r2, #0
8000792: 601a str r2, [r3, #0]
8000794: 605a str r2, [r3, #4]
/* USER CODE BEGIN TIM6_Init 1 */
/* USER CODE END TIM6_Init 1 */
htim6.Instance = TIM6;
8000796: 4b1a ldr r3, [pc, #104] ; (8000800 <MX_TIM6_Init+0x78>)
8000798: 4a1a ldr r2, [pc, #104] ; (8000804 <MX_TIM6_Init+0x7c>)
800079a: 601a str r2, [r3, #0]
htim6.Init.Prescaler = 4000;
800079c: 4b18 ldr r3, [pc, #96] ; (8000800 <MX_TIM6_Init+0x78>)
800079e: f44f 627a mov.w r2, #4000 ; 0xfa0
80007a2: 605a str r2, [r3, #4]
htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
80007a4: 4b16 ldr r3, [pc, #88] ; (8000800 <MX_TIM6_Init+0x78>)
80007a6: 2200 movs r2, #0
80007a8: 609a str r2, [r3, #8]
htim6.Init.Period = 10000;
80007aa: 4b15 ldr r3, [pc, #84] ; (8000800 <MX_TIM6_Init+0x78>)
80007ac: f242 7210 movw r2, #10000 ; 0x2710
80007b0: 60da str r2, [r3, #12]
htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE;
80007b2: 4b13 ldr r3, [pc, #76] ; (8000800 <MX_TIM6_Init+0x78>)
80007b4: 2280 movs r2, #128 ; 0x80
80007b6: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim6) != HAL_OK)
80007b8: 4811 ldr r0, [pc, #68] ; (8000800 <MX_TIM6_Init+0x78>)
80007ba: f003 fa7d bl 8003cb8 <HAL_TIM_Base_Init>
80007be: 4603 mov r3, r0
80007c0: 2b00 cmp r3, #0
80007c2: d001 beq.n 80007c8 <MX_TIM6_Init+0x40>
{
Error_Handler();
80007c4: f001 f996 bl 8001af4 <Error_Handler>
}
if (HAL_TIM_OnePulse_Init(&htim6, TIM_OPMODE_SINGLE) != HAL_OK)
80007c8: 2108 movs r1, #8
80007ca: 480d ldr r0, [pc, #52] ; (8000800 <MX_TIM6_Init+0x78>)
80007cc: f003 fac3 bl 8003d56 <HAL_TIM_OnePulse_Init>
80007d0: 4603 mov r3, r0
80007d2: 2b00 cmp r3, #0
80007d4: d001 beq.n 80007da <MX_TIM6_Init+0x52>
{
Error_Handler();
80007d6: f001 f98d bl 8001af4 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
80007da: 2300 movs r3, #0
80007dc: 603b str r3, [r7, #0]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
80007de: 2300 movs r3, #0
80007e0: 607b str r3, [r7, #4]
if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK)
80007e2: 463b mov r3, r7
80007e4: 4619 mov r1, r3
80007e6: 4806 ldr r0, [pc, #24] ; (8000800 <MX_TIM6_Init+0x78>)
80007e8: f003 fcd6 bl 8004198 <HAL_TIMEx_MasterConfigSynchronization>
80007ec: 4603 mov r3, r0
80007ee: 2b00 cmp r3, #0
80007f0: d001 beq.n 80007f6 <MX_TIM6_Init+0x6e>
{
Error_Handler();
80007f2: f001 f97f bl 8001af4 <Error_Handler>
}
/* USER CODE BEGIN TIM6_Init 2 */
/* USER CODE END TIM6_Init 2 */
}
80007f6: bf00 nop
80007f8: 3708 adds r7, #8
80007fa: 46bd mov sp, r7
80007fc: bd80 pop {r7, pc}
80007fe: bf00 nop
8000800: 20000458 .word 0x20000458
8000804: 40001000 .word 0x40001000
08000808 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
8000808: b580 push {r7, lr}
800080a: b08e sub sp, #56 ; 0x38
800080c: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
800080e: f107 0324 add.w r3, r7, #36 ; 0x24
8000812: 2200 movs r2, #0
8000814: 601a str r2, [r3, #0]
8000816: 605a str r2, [r3, #4]
8000818: 609a str r2, [r3, #8]
800081a: 60da str r2, [r3, #12]
800081c: 611a str r2, [r3, #16]
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOE_CLK_ENABLE();
800081e: 2300 movs r3, #0
8000820: 623b str r3, [r7, #32]
8000822: 4bb0 ldr r3, [pc, #704] ; (8000ae4 <MX_GPIO_Init+0x2dc>)
8000824: 6b1b ldr r3, [r3, #48] ; 0x30
8000826: 4aaf ldr r2, [pc, #700] ; (8000ae4 <MX_GPIO_Init+0x2dc>)
8000828: f043 0310 orr.w r3, r3, #16
800082c: 6313 str r3, [r2, #48] ; 0x30
800082e: 4bad ldr r3, [pc, #692] ; (8000ae4 <MX_GPIO_Init+0x2dc>)
8000830: 6b1b ldr r3, [r3, #48] ; 0x30
8000832: f003 0310 and.w r3, r3, #16
8000836: 623b str r3, [r7, #32]
8000838: 6a3b ldr r3, [r7, #32]
__HAL_RCC_GPIOC_CLK_ENABLE();
800083a: 2300 movs r3, #0
800083c: 61fb str r3, [r7, #28]
800083e: 4ba9 ldr r3, [pc, #676] ; (8000ae4 <MX_GPIO_Init+0x2dc>)
8000840: 6b1b ldr r3, [r3, #48] ; 0x30
8000842: 4aa8 ldr r2, [pc, #672] ; (8000ae4 <MX_GPIO_Init+0x2dc>)
8000844: f043 0304 orr.w r3, r3, #4
8000848: 6313 str r3, [r2, #48] ; 0x30
800084a: 4ba6 ldr r3, [pc, #664] ; (8000ae4 <MX_GPIO_Init+0x2dc>)
800084c: 6b1b ldr r3, [r3, #48] ; 0x30
800084e: f003 0304 and.w r3, r3, #4
8000852: 61fb str r3, [r7, #28]
8000854: 69fb ldr r3, [r7, #28]
__HAL_RCC_GPIOF_CLK_ENABLE();
8000856: 2300 movs r3, #0
8000858: 61bb str r3, [r7, #24]
800085a: 4ba2 ldr r3, [pc, #648] ; (8000ae4 <MX_GPIO_Init+0x2dc>)
800085c: 6b1b ldr r3, [r3, #48] ; 0x30
800085e: 4aa1 ldr r2, [pc, #644] ; (8000ae4 <MX_GPIO_Init+0x2dc>)
8000860: f043 0320 orr.w r3, r3, #32
8000864: 6313 str r3, [r2, #48] ; 0x30
8000866: 4b9f ldr r3, [pc, #636] ; (8000ae4 <MX_GPIO_Init+0x2dc>)
8000868: 6b1b ldr r3, [r3, #48] ; 0x30
800086a: f003 0320 and.w r3, r3, #32
800086e: 61bb str r3, [r7, #24]
8000870: 69bb ldr r3, [r7, #24]
__HAL_RCC_GPIOH_CLK_ENABLE();
8000872: 2300 movs r3, #0
8000874: 617b str r3, [r7, #20]
8000876: 4b9b ldr r3, [pc, #620] ; (8000ae4 <MX_GPIO_Init+0x2dc>)
8000878: 6b1b ldr r3, [r3, #48] ; 0x30
800087a: 4a9a ldr r2, [pc, #616] ; (8000ae4 <MX_GPIO_Init+0x2dc>)
800087c: f043 0380 orr.w r3, r3, #128 ; 0x80
8000880: 6313 str r3, [r2, #48] ; 0x30
8000882: 4b98 ldr r3, [pc, #608] ; (8000ae4 <MX_GPIO_Init+0x2dc>)
8000884: 6b1b ldr r3, [r3, #48] ; 0x30
8000886: f003 0380 and.w r3, r3, #128 ; 0x80
800088a: 617b str r3, [r7, #20]
800088c: 697b ldr r3, [r7, #20]
__HAL_RCC_GPIOA_CLK_ENABLE();
800088e: 2300 movs r3, #0
8000890: 613b str r3, [r7, #16]
8000892: 4b94 ldr r3, [pc, #592] ; (8000ae4 <MX_GPIO_Init+0x2dc>)
8000894: 6b1b ldr r3, [r3, #48] ; 0x30
8000896: 4a93 ldr r2, [pc, #588] ; (8000ae4 <MX_GPIO_Init+0x2dc>)
8000898: f043 0301 orr.w r3, r3, #1
800089c: 6313 str r3, [r2, #48] ; 0x30
800089e: 4b91 ldr r3, [pc, #580] ; (8000ae4 <MX_GPIO_Init+0x2dc>)
80008a0: 6b1b ldr r3, [r3, #48] ; 0x30
80008a2: f003 0301 and.w r3, r3, #1
80008a6: 613b str r3, [r7, #16]
80008a8: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOB_CLK_ENABLE();
80008aa: 2300 movs r3, #0
80008ac: 60fb str r3, [r7, #12]
80008ae: 4b8d ldr r3, [pc, #564] ; (8000ae4 <MX_GPIO_Init+0x2dc>)
80008b0: 6b1b ldr r3, [r3, #48] ; 0x30
80008b2: 4a8c ldr r2, [pc, #560] ; (8000ae4 <MX_GPIO_Init+0x2dc>)
80008b4: f043 0302 orr.w r3, r3, #2
80008b8: 6313 str r3, [r2, #48] ; 0x30
80008ba: 4b8a ldr r3, [pc, #552] ; (8000ae4 <MX_GPIO_Init+0x2dc>)
80008bc: 6b1b ldr r3, [r3, #48] ; 0x30
80008be: f003 0302 and.w r3, r3, #2
80008c2: 60fb str r3, [r7, #12]
80008c4: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOG_CLK_ENABLE();
80008c6: 2300 movs r3, #0
80008c8: 60bb str r3, [r7, #8]
80008ca: 4b86 ldr r3, [pc, #536] ; (8000ae4 <MX_GPIO_Init+0x2dc>)
80008cc: 6b1b ldr r3, [r3, #48] ; 0x30
80008ce: 4a85 ldr r2, [pc, #532] ; (8000ae4 <MX_GPIO_Init+0x2dc>)
80008d0: f043 0340 orr.w r3, r3, #64 ; 0x40
80008d4: 6313 str r3, [r2, #48] ; 0x30
80008d6: 4b83 ldr r3, [pc, #524] ; (8000ae4 <MX_GPIO_Init+0x2dc>)
80008d8: 6b1b ldr r3, [r3, #48] ; 0x30
80008da: f003 0340 and.w r3, r3, #64 ; 0x40
80008de: 60bb str r3, [r7, #8]
80008e0: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOD_CLK_ENABLE();
80008e2: 2300 movs r3, #0
80008e4: 607b str r3, [r7, #4]
80008e6: 4b7f ldr r3, [pc, #508] ; (8000ae4 <MX_GPIO_Init+0x2dc>)
80008e8: 6b1b ldr r3, [r3, #48] ; 0x30
80008ea: 4a7e ldr r2, [pc, #504] ; (8000ae4 <MX_GPIO_Init+0x2dc>)
80008ec: f043 0308 orr.w r3, r3, #8
80008f0: 6313 str r3, [r2, #48] ; 0x30
80008f2: 4b7c ldr r3, [pc, #496] ; (8000ae4 <MX_GPIO_Init+0x2dc>)
80008f4: 6b1b ldr r3, [r3, #48] ; 0x30
80008f6: f003 0308 and.w r3, r3, #8
80008fa: 607b str r3, [r7, #4]
80008fc: 687b ldr r3, [r7, #4]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOC, NCS_MEMS_SPI_Pin|CSX_Pin|OTG_FS_PSO_Pin, GPIO_PIN_RESET);
80008fe: 2200 movs r2, #0
8000900: 2116 movs r1, #22
8000902: 4879 ldr r0, [pc, #484] ; (8000ae8 <MX_GPIO_Init+0x2e0>)
8000904: f002 fa0a bl 8002d1c <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(ACP_RST_GPIO_Port, ACP_RST_Pin, GPIO_PIN_RESET);
8000908: 2200 movs r2, #0
800090a: 2180 movs r1, #128 ; 0x80
800090c: 4877 ldr r0, [pc, #476] ; (8000aec <MX_GPIO_Init+0x2e4>)
800090e: f002 fa05 bl 8002d1c <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOD, RDX_Pin|WRX_DCX_Pin, GPIO_PIN_RESET);
8000912: 2200 movs r2, #0
8000914: f44f 5140 mov.w r1, #12288 ; 0x3000
8000918: 4875 ldr r0, [pc, #468] ; (8000af0 <MX_GPIO_Init+0x2e8>)
800091a: f002 f9ff bl 8002d1c <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOG, LD3_Pin|LD4_Pin, GPIO_PIN_RESET);
800091e: 2200 movs r2, #0
8000920: f44f 41c0 mov.w r1, #24576 ; 0x6000
8000924: 4873 ldr r0, [pc, #460] ; (8000af4 <MX_GPIO_Init+0x2ec>)
8000926: f002 f9f9 bl 8002d1c <HAL_GPIO_WritePin>
/*Configure GPIO pins : A0_Pin A1_Pin A2_Pin A3_Pin
A4_Pin A5_Pin SDNRAS_Pin A6_Pin
A7_Pin A8_Pin A9_Pin */
GPIO_InitStruct.Pin = A0_Pin|A1_Pin|A2_Pin|A3_Pin
800092a: f64f 033f movw r3, #63551 ; 0xf83f
800092e: 627b str r3, [r7, #36] ; 0x24
|A4_Pin|A5_Pin|SDNRAS_Pin|A6_Pin
|A7_Pin|A8_Pin|A9_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000930: 2302 movs r3, #2
8000932: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000934: 2300 movs r3, #0
8000936: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000938: 2303 movs r3, #3
800093a: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
800093c: 230c movs r3, #12
800093e: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
8000940: f107 0324 add.w r3, r7, #36 ; 0x24
8000944: 4619 mov r1, r3
8000946: 486c ldr r0, [pc, #432] ; (8000af8 <MX_GPIO_Init+0x2f0>)
8000948: f002 f83e bl 80029c8 <HAL_GPIO_Init>
/*Configure GPIO pins : SPI5_SCK_Pin SPI5_MISO_Pin SPI5_MOSI_Pin */
GPIO_InitStruct.Pin = SPI5_SCK_Pin|SPI5_MISO_Pin|SPI5_MOSI_Pin;
800094c: f44f 7360 mov.w r3, #896 ; 0x380
8000950: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000952: 2302 movs r3, #2
8000954: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000956: 2300 movs r3, #0
8000958: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
800095a: 2300 movs r3, #0
800095c: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF5_SPI5;
800095e: 2305 movs r3, #5
8000960: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
8000962: f107 0324 add.w r3, r7, #36 ; 0x24
8000966: 4619 mov r1, r3
8000968: 4863 ldr r0, [pc, #396] ; (8000af8 <MX_GPIO_Init+0x2f0>)
800096a: f002 f82d bl 80029c8 <HAL_GPIO_Init>
/*Configure GPIO pin : ENABLE_Pin */
GPIO_InitStruct.Pin = ENABLE_Pin;
800096e: f44f 6380 mov.w r3, #1024 ; 0x400
8000972: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000974: 2302 movs r3, #2
8000976: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000978: 2300 movs r3, #0
800097a: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
800097c: 2300 movs r3, #0
800097e: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
8000980: 230e movs r3, #14
8000982: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(ENABLE_GPIO_Port, &GPIO_InitStruct);
8000984: f107 0324 add.w r3, r7, #36 ; 0x24
8000988: 4619 mov r1, r3
800098a: 485b ldr r0, [pc, #364] ; (8000af8 <MX_GPIO_Init+0x2f0>)
800098c: f002 f81c bl 80029c8 <HAL_GPIO_Init>
/*Configure GPIO pin : SDNWE_Pin */
GPIO_InitStruct.Pin = SDNWE_Pin;
8000990: 2301 movs r3, #1
8000992: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000994: 2302 movs r3, #2
8000996: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000998: 2300 movs r3, #0
800099a: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
800099c: 2303 movs r3, #3
800099e: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
80009a0: 230c movs r3, #12
80009a2: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(SDNWE_GPIO_Port, &GPIO_InitStruct);
80009a4: f107 0324 add.w r3, r7, #36 ; 0x24
80009a8: 4619 mov r1, r3
80009aa: 484f ldr r0, [pc, #316] ; (8000ae8 <MX_GPIO_Init+0x2e0>)
80009ac: f002 f80c bl 80029c8 <HAL_GPIO_Init>
/*Configure GPIO pins : NCS_MEMS_SPI_Pin CSX_Pin OTG_FS_PSO_Pin */
GPIO_InitStruct.Pin = NCS_MEMS_SPI_Pin|CSX_Pin|OTG_FS_PSO_Pin;
80009b0: 2316 movs r3, #22
80009b2: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
80009b4: 2301 movs r3, #1
80009b6: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80009b8: 2300 movs r3, #0
80009ba: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80009bc: 2300 movs r3, #0
80009be: 633b str r3, [r7, #48] ; 0x30
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
80009c0: f107 0324 add.w r3, r7, #36 ; 0x24
80009c4: 4619 mov r1, r3
80009c6: 4848 ldr r0, [pc, #288] ; (8000ae8 <MX_GPIO_Init+0x2e0>)
80009c8: f001 fffe bl 80029c8 <HAL_GPIO_Init>
/*Configure GPIO pin : B1_Pin */
GPIO_InitStruct.Pin = B1_Pin;
80009cc: 2301 movs r3, #1
80009ce: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
80009d0: 4b4a ldr r3, [pc, #296] ; (8000afc <MX_GPIO_Init+0x2f4>)
80009d2: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80009d4: 2300 movs r3, #0
80009d6: 62fb str r3, [r7, #44] ; 0x2c
HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct);
80009d8: f107 0324 add.w r3, r7, #36 ; 0x24
80009dc: 4619 mov r1, r3
80009de: 4843 ldr r0, [pc, #268] ; (8000aec <MX_GPIO_Init+0x2e4>)
80009e0: f001 fff2 bl 80029c8 <HAL_GPIO_Init>
/*Configure GPIO pins : MEMS_INT1_Pin MEMS_INT2_Pin TP_INT1_Pin */
GPIO_InitStruct.Pin = MEMS_INT1_Pin|MEMS_INT2_Pin|TP_INT1_Pin;
80009e4: f248 0306 movw r3, #32774 ; 0x8006
80009e8: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_EVT_RISING;
80009ea: 4b45 ldr r3, [pc, #276] ; (8000b00 <MX_GPIO_Init+0x2f8>)
80009ec: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80009ee: 2300 movs r3, #0
80009f0: 62fb str r3, [r7, #44] ; 0x2c
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80009f2: f107 0324 add.w r3, r7, #36 ; 0x24
80009f6: 4619 mov r1, r3
80009f8: 483c ldr r0, [pc, #240] ; (8000aec <MX_GPIO_Init+0x2e4>)
80009fa: f001 ffe5 bl 80029c8 <HAL_GPIO_Init>
/*Configure GPIO pins : B5_Pin VSYNC_Pin G2_Pin R4_Pin
R5_Pin */
GPIO_InitStruct.Pin = B5_Pin|VSYNC_Pin|G2_Pin|R4_Pin
80009fe: f641 0358 movw r3, #6232 ; 0x1858
8000a02: 627b str r3, [r7, #36] ; 0x24
|R5_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000a04: 2302 movs r3, #2
8000a06: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000a08: 2300 movs r3, #0
8000a0a: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000a0c: 2300 movs r3, #0
8000a0e: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
8000a10: 230e movs r3, #14
8000a12: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000a14: f107 0324 add.w r3, r7, #36 ; 0x24
8000a18: 4619 mov r1, r3
8000a1a: 4834 ldr r0, [pc, #208] ; (8000aec <MX_GPIO_Init+0x2e4>)
8000a1c: f001 ffd4 bl 80029c8 <HAL_GPIO_Init>
/*Configure GPIO pin : ACP_RST_Pin */
GPIO_InitStruct.Pin = ACP_RST_Pin;
8000a20: 2380 movs r3, #128 ; 0x80
8000a22: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000a24: 2301 movs r3, #1
8000a26: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000a28: 2300 movs r3, #0
8000a2a: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000a2c: 2300 movs r3, #0
8000a2e: 633b str r3, [r7, #48] ; 0x30
HAL_GPIO_Init(ACP_RST_GPIO_Port, &GPIO_InitStruct);
8000a30: f107 0324 add.w r3, r7, #36 ; 0x24
8000a34: 4619 mov r1, r3
8000a36: 482d ldr r0, [pc, #180] ; (8000aec <MX_GPIO_Init+0x2e4>)
8000a38: f001 ffc6 bl 80029c8 <HAL_GPIO_Init>
/*Configure GPIO pin : OTG_FS_OC_Pin */
GPIO_InitStruct.Pin = OTG_FS_OC_Pin;
8000a3c: 2320 movs r3, #32
8000a3e: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_EVT_RISING;
8000a40: 4b2f ldr r3, [pc, #188] ; (8000b00 <MX_GPIO_Init+0x2f8>)
8000a42: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000a44: 2300 movs r3, #0
8000a46: 62fb str r3, [r7, #44] ; 0x2c
HAL_GPIO_Init(OTG_FS_OC_GPIO_Port, &GPIO_InitStruct);
8000a48: f107 0324 add.w r3, r7, #36 ; 0x24
8000a4c: 4619 mov r1, r3
8000a4e: 4826 ldr r0, [pc, #152] ; (8000ae8 <MX_GPIO_Init+0x2e0>)
8000a50: f001 ffba bl 80029c8 <HAL_GPIO_Init>
/*Configure GPIO pins : R3_Pin R6_Pin */
GPIO_InitStruct.Pin = R3_Pin|R6_Pin;
8000a54: 2303 movs r3, #3
8000a56: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000a58: 2302 movs r3, #2
8000a5a: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000a5c: 2300 movs r3, #0
8000a5e: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000a60: 2300 movs r3, #0
8000a62: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF9_LTDC;
8000a64: 2309 movs r3, #9
8000a66: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8000a68: f107 0324 add.w r3, r7, #36 ; 0x24
8000a6c: 4619 mov r1, r3
8000a6e: 4825 ldr r0, [pc, #148] ; (8000b04 <MX_GPIO_Init+0x2fc>)
8000a70: f001 ffaa bl 80029c8 <HAL_GPIO_Init>
/*Configure GPIO pin : BOOT1_Pin */
GPIO_InitStruct.Pin = BOOT1_Pin;
8000a74: 2304 movs r3, #4
8000a76: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8000a78: 2300 movs r3, #0
8000a7a: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000a7c: 2300 movs r3, #0
8000a7e: 62fb str r3, [r7, #44] ; 0x2c
HAL_GPIO_Init(BOOT1_GPIO_Port, &GPIO_InitStruct);
8000a80: f107 0324 add.w r3, r7, #36 ; 0x24
8000a84: 4619 mov r1, r3
8000a86: 481f ldr r0, [pc, #124] ; (8000b04 <MX_GPIO_Init+0x2fc>)
8000a88: f001 ff9e bl 80029c8 <HAL_GPIO_Init>
/*Configure GPIO pins : A10_Pin A11_Pin BA0_Pin BA1_Pin
SDCLK_Pin SDNCAS_Pin */
GPIO_InitStruct.Pin = A10_Pin|A11_Pin|BA0_Pin|BA1_Pin
8000a8c: f248 1333 movw r3, #33075 ; 0x8133
8000a90: 627b str r3, [r7, #36] ; 0x24
|SDCLK_Pin|SDNCAS_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000a92: 2302 movs r3, #2
8000a94: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000a96: 2300 movs r3, #0
8000a98: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000a9a: 2303 movs r3, #3
8000a9c: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
8000a9e: 230c movs r3, #12
8000aa0: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
8000aa2: f107 0324 add.w r3, r7, #36 ; 0x24
8000aa6: 4619 mov r1, r3
8000aa8: 4812 ldr r0, [pc, #72] ; (8000af4 <MX_GPIO_Init+0x2ec>)
8000aaa: f001 ff8d bl 80029c8 <HAL_GPIO_Init>
/*Configure GPIO pins : D4_Pin D5_Pin D6_Pin D7_Pin
D8_Pin D9_Pin D10_Pin D11_Pin
D12_Pin NBL0_Pin NBL1_Pin */
GPIO_InitStruct.Pin = D4_Pin|D5_Pin|D6_Pin|D7_Pin
8000aae: f64f 7383 movw r3, #65411 ; 0xff83
8000ab2: 627b str r3, [r7, #36] ; 0x24
|D8_Pin|D9_Pin|D10_Pin|D11_Pin
|D12_Pin|NBL0_Pin|NBL1_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000ab4: 2302 movs r3, #2
8000ab6: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000ab8: 2300 movs r3, #0
8000aba: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000abc: 2303 movs r3, #3
8000abe: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
8000ac0: 230c movs r3, #12
8000ac2: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
8000ac4: f107 0324 add.w r3, r7, #36 ; 0x24
8000ac8: 4619 mov r1, r3
8000aca: 480f ldr r0, [pc, #60] ; (8000b08 <MX_GPIO_Init+0x300>)
8000acc: f001 ff7c bl 80029c8 <HAL_GPIO_Init>
/*Configure GPIO pins : G4_Pin G5_Pin B6_Pin B7_Pin */
GPIO_InitStruct.Pin = G4_Pin|G5_Pin|B6_Pin|B7_Pin;
8000ad0: f44f 6370 mov.w r3, #3840 ; 0xf00
8000ad4: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000ad6: 2302 movs r3, #2
8000ad8: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000ada: 2300 movs r3, #0
8000adc: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000ade: 2300 movs r3, #0
8000ae0: 633b str r3, [r7, #48] ; 0x30
8000ae2: e013 b.n 8000b0c <MX_GPIO_Init+0x304>
8000ae4: 40023800 .word 0x40023800
8000ae8: 40020800 .word 0x40020800
8000aec: 40020000 .word 0x40020000
8000af0: 40020c00 .word 0x40020c00
8000af4: 40021800 .word 0x40021800
8000af8: 40021400 .word 0x40021400
8000afc: 10110000 .word 0x10110000
8000b00: 10120000 .word 0x10120000
8000b04: 40020400 .word 0x40020400
8000b08: 40021000 .word 0x40021000
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
8000b0c: 230e movs r3, #14
8000b0e: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8000b10: f107 0324 add.w r3, r7, #36 ; 0x24
8000b14: 4619 mov r1, r3
8000b16: 4877 ldr r0, [pc, #476] ; (8000cf4 <MX_GPIO_Init+0x4ec>)
8000b18: f001 ff56 bl 80029c8 <HAL_GPIO_Init>
/*Configure GPIO pins : OTG_HS_ID_Pin OTG_HS_DM_Pin OTG_HS_DP_Pin */
GPIO_InitStruct.Pin = OTG_HS_ID_Pin|OTG_HS_DM_Pin|OTG_HS_DP_Pin;
8000b1c: f44f 4350 mov.w r3, #53248 ; 0xd000
8000b20: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000b22: 2302 movs r3, #2
8000b24: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000b26: 2300 movs r3, #0
8000b28: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000b2a: 2300 movs r3, #0
8000b2c: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF12_OTG_HS_FS;
8000b2e: 230c movs r3, #12
8000b30: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8000b32: f107 0324 add.w r3, r7, #36 ; 0x24
8000b36: 4619 mov r1, r3
8000b38: 486e ldr r0, [pc, #440] ; (8000cf4 <MX_GPIO_Init+0x4ec>)
8000b3a: f001 ff45 bl 80029c8 <HAL_GPIO_Init>
/*Configure GPIO pin : VBUS_HS_Pin */
GPIO_InitStruct.Pin = VBUS_HS_Pin;
8000b3e: f44f 5300 mov.w r3, #8192 ; 0x2000
8000b42: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8000b44: 2300 movs r3, #0
8000b46: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000b48: 2300 movs r3, #0
8000b4a: 62fb str r3, [r7, #44] ; 0x2c
HAL_GPIO_Init(VBUS_HS_GPIO_Port, &GPIO_InitStruct);
8000b4c: f107 0324 add.w r3, r7, #36 ; 0x24
8000b50: 4619 mov r1, r3
8000b52: 4868 ldr r0, [pc, #416] ; (8000cf4 <MX_GPIO_Init+0x4ec>)
8000b54: f001 ff38 bl 80029c8 <HAL_GPIO_Init>
/*Configure GPIO pins : D13_Pin D14_Pin D15_Pin D0_Pin
D1_Pin D2_Pin D3_Pin */
GPIO_InitStruct.Pin = D13_Pin|D14_Pin|D15_Pin|D0_Pin
8000b58: f24c 7303 movw r3, #50947 ; 0xc703
8000b5c: 627b str r3, [r7, #36] ; 0x24
|D1_Pin|D2_Pin|D3_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000b5e: 2302 movs r3, #2
8000b60: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000b62: 2300 movs r3, #0
8000b64: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000b66: 2303 movs r3, #3
8000b68: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
8000b6a: 230c movs r3, #12
8000b6c: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
8000b6e: f107 0324 add.w r3, r7, #36 ; 0x24
8000b72: 4619 mov r1, r3
8000b74: 4860 ldr r0, [pc, #384] ; (8000cf8 <MX_GPIO_Init+0x4f0>)
8000b76: f001 ff27 bl 80029c8 <HAL_GPIO_Init>
/*Configure GPIO pin : TE_Pin */
GPIO_InitStruct.Pin = TE_Pin;
8000b7a: f44f 6300 mov.w r3, #2048 ; 0x800
8000b7e: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8000b80: 2300 movs r3, #0
8000b82: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000b84: 2300 movs r3, #0
8000b86: 62fb str r3, [r7, #44] ; 0x2c
HAL_GPIO_Init(TE_GPIO_Port, &GPIO_InitStruct);
8000b88: f107 0324 add.w r3, r7, #36 ; 0x24
8000b8c: 4619 mov r1, r3
8000b8e: 485a ldr r0, [pc, #360] ; (8000cf8 <MX_GPIO_Init+0x4f0>)
8000b90: f001 ff1a bl 80029c8 <HAL_GPIO_Init>
/*Configure GPIO pins : RDX_Pin WRX_DCX_Pin */
GPIO_InitStruct.Pin = RDX_Pin|WRX_DCX_Pin;
8000b94: f44f 5340 mov.w r3, #12288 ; 0x3000
8000b98: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000b9a: 2301 movs r3, #1
8000b9c: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000b9e: 2300 movs r3, #0
8000ba0: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000ba2: 2300 movs r3, #0
8000ba4: 633b str r3, [r7, #48] ; 0x30
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
8000ba6: f107 0324 add.w r3, r7, #36 ; 0x24
8000baa: 4619 mov r1, r3
8000bac: 4852 ldr r0, [pc, #328] ; (8000cf8 <MX_GPIO_Init+0x4f0>)
8000bae: f001 ff0b bl 80029c8 <HAL_GPIO_Init>
/*Configure GPIO pins : R7_Pin DOTCLK_Pin B3_Pin */
GPIO_InitStruct.Pin = R7_Pin|DOTCLK_Pin|B3_Pin;
8000bb2: f44f 630c mov.w r3, #2240 ; 0x8c0
8000bb6: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000bb8: 2302 movs r3, #2
8000bba: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000bbc: 2300 movs r3, #0
8000bbe: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000bc0: 2300 movs r3, #0
8000bc2: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
8000bc4: 230e movs r3, #14
8000bc6: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
8000bc8: f107 0324 add.w r3, r7, #36 ; 0x24
8000bcc: 4619 mov r1, r3
8000bce: 484b ldr r0, [pc, #300] ; (8000cfc <MX_GPIO_Init+0x4f4>)
8000bd0: f001 fefa bl 80029c8 <HAL_GPIO_Init>
/*Configure GPIO pins : HSYNC_Pin G6_Pin R2_Pin */
GPIO_InitStruct.Pin = HSYNC_Pin|G6_Pin|R2_Pin;
8000bd4: f44f 6398 mov.w r3, #1216 ; 0x4c0
8000bd8: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000bda: 2302 movs r3, #2
8000bdc: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000bde: 2300 movs r3, #0
8000be0: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000be2: 2300 movs r3, #0
8000be4: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
8000be6: 230e movs r3, #14
8000be8: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8000bea: f107 0324 add.w r3, r7, #36 ; 0x24
8000bee: 4619 mov r1, r3
8000bf0: 4843 ldr r0, [pc, #268] ; (8000d00 <MX_GPIO_Init+0x4f8>)
8000bf2: f001 fee9 bl 80029c8 <HAL_GPIO_Init>
/*Configure GPIO pin : I2C3_SDA_Pin */
GPIO_InitStruct.Pin = I2C3_SDA_Pin;
8000bf6: f44f 7300 mov.w r3, #512 ; 0x200
8000bfa: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
8000bfc: 2312 movs r3, #18
8000bfe: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_PULLUP;
8000c00: 2301 movs r3, #1
8000c02: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000c04: 2300 movs r3, #0
8000c06: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF4_I2C3;
8000c08: 2304 movs r3, #4
8000c0a: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(I2C3_SDA_GPIO_Port, &GPIO_InitStruct);
8000c0c: f107 0324 add.w r3, r7, #36 ; 0x24
8000c10: 4619 mov r1, r3
8000c12: 483b ldr r0, [pc, #236] ; (8000d00 <MX_GPIO_Init+0x4f8>)
8000c14: f001 fed8 bl 80029c8 <HAL_GPIO_Init>
/*Configure GPIO pin : I2C3_SCL_Pin */
GPIO_InitStruct.Pin = I2C3_SCL_Pin;
8000c18: f44f 7380 mov.w r3, #256 ; 0x100
8000c1c: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
8000c1e: 2312 movs r3, #18
8000c20: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_PULLUP;
8000c22: 2301 movs r3, #1
8000c24: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000c26: 2300 movs r3, #0
8000c28: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF4_I2C3;
8000c2a: 2304 movs r3, #4
8000c2c: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(I2C3_SCL_GPIO_Port, &GPIO_InitStruct);
8000c2e: f107 0324 add.w r3, r7, #36 ; 0x24
8000c32: 4619 mov r1, r3
8000c34: 4833 ldr r0, [pc, #204] ; (8000d04 <MX_GPIO_Init+0x4fc>)
8000c36: f001 fec7 bl 80029c8 <HAL_GPIO_Init>
/*Configure GPIO pins : STLINK_RX_Pin STLINK_TX_Pin */
GPIO_InitStruct.Pin = STLINK_RX_Pin|STLINK_TX_Pin;
8000c3a: f44f 63c0 mov.w r3, #1536 ; 0x600
8000c3e: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000c40: 2302 movs r3, #2
8000c42: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000c44: 2300 movs r3, #0
8000c46: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000c48: 2303 movs r3, #3
8000c4a: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
8000c4c: 2307 movs r3, #7
8000c4e: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000c50: f107 0324 add.w r3, r7, #36 ; 0x24
8000c54: 4619 mov r1, r3
8000c56: 482b ldr r0, [pc, #172] ; (8000d04 <MX_GPIO_Init+0x4fc>)
8000c58: f001 feb6 bl 80029c8 <HAL_GPIO_Init>
/*Configure GPIO pins : G7_Pin B2_Pin */
GPIO_InitStruct.Pin = G7_Pin|B2_Pin;
8000c5c: 2348 movs r3, #72 ; 0x48
8000c5e: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000c60: 2302 movs r3, #2
8000c62: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000c64: 2300 movs r3, #0
8000c66: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000c68: 2300 movs r3, #0
8000c6a: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
8000c6c: 230e movs r3, #14
8000c6e: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
8000c70: f107 0324 add.w r3, r7, #36 ; 0x24
8000c74: 4619 mov r1, r3
8000c76: 4820 ldr r0, [pc, #128] ; (8000cf8 <MX_GPIO_Init+0x4f0>)
8000c78: f001 fea6 bl 80029c8 <HAL_GPIO_Init>
/*Configure GPIO pins : G3_Pin B4_Pin */
GPIO_InitStruct.Pin = G3_Pin|B4_Pin;
8000c7c: f44f 53a0 mov.w r3, #5120 ; 0x1400
8000c80: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000c82: 2302 movs r3, #2
8000c84: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000c86: 2300 movs r3, #0
8000c88: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000c8a: 2300 movs r3, #0
8000c8c: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF9_LTDC;
8000c8e: 2309 movs r3, #9
8000c90: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
8000c92: f107 0324 add.w r3, r7, #36 ; 0x24
8000c96: 4619 mov r1, r3
8000c98: 4818 ldr r0, [pc, #96] ; (8000cfc <MX_GPIO_Init+0x4f4>)
8000c9a: f001 fe95 bl 80029c8 <HAL_GPIO_Init>
/*Configure GPIO pins : LD3_Pin LD4_Pin */
GPIO_InitStruct.Pin = LD3_Pin|LD4_Pin;
8000c9e: f44f 43c0 mov.w r3, #24576 ; 0x6000
8000ca2: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000ca4: 2301 movs r3, #1
8000ca6: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000ca8: 2300 movs r3, #0
8000caa: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000cac: 2300 movs r3, #0
8000cae: 633b str r3, [r7, #48] ; 0x30
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
8000cb0: f107 0324 add.w r3, r7, #36 ; 0x24
8000cb4: 4619 mov r1, r3
8000cb6: 4811 ldr r0, [pc, #68] ; (8000cfc <MX_GPIO_Init+0x4f4>)
8000cb8: f001 fe86 bl 80029c8 <HAL_GPIO_Init>
/*Configure GPIO pins : SDCKE1_Pin SDNE1_Pin */
GPIO_InitStruct.Pin = SDCKE1_Pin|SDNE1_Pin;
8000cbc: 2360 movs r3, #96 ; 0x60
8000cbe: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000cc0: 2302 movs r3, #2
8000cc2: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000cc4: 2300 movs r3, #0
8000cc6: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000cc8: 2303 movs r3, #3
8000cca: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
8000ccc: 230c movs r3, #12
8000cce: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8000cd0: f107 0324 add.w r3, r7, #36 ; 0x24
8000cd4: 4619 mov r1, r3
8000cd6: 4807 ldr r0, [pc, #28] ; (8000cf4 <MX_GPIO_Init+0x4ec>)
8000cd8: f001 fe76 bl 80029c8 <HAL_GPIO_Init>
/* EXTI interrupt init*/
HAL_NVIC_SetPriority(EXTI0_IRQn, 0, 0);
8000cdc: 2200 movs r2, #0
8000cde: 2100 movs r1, #0
8000ce0: 2006 movs r0, #6
8000ce2: f001 fe18 bl 8002916 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(EXTI0_IRQn);
8000ce6: 2006 movs r0, #6
8000ce8: f001 fe31 bl 800294e <HAL_NVIC_EnableIRQ>
}
8000cec: bf00 nop
8000cee: 3738 adds r7, #56 ; 0x38
8000cf0: 46bd mov sp, r7
8000cf2: bd80 pop {r7, pc}
8000cf4: 40020400 .word 0x40020400
8000cf8: 40020c00 .word 0x40020c00
8000cfc: 40021800 .word 0x40021800
8000d00: 40020800 .word 0x40020800
8000d04: 40020000 .word 0x40020000
08000d08 <getSoundLevel>:
/* USER CODE BEGIN 4 */
uint8_t getSoundLevel(void){
8000d08: b580 push {r7, lr}
8000d0a: b086 sub sp, #24
8000d0c: af00 add r7, sp, #0
static uint8_t multiplier = 3;
static uint16_t averagedDifferences = 0;
uint16_t returnValue;
uint8_t samples[16];
uint16_t sumOfDifferences = 0;
8000d0e: 2300 movs r3, #0
8000d10: 82bb strh r3, [r7, #20]
for(uint8_t i = 0; i < sizeof(samples); ++i){
8000d12: 2300 movs r3, #0
8000d14: 74fb strb r3, [r7, #19]
8000d16: e017 b.n 8000d48 <getSoundLevel+0x40>
HAL_Delay(1);
8000d18: 2001 movs r0, #1
8000d1a: f001 f935 bl 8001f88 <HAL_Delay>
HAL_ADC_Start(&hadc3);
8000d1e: 483e ldr r0, [pc, #248] ; (8000e18 <getSoundLevel+0x110>)
8000d20: f001 f998 bl 8002054 <HAL_ADC_Start>
HAL_ADC_PollForConversion(&hadc3, (uint32_t) 20);
8000d24: 2114 movs r1, #20
8000d26: 483c ldr r0, [pc, #240] ; (8000e18 <getSoundLevel+0x110>)
8000d28: f001 fa5a bl 80021e0 <HAL_ADC_PollForConversion>
samples[i] = HAL_ADC_GetValue(&hadc3);
8000d2c: 483a ldr r0, [pc, #232] ; (8000e18 <getSoundLevel+0x110>)
8000d2e: f001 fadb bl 80022e8 <HAL_ADC_GetValue>
8000d32: 4602 mov r2, r0
8000d34: 7cfb ldrb r3, [r7, #19]
8000d36: b2d2 uxtb r2, r2
8000d38: f107 0118 add.w r1, r7, #24
8000d3c: 440b add r3, r1
8000d3e: f803 2c18 strb.w r2, [r3, #-24]
for(uint8_t i = 0; i < sizeof(samples); ++i){
8000d42: 7cfb ldrb r3, [r7, #19]
8000d44: 3301 adds r3, #1
8000d46: 74fb strb r3, [r7, #19]
8000d48: 7cfb ldrb r3, [r7, #19]
8000d4a: 2b0f cmp r3, #15
8000d4c: d9e4 bls.n 8000d18 <getSoundLevel+0x10>
}
for(uint8_t i = 0; i < sizeof(samples) - 1; ++i){
8000d4e: 2300 movs r3, #0
8000d50: 74bb strb r3, [r7, #18]
8000d52: e018 b.n 8000d86 <getSoundLevel+0x7e>
sumOfDifferences += abs(samples[i] - samples[i + 1]);
8000d54: 7cbb ldrb r3, [r7, #18]
8000d56: f107 0218 add.w r2, r7, #24
8000d5a: 4413 add r3, r2
8000d5c: f813 3c18 ldrb.w r3, [r3, #-24]
8000d60: 461a mov r2, r3
8000d62: 7cbb ldrb r3, [r7, #18]
8000d64: 3301 adds r3, #1
8000d66: f107 0118 add.w r1, r7, #24
8000d6a: 440b add r3, r1
8000d6c: f813 3c18 ldrb.w r3, [r3, #-24]
8000d70: 1ad3 subs r3, r2, r3
8000d72: 2b00 cmp r3, #0
8000d74: bfb8 it lt
8000d76: 425b neglt r3, r3
8000d78: b29a uxth r2, r3
8000d7a: 8abb ldrh r3, [r7, #20]
8000d7c: 4413 add r3, r2
8000d7e: 82bb strh r3, [r7, #20]
for(uint8_t i = 0; i < sizeof(samples) - 1; ++i){
8000d80: 7cbb ldrb r3, [r7, #18]
8000d82: 3301 adds r3, #1
8000d84: 74bb strb r3, [r7, #18]
8000d86: 7cbb ldrb r3, [r7, #18]
8000d88: 2b0e cmp r3, #14
8000d8a: d9e3 bls.n 8000d54 <getSoundLevel+0x4c>
}
averagedDifferences += ((int32_t) sumOfDifferences - (int32_t) averagedDifferences) / 4;
8000d8c: 8abb ldrh r3, [r7, #20]
8000d8e: 4a23 ldr r2, [pc, #140] ; (8000e1c <getSoundLevel+0x114>)
8000d90: 8812 ldrh r2, [r2, #0]
8000d92: 1a9b subs r3, r3, r2
8000d94: 2b00 cmp r3, #0
8000d96: da00 bge.n 8000d9a <getSoundLevel+0x92>
8000d98: 3303 adds r3, #3
8000d9a: 109b asrs r3, r3, #2
8000d9c: b29a uxth r2, r3
8000d9e: 4b1f ldr r3, [pc, #124] ; (8000e1c <getSoundLevel+0x114>)
8000da0: 881b ldrh r3, [r3, #0]
8000da2: 4413 add r3, r2
8000da4: b29a uxth r2, r3
8000da6: 4b1d ldr r3, [pc, #116] ; (8000e1c <getSoundLevel+0x114>)
8000da8: 801a strh r2, [r3, #0]
if(averagedDifferences < prescale_DownShift){returnValue = 0;}else{returnValue = averagedDifferences - prescale_DownShift;}
8000daa: 4b1d ldr r3, [pc, #116] ; (8000e20 <getSoundLevel+0x118>)
8000dac: 781b ldrb r3, [r3, #0]
8000dae: b29a uxth r2, r3
8000db0: 4b1a ldr r3, [pc, #104] ; (8000e1c <getSoundLevel+0x114>)
8000db2: 881b ldrh r3, [r3, #0]
8000db4: 429a cmp r2, r3
8000db6: d902 bls.n 8000dbe <getSoundLevel+0xb6>
8000db8: 2300 movs r3, #0
8000dba: 82fb strh r3, [r7, #22]
8000dbc: e006 b.n 8000dcc <getSoundLevel+0xc4>
8000dbe: 4b17 ldr r3, [pc, #92] ; (8000e1c <getSoundLevel+0x114>)
8000dc0: 881a ldrh r2, [r3, #0]
8000dc2: 4b17 ldr r3, [pc, #92] ; (8000e20 <getSoundLevel+0x118>)
8000dc4: 781b ldrb r3, [r3, #0]
8000dc6: b29b uxth r3, r3
8000dc8: 1ad3 subs r3, r2, r3
8000dca: 82fb strh r3, [r7, #22]
returnValue = (returnValue / divisor) * multiplier;
8000dcc: 8afb ldrh r3, [r7, #22]
8000dce: 4a15 ldr r2, [pc, #84] ; (8000e24 <getSoundLevel+0x11c>)
8000dd0: 7812 ldrb r2, [r2, #0]
8000dd2: fb93 f3f2 sdiv r3, r3, r2
8000dd6: b29a uxth r2, r3
8000dd8: 4b13 ldr r3, [pc, #76] ; (8000e28 <getSoundLevel+0x120>)
8000dda: 781b ldrb r3, [r3, #0]
8000ddc: b29b uxth r3, r3
8000dde: fb12 f303 smulbb r3, r2, r3
8000de2: 82fb strh r3, [r7, #22]
if(returnValue < postscale_DownShift){returnValue = 0;}else{returnValue -= postscale_DownShift;}
8000de4: 4b11 ldr r3, [pc, #68] ; (8000e2c <getSoundLevel+0x124>)
8000de6: 781b ldrb r3, [r3, #0]
8000de8: b29b uxth r3, r3
8000dea: 8afa ldrh r2, [r7, #22]
8000dec: 429a cmp r2, r3
8000dee: d202 bcs.n 8000df6 <getSoundLevel+0xee>
8000df0: 2300 movs r3, #0
8000df2: 82fb strh r3, [r7, #22]
8000df4: e005 b.n 8000e02 <getSoundLevel+0xfa>
8000df6: 4b0d ldr r3, [pc, #52] ; (8000e2c <getSoundLevel+0x124>)
8000df8: 781b ldrb r3, [r3, #0]
8000dfa: b29b uxth r3, r3
8000dfc: 8afa ldrh r2, [r7, #22]
8000dfe: 1ad3 subs r3, r2, r3
8000e00: 82fb strh r3, [r7, #22]
if(returnValue >= 0xFF){return 0xFF;} else{return returnValue;}
8000e02: 8afb ldrh r3, [r7, #22]
8000e04: 2bfe cmp r3, #254 ; 0xfe
8000e06: d901 bls.n 8000e0c <getSoundLevel+0x104>
8000e08: 23ff movs r3, #255 ; 0xff
8000e0a: e001 b.n 8000e10 <getSoundLevel+0x108>
8000e0c: 8afb ldrh r3, [r7, #22]
8000e0e: b2db uxtb r3, r3
}
8000e10: 4618 mov r0, r3
8000e12: 3718 adds r7, #24
8000e14: 46bd mov sp, r7
8000e16: bd80 pop {r7, pc}
8000e18: 200003b8 .word 0x200003b8
8000e1c: 200003a6 .word 0x200003a6
8000e20: 20000000 .word 0x20000000
8000e24: 20000001 .word 0x20000001
8000e28: 20000002 .word 0x20000002
8000e2c: 200003a8 .word 0x200003a8
08000e30 <LEDDesign_Off>:
void LEDDesign_Off(void){
8000e30: b480 push {r7}
8000e32: b083 sub sp, #12
8000e34: af00 add r7, sp, #0
for(uint8_t i = 0; i < 64; ++i){
8000e36: 2300 movs r3, #0
8000e38: 71fb strb r3, [r7, #7]
8000e3a: e015 b.n 8000e68 <LEDDesign_Off+0x38>
for(uint8_t j = 0; j < 3; ++j){
8000e3c: 2300 movs r3, #0
8000e3e: 71bb strb r3, [r7, #6]
8000e40: e00c b.n 8000e5c <LEDDesign_Off+0x2c>
LEDData[i][j] = 0x00;
8000e42: 79fa ldrb r2, [r7, #7]
8000e44: 79b9 ldrb r1, [r7, #6]
8000e46: 480d ldr r0, [pc, #52] ; (8000e7c <LEDDesign_Off+0x4c>)
8000e48: 4613 mov r3, r2
8000e4a: 005b lsls r3, r3, #1
8000e4c: 4413 add r3, r2
8000e4e: 4403 add r3, r0
8000e50: 440b add r3, r1
8000e52: 2200 movs r2, #0
8000e54: 701a strb r2, [r3, #0]
for(uint8_t j = 0; j < 3; ++j){
8000e56: 79bb ldrb r3, [r7, #6]
8000e58: 3301 adds r3, #1
8000e5a: 71bb strb r3, [r7, #6]
8000e5c: 79bb ldrb r3, [r7, #6]
8000e5e: 2b02 cmp r3, #2
8000e60: d9ef bls.n 8000e42 <LEDDesign_Off+0x12>
for(uint8_t i = 0; i < 64; ++i){
8000e62: 79fb ldrb r3, [r7, #7]
8000e64: 3301 adds r3, #1
8000e66: 71fb strb r3, [r7, #7]
8000e68: 79fb ldrb r3, [r7, #7]
8000e6a: 2b3f cmp r3, #63 ; 0x3f
8000e6c: d9e6 bls.n 8000e3c <LEDDesign_Off+0xc>
}
}
}
8000e6e: bf00 nop
8000e70: 370c adds r7, #12
8000e72: 46bd mov sp, r7
8000e74: f85d 7b04 ldr.w r7, [sp], #4
8000e78: 4770 bx lr
8000e7a: bf00 nop
8000e7c: 20000094 .word 0x20000094
08000e80 <LEDDesign_ColorWhite>:
void LEDDesign_ColorWhite(void){
8000e80: b480 push {r7}
8000e82: b083 sub sp, #12
8000e84: af00 add r7, sp, #0
for(uint8_t i = 0; i < 64; ++i){
8000e86: 2300 movs r3, #0
8000e88: 71fb strb r3, [r7, #7]
8000e8a: e015 b.n 8000eb8 <LEDDesign_ColorWhite+0x38>
for(uint8_t j = 0; j < 3; ++j){
8000e8c: 2300 movs r3, #0
8000e8e: 71bb strb r3, [r7, #6]
8000e90: e00c b.n 8000eac <LEDDesign_ColorWhite+0x2c>
LEDData[i][j] = 0xFF;
8000e92: 79fa ldrb r2, [r7, #7]
8000e94: 79b9 ldrb r1, [r7, #6]
8000e96: 480d ldr r0, [pc, #52] ; (8000ecc <LEDDesign_ColorWhite+0x4c>)
8000e98: 4613 mov r3, r2
8000e9a: 005b lsls r3, r3, #1
8000e9c: 4413 add r3, r2
8000e9e: 4403 add r3, r0
8000ea0: 440b add r3, r1
8000ea2: 22ff movs r2, #255 ; 0xff
8000ea4: 701a strb r2, [r3, #0]
for(uint8_t j = 0; j < 3; ++j){
8000ea6: 79bb ldrb r3, [r7, #6]
8000ea8: 3301 adds r3, #1
8000eaa: 71bb strb r3, [r7, #6]
8000eac: 79bb ldrb r3, [r7, #6]
8000eae: 2b02 cmp r3, #2
8000eb0: d9ef bls.n 8000e92 <LEDDesign_ColorWhite+0x12>
for(uint8_t i = 0; i < 64; ++i){
8000eb2: 79fb ldrb r3, [r7, #7]
8000eb4: 3301 adds r3, #1
8000eb6: 71fb strb r3, [r7, #7]
8000eb8: 79fb ldrb r3, [r7, #7]
8000eba: 2b3f cmp r3, #63 ; 0x3f
8000ebc: d9e6 bls.n 8000e8c <LEDDesign_ColorWhite+0xc>
}
}
}
8000ebe: bf00 nop
8000ec0: 370c adds r7, #12
8000ec2: 46bd mov sp, r7
8000ec4: f85d 7b04 ldr.w r7, [sp], #4
8000ec8: 4770 bx lr
8000eca: bf00 nop
8000ecc: 20000094 .word 0x20000094
08000ed0 <LEDDesign_ColorBlue>:
void LEDDesign_ColorBlue(void){
8000ed0: b480 push {r7}
8000ed2: b083 sub sp, #12
8000ed4: af00 add r7, sp, #0
for(uint8_t i = 0; i < 64; ++i){
8000ed6: 2300 movs r3, #0
8000ed8: 71fb strb r3, [r7, #7]
8000eda: e00a b.n 8000ef2 <LEDDesign_ColorBlue+0x22>
LEDData[i][0] = 0x00;
8000edc: 79fa ldrb r2, [r7, #7]
8000ede: 491b ldr r1, [pc, #108] ; (8000f4c <LEDDesign_ColorBlue+0x7c>)
8000ee0: 4613 mov r3, r2
8000ee2: 005b lsls r3, r3, #1
8000ee4: 4413 add r3, r2
8000ee6: 440b add r3, r1
8000ee8: 2200 movs r2, #0
8000eea: 701a strb r2, [r3, #0]
for(uint8_t i = 0; i < 64; ++i){
8000eec: 79fb ldrb r3, [r7, #7]
8000eee: 3301 adds r3, #1
8000ef0: 71fb strb r3, [r7, #7]
8000ef2: 79fb ldrb r3, [r7, #7]
8000ef4: 2b3f cmp r3, #63 ; 0x3f
8000ef6: d9f1 bls.n 8000edc <LEDDesign_ColorBlue+0xc>
}
for(uint8_t i = 0; i < 64; ++i){
8000ef8: 2300 movs r3, #0
8000efa: 71bb strb r3, [r7, #6]
8000efc: e00b b.n 8000f16 <LEDDesign_ColorBlue+0x46>
LEDData[i][1] = 0x00;
8000efe: 79ba ldrb r2, [r7, #6]
8000f00: 4912 ldr r1, [pc, #72] ; (8000f4c <LEDDesign_ColorBlue+0x7c>)
8000f02: 4613 mov r3, r2
8000f04: 005b lsls r3, r3, #1
8000f06: 4413 add r3, r2
8000f08: 440b add r3, r1
8000f0a: 3301 adds r3, #1
8000f0c: 2200 movs r2, #0
8000f0e: 701a strb r2, [r3, #0]
for(uint8_t i = 0; i < 64; ++i){
8000f10: 79bb ldrb r3, [r7, #6]
8000f12: 3301 adds r3, #1
8000f14: 71bb strb r3, [r7, #6]
8000f16: 79bb ldrb r3, [r7, #6]
8000f18: 2b3f cmp r3, #63 ; 0x3f
8000f1a: d9f0 bls.n 8000efe <LEDDesign_ColorBlue+0x2e>
}
for(uint8_t i = 0; i < 64; ++i){
8000f1c: 2300 movs r3, #0
8000f1e: 717b strb r3, [r7, #5]
8000f20: e00b b.n 8000f3a <LEDDesign_ColorBlue+0x6a>
LEDData[i][2] = 0xFF;
8000f22: 797a ldrb r2, [r7, #5]
8000f24: 4909 ldr r1, [pc, #36] ; (8000f4c <LEDDesign_ColorBlue+0x7c>)
8000f26: 4613 mov r3, r2
8000f28: 005b lsls r3, r3, #1
8000f2a: 4413 add r3, r2
8000f2c: 440b add r3, r1
8000f2e: 3302 adds r3, #2
8000f30: 22ff movs r2, #255 ; 0xff
8000f32: 701a strb r2, [r3, #0]
for(uint8_t i = 0; i < 64; ++i){
8000f34: 797b ldrb r3, [r7, #5]
8000f36: 3301 adds r3, #1
8000f38: 717b strb r3, [r7, #5]
8000f3a: 797b ldrb r3, [r7, #5]
8000f3c: 2b3f cmp r3, #63 ; 0x3f
8000f3e: d9f0 bls.n 8000f22 <LEDDesign_ColorBlue+0x52>
}
}
8000f40: bf00 nop
8000f42: 370c adds r7, #12
8000f44: 46bd mov sp, r7
8000f46: f85d 7b04 ldr.w r7, [sp], #4
8000f4a: 4770 bx lr
8000f4c: 20000094 .word 0x20000094
08000f50 <LEDDesign_ColorGreen>:
void LEDDesign_ColorGreen(void){
8000f50: b480 push {r7}
8000f52: b083 sub sp, #12
8000f54: af00 add r7, sp, #0
for(uint8_t i = 0; i < 64; ++i){
8000f56: 2300 movs r3, #0
8000f58: 71fb strb r3, [r7, #7]
8000f5a: e00a b.n 8000f72 <LEDDesign_ColorGreen+0x22>
LEDData[i][0] = 0xFF;
8000f5c: 79fa ldrb r2, [r7, #7]
8000f5e: 491b ldr r1, [pc, #108] ; (8000fcc <LEDDesign_ColorGreen+0x7c>)
8000f60: 4613 mov r3, r2
8000f62: 005b lsls r3, r3, #1
8000f64: 4413 add r3, r2
8000f66: 440b add r3, r1
8000f68: 22ff movs r2, #255 ; 0xff
8000f6a: 701a strb r2, [r3, #0]
for(uint8_t i = 0; i < 64; ++i){
8000f6c: 79fb ldrb r3, [r7, #7]
8000f6e: 3301 adds r3, #1
8000f70: 71fb strb r3, [r7, #7]
8000f72: 79fb ldrb r3, [r7, #7]
8000f74: 2b3f cmp r3, #63 ; 0x3f
8000f76: d9f1 bls.n 8000f5c <LEDDesign_ColorGreen+0xc>
}
for(uint8_t i = 0; i < 64; ++i){
8000f78: 2300 movs r3, #0
8000f7a: 71bb strb r3, [r7, #6]
8000f7c: e00b b.n 8000f96 <LEDDesign_ColorGreen+0x46>
LEDData[i][1] = 0x00;
8000f7e: 79ba ldrb r2, [r7, #6]
8000f80: 4912 ldr r1, [pc, #72] ; (8000fcc <LEDDesign_ColorGreen+0x7c>)
8000f82: 4613 mov r3, r2
8000f84: 005b lsls r3, r3, #1
8000f86: 4413 add r3, r2
8000f88: 440b add r3, r1
8000f8a: 3301 adds r3, #1
8000f8c: 2200 movs r2, #0
8000f8e: 701a strb r2, [r3, #0]
for(uint8_t i = 0; i < 64; ++i){
8000f90: 79bb ldrb r3, [r7, #6]
8000f92: 3301 adds r3, #1
8000f94: 71bb strb r3, [r7, #6]
8000f96: 79bb ldrb r3, [r7, #6]
8000f98: 2b3f cmp r3, #63 ; 0x3f
8000f9a: d9f0 bls.n 8000f7e <LEDDesign_ColorGreen+0x2e>
}
for(uint8_t i = 0; i < 64; ++i){
8000f9c: 2300 movs r3, #0
8000f9e: 717b strb r3, [r7, #5]
8000fa0: e00b b.n 8000fba <LEDDesign_ColorGreen+0x6a>
LEDData[i][2] = 0x00;
8000fa2: 797a ldrb r2, [r7, #5]
8000fa4: 4909 ldr r1, [pc, #36] ; (8000fcc <LEDDesign_ColorGreen+0x7c>)
8000fa6: 4613 mov r3, r2
8000fa8: 005b lsls r3, r3, #1
8000faa: 4413 add r3, r2
8000fac: 440b add r3, r1
8000fae: 3302 adds r3, #2
8000fb0: 2200 movs r2, #0
8000fb2: 701a strb r2, [r3, #0]
for(uint8_t i = 0; i < 64; ++i){
8000fb4: 797b ldrb r3, [r7, #5]
8000fb6: 3301 adds r3, #1
8000fb8: 717b strb r3, [r7, #5]
8000fba: 797b ldrb r3, [r7, #5]
8000fbc: 2b3f cmp r3, #63 ; 0x3f
8000fbe: d9f0 bls.n 8000fa2 <LEDDesign_ColorGreen+0x52>
}
}
8000fc0: bf00 nop
8000fc2: 370c adds r7, #12
8000fc4: 46bd mov sp, r7
8000fc6: f85d 7b04 ldr.w r7, [sp], #4
8000fca: 4770 bx lr
8000fcc: 20000094 .word 0x20000094
08000fd0 <LEDDesign_ColorRed>:
void LEDDesign_ColorRed(void){
8000fd0: b480 push {r7}
8000fd2: b083 sub sp, #12
8000fd4: af00 add r7, sp, #0
for(uint8_t i = 0; i < 64; ++i){
8000fd6: 2300 movs r3, #0
8000fd8: 71fb strb r3, [r7, #7]
8000fda: e00a b.n 8000ff2 <LEDDesign_ColorRed+0x22>
LEDData[i][0] = 0x00;
8000fdc: 79fa ldrb r2, [r7, #7]
8000fde: 491b ldr r1, [pc, #108] ; (800104c <LEDDesign_ColorRed+0x7c>)
8000fe0: 4613 mov r3, r2
8000fe2: 005b lsls r3, r3, #1
8000fe4: 4413 add r3, r2
8000fe6: 440b add r3, r1
8000fe8: 2200 movs r2, #0
8000fea: 701a strb r2, [r3, #0]
for(uint8_t i = 0; i < 64; ++i){
8000fec: 79fb ldrb r3, [r7, #7]
8000fee: 3301 adds r3, #1
8000ff0: 71fb strb r3, [r7, #7]
8000ff2: 79fb ldrb r3, [r7, #7]
8000ff4: 2b3f cmp r3, #63 ; 0x3f
8000ff6: d9f1 bls.n 8000fdc <LEDDesign_ColorRed+0xc>
}
for(uint8_t i = 0; i < 64; ++i){
8000ff8: 2300 movs r3, #0
8000ffa: 71bb strb r3, [r7, #6]
8000ffc: e00b b.n 8001016 <LEDDesign_ColorRed+0x46>
LEDData[i][1] = 0xFF;
8000ffe: 79ba ldrb r2, [r7, #6]
8001000: 4912 ldr r1, [pc, #72] ; (800104c <LEDDesign_ColorRed+0x7c>)
8001002: 4613 mov r3, r2
8001004: 005b lsls r3, r3, #1
8001006: 4413 add r3, r2
8001008: 440b add r3, r1
800100a: 3301 adds r3, #1
800100c: 22ff movs r2, #255 ; 0xff
800100e: 701a strb r2, [r3, #0]
for(uint8_t i = 0; i < 64; ++i){
8001010: 79bb ldrb r3, [r7, #6]
8001012: 3301 adds r3, #1
8001014: 71bb strb r3, [r7, #6]
8001016: 79bb ldrb r3, [r7, #6]
8001018: 2b3f cmp r3, #63 ; 0x3f
800101a: d9f0 bls.n 8000ffe <LEDDesign_ColorRed+0x2e>
}
for(uint8_t i = 0; i < 64; ++i){
800101c: 2300 movs r3, #0
800101e: 717b strb r3, [r7, #5]
8001020: e00b b.n 800103a <LEDDesign_ColorRed+0x6a>
LEDData[i][2] = 0x00;
8001022: 797a ldrb r2, [r7, #5]
8001024: 4909 ldr r1, [pc, #36] ; (800104c <LEDDesign_ColorRed+0x7c>)
8001026: 4613 mov r3, r2
8001028: 005b lsls r3, r3, #1
800102a: 4413 add r3, r2
800102c: 440b add r3, r1
800102e: 3302 adds r3, #2
8001030: 2200 movs r2, #0
8001032: 701a strb r2, [r3, #0]
for(uint8_t i = 0; i < 64; ++i){
8001034: 797b ldrb r3, [r7, #5]
8001036: 3301 adds r3, #1
8001038: 717b strb r3, [r7, #5]
800103a: 797b ldrb r3, [r7, #5]
800103c: 2b3f cmp r3, #63 ; 0x3f
800103e: d9f0 bls.n 8001022 <LEDDesign_ColorRed+0x52>
}
}
8001040: bf00 nop
8001042: 370c adds r7, #12
8001044: 46bd mov sp, r7
8001046: f85d 7b04 ldr.w r7, [sp], #4
800104a: 4770 bx lr
800104c: 20000094 .word 0x20000094
08001050 <LEDDesign_Crazy>:
void LEDDesign_Crazy(void){
8001050: b590 push {r4, r7, lr}
8001052: b085 sub sp, #20
8001054: af00 add r7, sp, #0
HAL_Delay(50);
8001056: 2032 movs r0, #50 ; 0x32
8001058: f000 ff96 bl 8001f88 <HAL_Delay>
for(uint8_t i = 0; i < 64; ++i){
800105c: 2300 movs r3, #0
800105e: 73fb strb r3, [r7, #15]
8001060: e029 b.n 80010b6 <LEDDesign_Crazy+0x66>
for(uint8_t j = 0; j < 3; ++j){
8001062: 2300 movs r3, #0
8001064: 73bb strb r3, [r7, #14]
8001066: e020 b.n 80010aa <LEDDesign_Crazy+0x5a>
LEDData[i][j] = (uint8_t) (0xFF * (((float) rand()) / RAND_MAX));
8001068: f003 f958 bl 800431c <rand>
800106c: ee07 0a90 vmov s15, r0
8001070: eeb8 7ae7 vcvt.f32.s32 s14, s15
8001074: eddf 6a13 vldr s13, [pc, #76] ; 80010c4 <LEDDesign_Crazy+0x74>
8001078: eec7 7a26 vdiv.f32 s15, s14, s13
800107c: ed9f 7a12 vldr s14, [pc, #72] ; 80010c8 <LEDDesign_Crazy+0x78>
8001080: ee67 7a87 vmul.f32 s15, s15, s14
8001084: 7bfa ldrb r2, [r7, #15]
8001086: 7bb9 ldrb r1, [r7, #14]
8001088: eefc 7ae7 vcvt.u32.f32 s15, s15
800108c: edc7 7a01 vstr s15, [r7, #4]
8001090: 793b ldrb r3, [r7, #4]
8001092: b2dc uxtb r4, r3
8001094: 480d ldr r0, [pc, #52] ; (80010cc <LEDDesign_Crazy+0x7c>)
8001096: 4613 mov r3, r2
8001098: 005b lsls r3, r3, #1
800109a: 4413 add r3, r2
800109c: 4403 add r3, r0
800109e: 440b add r3, r1
80010a0: 4622 mov r2, r4
80010a2: 701a strb r2, [r3, #0]
for(uint8_t j = 0; j < 3; ++j){
80010a4: 7bbb ldrb r3, [r7, #14]
80010a6: 3301 adds r3, #1
80010a8: 73bb strb r3, [r7, #14]
80010aa: 7bbb ldrb r3, [r7, #14]
80010ac: 2b02 cmp r3, #2
80010ae: d9db bls.n 8001068 <LEDDesign_Crazy+0x18>
for(uint8_t i = 0; i < 64; ++i){
80010b0: 7bfb ldrb r3, [r7, #15]
80010b2: 3301 adds r3, #1
80010b4: 73fb strb r3, [r7, #15]
80010b6: 7bfb ldrb r3, [r7, #15]
80010b8: 2b3f cmp r3, #63 ; 0x3f
80010ba: d9d2 bls.n 8001062 <LEDDesign_Crazy+0x12>
}
}
}
80010bc: bf00 nop
80010be: 3714 adds r7, #20
80010c0: 46bd mov sp, r7
80010c2: bd90 pop {r4, r7, pc}
80010c4: 4f000000 .word 0x4f000000
80010c8: 437f0000 .word 0x437f0000
80010cc: 20000094 .word 0x20000094
080010d0 <LEDDesign_Smile>:
void LEDDesign_Smile(void){
80010d0: b580 push {r7, lr}
80010d2: b082 sub sp, #8
80010d4: af00 add r7, sp, #0
uint8_t currentSoundLevel = getSoundLevel();
80010d6: f7ff fe17 bl 8000d08 <getSoundLevel>
80010da: 4603 mov r3, r0
80010dc: 71fb strb r3, [r7, #7]
LEDData[0][0] = currentSoundLevel;
80010de: 4ac8 ldr r2, [pc, #800] ; (8001400 <LEDDesign_Smile+0x330>)
80010e0: 79fb ldrb r3, [r7, #7]
80010e2: 7013 strb r3, [r2, #0]
LEDData[0][1] = currentSoundLevel;
80010e4: 4ac6 ldr r2, [pc, #792] ; (8001400 <LEDDesign_Smile+0x330>)
80010e6: 79fb ldrb r3, [r7, #7]
80010e8: 7053 strb r3, [r2, #1]
LEDData[0][2] = currentSoundLevel;
80010ea: 4ac5 ldr r2, [pc, #788] ; (8001400 <LEDDesign_Smile+0x330>)
80010ec: 79fb ldrb r3, [r7, #7]
80010ee: 7093 strb r3, [r2, #2]
LEDData[1][0] = 0x00;
80010f0: 4bc3 ldr r3, [pc, #780] ; (8001400 <LEDDesign_Smile+0x330>)
80010f2: 2200 movs r2, #0
80010f4: 70da strb r2, [r3, #3]
LEDData[1][1] = 0x00;
80010f6: 4bc2 ldr r3, [pc, #776] ; (8001400 <LEDDesign_Smile+0x330>)
80010f8: 2200 movs r2, #0
80010fa: 711a strb r2, [r3, #4]
LEDData[1][2] = 0x00;
80010fc: 4bc0 ldr r3, [pc, #768] ; (8001400 <LEDDesign_Smile+0x330>)
80010fe: 2200 movs r2, #0
8001100: 715a strb r2, [r3, #5]
LEDData[2][0] = 0x00;
8001102: 4bbf ldr r3, [pc, #764] ; (8001400 <LEDDesign_Smile+0x330>)
8001104: 2200 movs r2, #0
8001106: 719a strb r2, [r3, #6]
LEDData[2][1] = 0x00;
8001108: 4bbd ldr r3, [pc, #756] ; (8001400 <LEDDesign_Smile+0x330>)
800110a: 2200 movs r2, #0
800110c: 71da strb r2, [r3, #7]
LEDData[2][2] = 0x00;
800110e: 4bbc ldr r3, [pc, #752] ; (8001400 <LEDDesign_Smile+0x330>)
8001110: 2200 movs r2, #0
8001112: 721a strb r2, [r3, #8]
LEDData[3][0] = 0x00;
8001114: 4bba ldr r3, [pc, #744] ; (8001400 <LEDDesign_Smile+0x330>)
8001116: 2200 movs r2, #0
8001118: 725a strb r2, [r3, #9]
LEDData[3][1] = 0x00;
800111a: 4bb9 ldr r3, [pc, #740] ; (8001400 <LEDDesign_Smile+0x330>)
800111c: 2200 movs r2, #0
800111e: 729a strb r2, [r3, #10]
LEDData[3][2] = 0x00;
8001120: 4bb7 ldr r3, [pc, #732] ; (8001400 <LEDDesign_Smile+0x330>)
8001122: 2200 movs r2, #0
8001124: 72da strb r2, [r3, #11]
LEDData[4][0] = 0x00;
8001126: 4bb6 ldr r3, [pc, #728] ; (8001400 <LEDDesign_Smile+0x330>)
8001128: 2200 movs r2, #0
800112a: 731a strb r2, [r3, #12]
LEDData[4][1] = 0x00;
800112c: 4bb4 ldr r3, [pc, #720] ; (8001400 <LEDDesign_Smile+0x330>)
800112e: 2200 movs r2, #0
8001130: 735a strb r2, [r3, #13]
LEDData[4][2] = 0x7F;
8001132: 4bb3 ldr r3, [pc, #716] ; (8001400 <LEDDesign_Smile+0x330>)
8001134: 227f movs r2, #127 ; 0x7f
8001136: 739a strb r2, [r3, #14]
LEDData[5][0] = 0x00;
8001138: 4bb1 ldr r3, [pc, #708] ; (8001400 <LEDDesign_Smile+0x330>)
800113a: 2200 movs r2, #0
800113c: 73da strb r2, [r3, #15]
LEDData[5][1] = 0x00;
800113e: 4bb0 ldr r3, [pc, #704] ; (8001400 <LEDDesign_Smile+0x330>)
8001140: 2200 movs r2, #0
8001142: 741a strb r2, [r3, #16]
LEDData[5][2] = 0x00;
8001144: 4bae ldr r3, [pc, #696] ; (8001400 <LEDDesign_Smile+0x330>)
8001146: 2200 movs r2, #0
8001148: 745a strb r2, [r3, #17]
LEDData[6][0] = 0x00;
800114a: 4bad ldr r3, [pc, #692] ; (8001400 <LEDDesign_Smile+0x330>)
800114c: 2200 movs r2, #0
800114e: 749a strb r2, [r3, #18]
LEDData[6][1] = 0x00;
8001150: 4bab ldr r3, [pc, #684] ; (8001400 <LEDDesign_Smile+0x330>)
8001152: 2200 movs r2, #0
8001154: 74da strb r2, [r3, #19]
LEDData[6][2] = 0x00;
8001156: 4baa ldr r3, [pc, #680] ; (8001400 <LEDDesign_Smile+0x330>)
8001158: 2200 movs r2, #0
800115a: 751a strb r2, [r3, #20]
LEDData[7][0] = 0x00;
800115c: 4ba8 ldr r3, [pc, #672] ; (8001400 <LEDDesign_Smile+0x330>)
800115e: 2200 movs r2, #0
8001160: 755a strb r2, [r3, #21]
LEDData[7][1] = 0x00;
8001162: 4ba7 ldr r3, [pc, #668] ; (8001400 <LEDDesign_Smile+0x330>)
8001164: 2200 movs r2, #0
8001166: 759a strb r2, [r3, #22]
LEDData[7][2] = 0x00;
8001168: 4ba5 ldr r3, [pc, #660] ; (8001400 <LEDDesign_Smile+0x330>)
800116a: 2200 movs r2, #0
800116c: 75da strb r2, [r3, #23]
LEDData[8][0] = 0x00;
800116e: 4ba4 ldr r3, [pc, #656] ; (8001400 <LEDDesign_Smile+0x330>)
8001170: 2200 movs r2, #0
8001172: 761a strb r2, [r3, #24]
LEDData[8][1] = 0x00;
8001174: 4ba2 ldr r3, [pc, #648] ; (8001400 <LEDDesign_Smile+0x330>)
8001176: 2200 movs r2, #0
8001178: 765a strb r2, [r3, #25]
LEDData[8][2] = 0x00;
800117a: 4ba1 ldr r3, [pc, #644] ; (8001400 <LEDDesign_Smile+0x330>)
800117c: 2200 movs r2, #0
800117e: 769a strb r2, [r3, #26]
LEDData[9][0] = 0x00;
8001180: 4b9f ldr r3, [pc, #636] ; (8001400 <LEDDesign_Smile+0x330>)
8001182: 2200 movs r2, #0
8001184: 76da strb r2, [r3, #27]
LEDData[9][1] = 0x00;
8001186: 4b9e ldr r3, [pc, #632] ; (8001400 <LEDDesign_Smile+0x330>)
8001188: 2200 movs r2, #0
800118a: 771a strb r2, [r3, #28]
LEDData[9][2] = 0x00;
800118c: 4b9c ldr r3, [pc, #624] ; (8001400 <LEDDesign_Smile+0x330>)
800118e: 2200 movs r2, #0
8001190: 775a strb r2, [r3, #29]
LEDData[10][0] = 0x00;
8001192: 4b9b ldr r3, [pc, #620] ; (8001400 <LEDDesign_Smile+0x330>)
8001194: 2200 movs r2, #0
8001196: 779a strb r2, [r3, #30]
LEDData[10][1] = 0x00;
8001198: 4b99 ldr r3, [pc, #612] ; (8001400 <LEDDesign_Smile+0x330>)
800119a: 2200 movs r2, #0
800119c: 77da strb r2, [r3, #31]
LEDData[10][2] = 0x7F;
800119e: 4b98 ldr r3, [pc, #608] ; (8001400 <LEDDesign_Smile+0x330>)
80011a0: 227f movs r2, #127 ; 0x7f
80011a2: f883 2020 strb.w r2, [r3, #32]
LEDData[11][0] = 0x00;
80011a6: 4b96 ldr r3, [pc, #600] ; (8001400 <LEDDesign_Smile+0x330>)
80011a8: 2200 movs r2, #0
80011aa: f883 2021 strb.w r2, [r3, #33] ; 0x21
LEDData[11][1] = 0x00;
80011ae: 4b94 ldr r3, [pc, #592] ; (8001400 <LEDDesign_Smile+0x330>)
80011b0: 2200 movs r2, #0
80011b2: f883 2022 strb.w r2, [r3, #34] ; 0x22
LEDData[11][2] = 0x00;
80011b6: 4b92 ldr r3, [pc, #584] ; (8001400 <LEDDesign_Smile+0x330>)
80011b8: 2200 movs r2, #0
80011ba: f883 2023 strb.w r2, [r3, #35] ; 0x23
LEDData[12][0] = 0x00;
80011be: 4b90 ldr r3, [pc, #576] ; (8001400 <LEDDesign_Smile+0x330>)
80011c0: 2200 movs r2, #0
80011c2: f883 2024 strb.w r2, [r3, #36] ; 0x24
LEDData[12][1] = 0x00;
80011c6: 4b8e ldr r3, [pc, #568] ; (8001400 <LEDDesign_Smile+0x330>)
80011c8: 2200 movs r2, #0
80011ca: f883 2025 strb.w r2, [r3, #37] ; 0x25
LEDData[12][2] = 0x00;
80011ce: 4b8c ldr r3, [pc, #560] ; (8001400 <LEDDesign_Smile+0x330>)
80011d0: 2200 movs r2, #0
80011d2: f883 2026 strb.w r2, [r3, #38] ; 0x26
LEDData[13][0] = 0x00;
80011d6: 4b8a ldr r3, [pc, #552] ; (8001400 <LEDDesign_Smile+0x330>)
80011d8: 2200 movs r2, #0
80011da: f883 2027 strb.w r2, [r3, #39] ; 0x27
LEDData[13][1] = 0x00;
80011de: 4b88 ldr r3, [pc, #544] ; (8001400 <LEDDesign_Smile+0x330>)
80011e0: 2200 movs r2, #0
80011e2: f883 2028 strb.w r2, [r3, #40] ; 0x28
LEDData[13][2] = 0x00;
80011e6: 4b86 ldr r3, [pc, #536] ; (8001400 <LEDDesign_Smile+0x330>)
80011e8: 2200 movs r2, #0
80011ea: f883 2029 strb.w r2, [r3, #41] ; 0x29
LEDData[14][0] = 0x00;
80011ee: 4b84 ldr r3, [pc, #528] ; (8001400 <LEDDesign_Smile+0x330>)
80011f0: 2200 movs r2, #0
80011f2: f883 202a strb.w r2, [r3, #42] ; 0x2a
LEDData[14][1] = 0x00;
80011f6: 4b82 ldr r3, [pc, #520] ; (8001400 <LEDDesign_Smile+0x330>)
80011f8: 2200 movs r2, #0
80011fa: f883 202b strb.w r2, [r3, #43] ; 0x2b
LEDData[14][2] = 0x00;
80011fe: 4b80 ldr r3, [pc, #512] ; (8001400 <LEDDesign_Smile+0x330>)
8001200: 2200 movs r2, #0
8001202: f883 202c strb.w r2, [r3, #44] ; 0x2c
LEDData[15][0] = 0x00;
8001206: 4b7e ldr r3, [pc, #504] ; (8001400 <LEDDesign_Smile+0x330>)
8001208: 2200 movs r2, #0
800120a: f883 202d strb.w r2, [r3, #45] ; 0x2d
LEDData[15][1] = 0x00;
800120e: 4b7c ldr r3, [pc, #496] ; (8001400 <LEDDesign_Smile+0x330>)
8001210: 2200 movs r2, #0
8001212: f883 202e strb.w r2, [r3, #46] ; 0x2e
LEDData[15][2] = 0x00;
8001216: 4b7a ldr r3, [pc, #488] ; (8001400 <LEDDesign_Smile+0x330>)
8001218: 2200 movs r2, #0
800121a: f883 202f strb.w r2, [r3, #47] ; 0x2f
LEDData[16][0] = 0x00;
800121e: 4b78 ldr r3, [pc, #480] ; (8001400 <LEDDesign_Smile+0x330>)
8001220: 2200 movs r2, #0
8001222: f883 2030 strb.w r2, [r3, #48] ; 0x30
LEDData[16][1] = 0x00;
8001226: 4b76 ldr r3, [pc, #472] ; (8001400 <LEDDesign_Smile+0x330>)
8001228: 2200 movs r2, #0
800122a: f883 2031 strb.w r2, [r3, #49] ; 0x31
LEDData[16][2] = 0x00;
800122e: 4b74 ldr r3, [pc, #464] ; (8001400 <LEDDesign_Smile+0x330>)
8001230: 2200 movs r2, #0
8001232: f883 2032 strb.w r2, [r3, #50] ; 0x32
LEDData[17][0] = 0x00;
8001236: 4b72 ldr r3, [pc, #456] ; (8001400 <LEDDesign_Smile+0x330>)
8001238: 2200 movs r2, #0
800123a: f883 2033 strb.w r2, [r3, #51] ; 0x33
LEDData[17][1] = 0x00;
800123e: 4b70 ldr r3, [pc, #448] ; (8001400 <LEDDesign_Smile+0x330>)
8001240: 2200 movs r2, #0
8001242: f883 2034 strb.w r2, [r3, #52] ; 0x34
LEDData[17][2] = 0x00;
8001246: 4b6e ldr r3, [pc, #440] ; (8001400 <LEDDesign_Smile+0x330>)
8001248: 2200 movs r2, #0
800124a: f883 2035 strb.w r2, [r3, #53] ; 0x35
LEDData[18][0] = 0x00;
800124e: 4b6c ldr r3, [pc, #432] ; (8001400 <LEDDesign_Smile+0x330>)
8001250: 2200 movs r2, #0
8001252: f883 2036 strb.w r2, [r3, #54] ; 0x36
LEDData[18][1] = 0x00;
8001256: 4b6a ldr r3, [pc, #424] ; (8001400 <LEDDesign_Smile+0x330>)
8001258: 2200 movs r2, #0
800125a: f883 2037 strb.w r2, [r3, #55] ; 0x37
LEDData[18][2] = 0x00;
800125e: 4b68 ldr r3, [pc, #416] ; (8001400 <LEDDesign_Smile+0x330>)
8001260: 2200 movs r2, #0
8001262: f883 2038 strb.w r2, [r3, #56] ; 0x38
LEDData[19][0] = 0x00;
8001266: 4b66 ldr r3, [pc, #408] ; (8001400 <LEDDesign_Smile+0x330>)
8001268: 2200 movs r2, #0
800126a: f883 2039 strb.w r2, [r3, #57] ; 0x39
LEDData[19][1] = 0x00;
800126e: 4b64 ldr r3, [pc, #400] ; (8001400 <LEDDesign_Smile+0x330>)
8001270: 2200 movs r2, #0
8001272: f883 203a strb.w r2, [r3, #58] ; 0x3a
LEDData[19][2] = 0x00;
8001276: 4b62 ldr r3, [pc, #392] ; (8001400 <LEDDesign_Smile+0x330>)
8001278: 2200 movs r2, #0
800127a: f883 203b strb.w r2, [r3, #59] ; 0x3b
LEDData[20][0] = 0x00;
800127e: 4b60 ldr r3, [pc, #384] ; (8001400 <LEDDesign_Smile+0x330>)
8001280: 2200 movs r2, #0
8001282: f883 203c strb.w r2, [r3, #60] ; 0x3c
LEDData[20][1] = 0x00;
8001286: 4b5e ldr r3, [pc, #376] ; (8001400 <LEDDesign_Smile+0x330>)
8001288: 2200 movs r2, #0
800128a: f883 203d strb.w r2, [r3, #61] ; 0x3d
LEDData[20][2] = 0x00;
800128e: 4b5c ldr r3, [pc, #368] ; (8001400 <LEDDesign_Smile+0x330>)
8001290: 2200 movs r2, #0
8001292: f883 203e strb.w r2, [r3, #62] ; 0x3e
LEDData[21][0] = 0x00;
8001296: 4b5a ldr r3, [pc, #360] ; (8001400 <LEDDesign_Smile+0x330>)
8001298: 2200 movs r2, #0
800129a: f883 203f strb.w r2, [r3, #63] ; 0x3f
LEDData[21][1] = 0x00;
800129e: 4b58 ldr r3, [pc, #352] ; (8001400 <LEDDesign_Smile+0x330>)
80012a0: 2200 movs r2, #0
80012a2: f883 2040 strb.w r2, [r3, #64] ; 0x40
LEDData[21][2] = 0x7F;
80012a6: 4b56 ldr r3, [pc, #344] ; (8001400 <LEDDesign_Smile+0x330>)
80012a8: 227f movs r2, #127 ; 0x7f
80012aa: f883 2041 strb.w r2, [r3, #65] ; 0x41
LEDData[22][0] = 0x00;
80012ae: 4b54 ldr r3, [pc, #336] ; (8001400 <LEDDesign_Smile+0x330>)
80012b0: 2200 movs r2, #0
80012b2: f883 2042 strb.w r2, [r3, #66] ; 0x42
LEDData[22][1] = 0x00;
80012b6: 4b52 ldr r3, [pc, #328] ; (8001400 <LEDDesign_Smile+0x330>)
80012b8: 2200 movs r2, #0
80012ba: f883 2043 strb.w r2, [r3, #67] ; 0x43
LEDData[22][2] = 0x00;
80012be: 4b50 ldr r3, [pc, #320] ; (8001400 <LEDDesign_Smile+0x330>)
80012c0: 2200 movs r2, #0
80012c2: f883 2044 strb.w r2, [r3, #68] ; 0x44
LEDData[23][0] = 0x00;
80012c6: 4b4e ldr r3, [pc, #312] ; (8001400 <LEDDesign_Smile+0x330>)
80012c8: 2200 movs r2, #0
80012ca: f883 2045 strb.w r2, [r3, #69] ; 0x45
LEDData[23][1] = 0x00;
80012ce: 4b4c ldr r3, [pc, #304] ; (8001400 <LEDDesign_Smile+0x330>)
80012d0: 2200 movs r2, #0
80012d2: f883 2046 strb.w r2, [r3, #70] ; 0x46
LEDData[23][2] = 0x00;
80012d6: 4b4a ldr r3, [pc, #296] ; (8001400 <LEDDesign_Smile+0x330>)
80012d8: 2200 movs r2, #0
80012da: f883 2047 strb.w r2, [r3, #71] ; 0x47
LEDData[24][0] = 0x00;
80012de: 4b48 ldr r3, [pc, #288] ; (8001400 <LEDDesign_Smile+0x330>)
80012e0: 2200 movs r2, #0
80012e2: f883 2048 strb.w r2, [r3, #72] ; 0x48
LEDData[24][1] = 0x00;
80012e6: 4b46 ldr r3, [pc, #280] ; (8001400 <LEDDesign_Smile+0x330>)
80012e8: 2200 movs r2, #0
80012ea: f883 2049 strb.w r2, [r3, #73] ; 0x49
LEDData[24][2] = 0x00;
80012ee: 4b44 ldr r3, [pc, #272] ; (8001400 <LEDDesign_Smile+0x330>)
80012f0: 2200 movs r2, #0
80012f2: f883 204a strb.w r2, [r3, #74] ; 0x4a
LEDData[25][0] = 0x00;
80012f6: 4b42 ldr r3, [pc, #264] ; (8001400 <LEDDesign_Smile+0x330>)
80012f8: 2200 movs r2, #0
80012fa: f883 204b strb.w r2, [r3, #75] ; 0x4b
LEDData[25][1] = 0x00;
80012fe: 4b40 ldr r3, [pc, #256] ; (8001400 <LEDDesign_Smile+0x330>)
8001300: 2200 movs r2, #0
8001302: f883 204c strb.w r2, [r3, #76] ; 0x4c
LEDData[25][2] = 0x00;
8001306: 4b3e ldr r3, [pc, #248] ; (8001400 <LEDDesign_Smile+0x330>)
8001308: 2200 movs r2, #0
800130a: f883 204d strb.w r2, [r3, #77] ; 0x4d
LEDData[26][0] = 0x00;
800130e: 4b3c ldr r3, [pc, #240] ; (8001400 <LEDDesign_Smile+0x330>)
8001310: 2200 movs r2, #0
8001312: f883 204e strb.w r2, [r3, #78] ; 0x4e
LEDData[26][1] = 0x00;
8001316: 4b3a ldr r3, [pc, #232] ; (8001400 <LEDDesign_Smile+0x330>)
8001318: 2200 movs r2, #0
800131a: f883 204f strb.w r2, [r3, #79] ; 0x4f
LEDData[26][2] = 0x7F;
800131e: 4b38 ldr r3, [pc, #224] ; (8001400 <LEDDesign_Smile+0x330>)
8001320: 227f movs r2, #127 ; 0x7f
8001322: f883 2050 strb.w r2, [r3, #80] ; 0x50
LEDData[27][0] = 0x00;
8001326: 4b36 ldr r3, [pc, #216] ; (8001400 <LEDDesign_Smile+0x330>)
8001328: 2200 movs r2, #0
800132a: f883 2051 strb.w r2, [r3, #81] ; 0x51
LEDData[27][1] = 0x00;
800132e: 4b34 ldr r3, [pc, #208] ; (8001400 <LEDDesign_Smile+0x330>)
8001330: 2200 movs r2, #0
8001332: f883 2052 strb.w r2, [r3, #82] ; 0x52
LEDData[27][2] = 0x00;
8001336: 4b32 ldr r3, [pc, #200] ; (8001400 <LEDDesign_Smile+0x330>)
8001338: 2200 movs r2, #0
800133a: f883 2053 strb.w r2, [r3, #83] ; 0x53
LEDData[28][0] = 0x00;
800133e: 4b30 ldr r3, [pc, #192] ; (8001400 <LEDDesign_Smile+0x330>)
8001340: 2200 movs r2, #0
8001342: f883 2054 strb.w r2, [r3, #84] ; 0x54
LEDData[28][1] = 0x00;
8001346: 4b2e ldr r3, [pc, #184] ; (8001400 <LEDDesign_Smile+0x330>)
8001348: 2200 movs r2, #0
800134a: f883 2055 strb.w r2, [r3, #85] ; 0x55
LEDData[28][2] = 0x00;
800134e: 4b2c ldr r3, [pc, #176] ; (8001400 <LEDDesign_Smile+0x330>)
8001350: 2200 movs r2, #0
8001352: f883 2056 strb.w r2, [r3, #86] ; 0x56
LEDData[29][0] = 0x00;
8001356: 4b2a ldr r3, [pc, #168] ; (8001400 <LEDDesign_Smile+0x330>)
8001358: 2200 movs r2, #0
800135a: f883 2057 strb.w r2, [r3, #87] ; 0x57
LEDData[29][1] = 0x00;
800135e: 4b28 ldr r3, [pc, #160] ; (8001400 <LEDDesign_Smile+0x330>)
8001360: 2200 movs r2, #0
8001362: f883 2058 strb.w r2, [r3, #88] ; 0x58
LEDData[29][2] = 0x00;
8001366: 4b26 ldr r3, [pc, #152] ; (8001400 <LEDDesign_Smile+0x330>)
8001368: 2200 movs r2, #0
800136a: f883 2059 strb.w r2, [r3, #89] ; 0x59
LEDData[30][0] = 0x00;
800136e: 4b24 ldr r3, [pc, #144] ; (8001400 <LEDDesign_Smile+0x330>)
8001370: 2200 movs r2, #0
8001372: f883 205a strb.w r2, [r3, #90] ; 0x5a
LEDData[30][1] = 0x00;
8001376: 4b22 ldr r3, [pc, #136] ; (8001400 <LEDDesign_Smile+0x330>)
8001378: 2200 movs r2, #0
800137a: f883 205b strb.w r2, [r3, #91] ; 0x5b
LEDData[30][2] = 0x00;
800137e: 4b20 ldr r3, [pc, #128] ; (8001400 <LEDDesign_Smile+0x330>)
8001380: 2200 movs r2, #0
8001382: f883 205c strb.w r2, [r3, #92] ; 0x5c
LEDData[31][0] = 0x00;
8001386: 4b1e ldr r3, [pc, #120] ; (8001400 <LEDDesign_Smile+0x330>)
8001388: 2200 movs r2, #0
800138a: f883 205d strb.w r2, [r3, #93] ; 0x5d
LEDData[31][1] = 0x00;
800138e: 4b1c ldr r3, [pc, #112] ; (8001400 <LEDDesign_Smile+0x330>)
8001390: 2200 movs r2, #0
8001392: f883 205e strb.w r2, [r3, #94] ; 0x5e
LEDData[31][2] = 0x00;
8001396: 4b1a ldr r3, [pc, #104] ; (8001400 <LEDDesign_Smile+0x330>)
8001398: 2200 movs r2, #0
800139a: f883 205f strb.w r2, [r3, #95] ; 0x5f
LEDData[32][0] = 0x00;
800139e: 4b18 ldr r3, [pc, #96] ; (8001400 <LEDDesign_Smile+0x330>)
80013a0: 2200 movs r2, #0
80013a2: f883 2060 strb.w r2, [r3, #96] ; 0x60
LEDData[32][1] = 0x00;
80013a6: 4b16 ldr r3, [pc, #88] ; (8001400 <LEDDesign_Smile+0x330>)
80013a8: 2200 movs r2, #0
80013aa: f883 2061 strb.w r2, [r3, #97] ; 0x61
LEDData[32][2] = 0x00;
80013ae: 4b14 ldr r3, [pc, #80] ; (8001400 <LEDDesign_Smile+0x330>)
80013b0: 2200 movs r2, #0
80013b2: f883 2062 strb.w r2, [r3, #98] ; 0x62
LEDData[33][0] = 0x00;
80013b6: 4b12 ldr r3, [pc, #72] ; (8001400 <LEDDesign_Smile+0x330>)
80013b8: 2200 movs r2, #0
80013ba: f883 2063 strb.w r2, [r3, #99] ; 0x63
LEDData[33][1] = 0x00;
80013be: 4b10 ldr r3, [pc, #64] ; (8001400 <LEDDesign_Smile+0x330>)
80013c0: 2200 movs r2, #0
80013c2: f883 2064 strb.w r2, [r3, #100] ; 0x64
LEDData[33][2] = 0x00;
80013c6: 4b0e ldr r3, [pc, #56] ; (8001400 <LEDDesign_Smile+0x330>)
80013c8: 2200 movs r2, #0
80013ca: f883 2065 strb.w r2, [r3, #101] ; 0x65
LEDData[34][0] = 0x00;
80013ce: 4b0c ldr r3, [pc, #48] ; (8001400 <LEDDesign_Smile+0x330>)
80013d0: 2200 movs r2, #0
80013d2: f883 2066 strb.w r2, [r3, #102] ; 0x66
LEDData[34][1] = 0x00;
80013d6: 4b0a ldr r3, [pc, #40] ; (8001400 <LEDDesign_Smile+0x330>)
80013d8: 2200 movs r2, #0
80013da: f883 2067 strb.w r2, [r3, #103] ; 0x67
LEDData[34][2] = 0x00;
80013de: 4b08 ldr r3, [pc, #32] ; (8001400 <LEDDesign_Smile+0x330>)
80013e0: 2200 movs r2, #0
80013e2: f883 2068 strb.w r2, [r3, #104] ; 0x68
LEDData[35][0] = 0x00;
80013e6: 4b06 ldr r3, [pc, #24] ; (8001400 <LEDDesign_Smile+0x330>)
80013e8: 2200 movs r2, #0
80013ea: f883 2069 strb.w r2, [r3, #105] ; 0x69
LEDData[35][1] = 0x00;
80013ee: 4b04 ldr r3, [pc, #16] ; (8001400 <LEDDesign_Smile+0x330>)
80013f0: 2200 movs r2, #0
80013f2: f883 206a strb.w r2, [r3, #106] ; 0x6a
LEDData[35][2] = 0x00;
80013f6: 4b02 ldr r3, [pc, #8] ; (8001400 <LEDDesign_Smile+0x330>)
80013f8: 2200 movs r2, #0
80013fa: f883 206b strb.w r2, [r3, #107] ; 0x6b
80013fe: e001 b.n 8001404 <LEDDesign_Smile+0x334>
8001400: 20000094 .word 0x20000094
LEDData[36][0] = 0x00;
8001404: 4ba9 ldr r3, [pc, #676] ; (80016ac <LEDDesign_Smile+0x5dc>)
8001406: 2200 movs r2, #0
8001408: f883 206c strb.w r2, [r3, #108] ; 0x6c
LEDData[36][1] = 0x00;
800140c: 4ba7 ldr r3, [pc, #668] ; (80016ac <LEDDesign_Smile+0x5dc>)
800140e: 2200 movs r2, #0
8001410: f883 206d strb.w r2, [r3, #109] ; 0x6d
LEDData[36][2] = 0x00;
8001414: 4ba5 ldr r3, [pc, #660] ; (80016ac <LEDDesign_Smile+0x5dc>)
8001416: 2200 movs r2, #0
8001418: f883 206e strb.w r2, [r3, #110] ; 0x6e
LEDData[37][0] = 0x00;
800141c: 4ba3 ldr r3, [pc, #652] ; (80016ac <LEDDesign_Smile+0x5dc>)
800141e: 2200 movs r2, #0
8001420: f883 206f strb.w r2, [r3, #111] ; 0x6f
LEDData[37][1] = 0x00;
8001424: 4ba1 ldr r3, [pc, #644] ; (80016ac <LEDDesign_Smile+0x5dc>)
8001426: 2200 movs r2, #0
8001428: f883 2070 strb.w r2, [r3, #112] ; 0x70
LEDData[37][2] = 0x7F;
800142c: 4b9f ldr r3, [pc, #636] ; (80016ac <LEDDesign_Smile+0x5dc>)
800142e: 227f movs r2, #127 ; 0x7f
8001430: f883 2071 strb.w r2, [r3, #113] ; 0x71
LEDData[38][0] = 0x00;
8001434: 4b9d ldr r3, [pc, #628] ; (80016ac <LEDDesign_Smile+0x5dc>)
8001436: 2200 movs r2, #0
8001438: f883 2072 strb.w r2, [r3, #114] ; 0x72
LEDData[38][1] = 0x00;
800143c: 4b9b ldr r3, [pc, #620] ; (80016ac <LEDDesign_Smile+0x5dc>)
800143e: 2200 movs r2, #0
8001440: f883 2073 strb.w r2, [r3, #115] ; 0x73
LEDData[38][2] = 0x00;
8001444: 4b99 ldr r3, [pc, #612] ; (80016ac <LEDDesign_Smile+0x5dc>)
8001446: 2200 movs r2, #0
8001448: f883 2074 strb.w r2, [r3, #116] ; 0x74
LEDData[39][0] = 0x00;
800144c: 4b97 ldr r3, [pc, #604] ; (80016ac <LEDDesign_Smile+0x5dc>)
800144e: 2200 movs r2, #0
8001450: f883 2075 strb.w r2, [r3, #117] ; 0x75
LEDData[39][1] = 0x00;
8001454: 4b95 ldr r3, [pc, #596] ; (80016ac <LEDDesign_Smile+0x5dc>)
8001456: 2200 movs r2, #0
8001458: f883 2076 strb.w r2, [r3, #118] ; 0x76
LEDData[39][2] = 0x00;
800145c: 4b93 ldr r3, [pc, #588] ; (80016ac <LEDDesign_Smile+0x5dc>)
800145e: 2200 movs r2, #0
8001460: f883 2077 strb.w r2, [r3, #119] ; 0x77
LEDData[40][0] = 0x00;
8001464: 4b91 ldr r3, [pc, #580] ; (80016ac <LEDDesign_Smile+0x5dc>)
8001466: 2200 movs r2, #0
8001468: f883 2078 strb.w r2, [r3, #120] ; 0x78
LEDData[40][1] = 0x00;
800146c: 4b8f ldr r3, [pc, #572] ; (80016ac <LEDDesign_Smile+0x5dc>)
800146e: 2200 movs r2, #0
8001470: f883 2079 strb.w r2, [r3, #121] ; 0x79
LEDData[40][2] = 0x00;
8001474: 4b8d ldr r3, [pc, #564] ; (80016ac <LEDDesign_Smile+0x5dc>)
8001476: 2200 movs r2, #0
8001478: f883 207a strb.w r2, [r3, #122] ; 0x7a
LEDData[41][0] = 0x00;
800147c: 4b8b ldr r3, [pc, #556] ; (80016ac <LEDDesign_Smile+0x5dc>)
800147e: 2200 movs r2, #0
8001480: f883 207b strb.w r2, [r3, #123] ; 0x7b
LEDData[41][1] = 0x00;
8001484: 4b89 ldr r3, [pc, #548] ; (80016ac <LEDDesign_Smile+0x5dc>)
8001486: 2200 movs r2, #0
8001488: f883 207c strb.w r2, [r3, #124] ; 0x7c
LEDData[41][2] = 0x00;
800148c: 4b87 ldr r3, [pc, #540] ; (80016ac <LEDDesign_Smile+0x5dc>)
800148e: 2200 movs r2, #0
8001490: f883 207d strb.w r2, [r3, #125] ; 0x7d
LEDData[42][0] = 0x00;
8001494: 4b85 ldr r3, [pc, #532] ; (80016ac <LEDDesign_Smile+0x5dc>)
8001496: 2200 movs r2, #0
8001498: f883 207e strb.w r2, [r3, #126] ; 0x7e
LEDData[42][1] = 0x00;
800149c: 4b83 ldr r3, [pc, #524] ; (80016ac <LEDDesign_Smile+0x5dc>)
800149e: 2200 movs r2, #0
80014a0: f883 207f strb.w r2, [r3, #127] ; 0x7f
LEDData[42][2] = 0x7F;
80014a4: 4b81 ldr r3, [pc, #516] ; (80016ac <LEDDesign_Smile+0x5dc>)
80014a6: 227f movs r2, #127 ; 0x7f
80014a8: f883 2080 strb.w r2, [r3, #128] ; 0x80
LEDData[43][0] = 0x00;
80014ac: 4b7f ldr r3, [pc, #508] ; (80016ac <LEDDesign_Smile+0x5dc>)
80014ae: 2200 movs r2, #0
80014b0: f883 2081 strb.w r2, [r3, #129] ; 0x81
LEDData[43][1] = 0x00;
80014b4: 4b7d ldr r3, [pc, #500] ; (80016ac <LEDDesign_Smile+0x5dc>)
80014b6: 2200 movs r2, #0
80014b8: f883 2082 strb.w r2, [r3, #130] ; 0x82
LEDData[43][2] = 0x00;
80014bc: 4b7b ldr r3, [pc, #492] ; (80016ac <LEDDesign_Smile+0x5dc>)
80014be: 2200 movs r2, #0
80014c0: f883 2083 strb.w r2, [r3, #131] ; 0x83
LEDData[44][0] = 0x00;
80014c4: 4b79 ldr r3, [pc, #484] ; (80016ac <LEDDesign_Smile+0x5dc>)
80014c6: 2200 movs r2, #0
80014c8: f883 2084 strb.w r2, [r3, #132] ; 0x84
LEDData[44][1] = 0x00;
80014cc: 4b77 ldr r3, [pc, #476] ; (80016ac <LEDDesign_Smile+0x5dc>)
80014ce: 2200 movs r2, #0
80014d0: f883 2085 strb.w r2, [r3, #133] ; 0x85
LEDData[44][2] = 0x00;
80014d4: 4b75 ldr r3, [pc, #468] ; (80016ac <LEDDesign_Smile+0x5dc>)
80014d6: 2200 movs r2, #0
80014d8: f883 2086 strb.w r2, [r3, #134] ; 0x86
LEDData[45][0] = 0x00;
80014dc: 4b73 ldr r3, [pc, #460] ; (80016ac <LEDDesign_Smile+0x5dc>)
80014de: 2200 movs r2, #0
80014e0: f883 2087 strb.w r2, [r3, #135] ; 0x87
LEDData[45][1] = 0x00;
80014e4: 4b71 ldr r3, [pc, #452] ; (80016ac <LEDDesign_Smile+0x5dc>)
80014e6: 2200 movs r2, #0
80014e8: f883 2088 strb.w r2, [r3, #136] ; 0x88
LEDData[45][2] = 0x00;
80014ec: 4b6f ldr r3, [pc, #444] ; (80016ac <LEDDesign_Smile+0x5dc>)
80014ee: 2200 movs r2, #0
80014f0: f883 2089 strb.w r2, [r3, #137] ; 0x89
LEDData[46][0] = 0x00;
80014f4: 4b6d ldr r3, [pc, #436] ; (80016ac <LEDDesign_Smile+0x5dc>)
80014f6: 2200 movs r2, #0
80014f8: f883 208a strb.w r2, [r3, #138] ; 0x8a
LEDData[46][1] = 0x00;
80014fc: 4b6b ldr r3, [pc, #428] ; (80016ac <LEDDesign_Smile+0x5dc>)
80014fe: 2200 movs r2, #0
8001500: f883 208b strb.w r2, [r3, #139] ; 0x8b
LEDData[46][2] = 0x00;
8001504: 4b69 ldr r3, [pc, #420] ; (80016ac <LEDDesign_Smile+0x5dc>)
8001506: 2200 movs r2, #0
8001508: f883 208c strb.w r2, [r3, #140] ; 0x8c
LEDData[47][0] = 0x00;
800150c: 4b67 ldr r3, [pc, #412] ; (80016ac <LEDDesign_Smile+0x5dc>)
800150e: 2200 movs r2, #0
8001510: f883 208d strb.w r2, [r3, #141] ; 0x8d
LEDData[47][1] = 0x00;
8001514: 4b65 ldr r3, [pc, #404] ; (80016ac <LEDDesign_Smile+0x5dc>)
8001516: 2200 movs r2, #0
8001518: f883 208e strb.w r2, [r3, #142] ; 0x8e
LEDData[47][2] = 0x00;
800151c: 4b63 ldr r3, [pc, #396] ; (80016ac <LEDDesign_Smile+0x5dc>)
800151e: 2200 movs r2, #0
8001520: f883 208f strb.w r2, [r3, #143] ; 0x8f
LEDData[48][0] = 0x00;
8001524: 4b61 ldr r3, [pc, #388] ; (80016ac <LEDDesign_Smile+0x5dc>)
8001526: 2200 movs r2, #0
8001528: f883 2090 strb.w r2, [r3, #144] ; 0x90
LEDData[48][1] = 0x00;
800152c: 4b5f ldr r3, [pc, #380] ; (80016ac <LEDDesign_Smile+0x5dc>)
800152e: 2200 movs r2, #0
8001530: f883 2091 strb.w r2, [r3, #145] ; 0x91
LEDData[48][2] = 0x00;
8001534: 4b5d ldr r3, [pc, #372] ; (80016ac <LEDDesign_Smile+0x5dc>)
8001536: 2200 movs r2, #0
8001538: f883 2092 strb.w r2, [r3, #146] ; 0x92
LEDData[49][0] = 0x00;
800153c: 4b5b ldr r3, [pc, #364] ; (80016ac <LEDDesign_Smile+0x5dc>)
800153e: 2200 movs r2, #0
8001540: f883 2093 strb.w r2, [r3, #147] ; 0x93
LEDData[49][1] = 0x00;
8001544: 4b59 ldr r3, [pc, #356] ; (80016ac <LEDDesign_Smile+0x5dc>)
8001546: 2200 movs r2, #0
8001548: f883 2094 strb.w r2, [r3, #148] ; 0x94
LEDData[49][2] = 0x00;
800154c: 4b57 ldr r3, [pc, #348] ; (80016ac <LEDDesign_Smile+0x5dc>)
800154e: 2200 movs r2, #0
8001550: f883 2095 strb.w r2, [r3, #149] ; 0x95
LEDData[50][0] = 0x00;
8001554: 4b55 ldr r3, [pc, #340] ; (80016ac <LEDDesign_Smile+0x5dc>)
8001556: 2200 movs r2, #0
8001558: f883 2096 strb.w r2, [r3, #150] ; 0x96
LEDData[50][1] = 0x00;
800155c: 4b53 ldr r3, [pc, #332] ; (80016ac <LEDDesign_Smile+0x5dc>)
800155e: 2200 movs r2, #0
8001560: f883 2097 strb.w r2, [r3, #151] ; 0x97
LEDData[50][2] = 0x00;
8001564: 4b51 ldr r3, [pc, #324] ; (80016ac <LEDDesign_Smile+0x5dc>)
8001566: 2200 movs r2, #0
8001568: f883 2098 strb.w r2, [r3, #152] ; 0x98
LEDData[51][0] = 0x00;
800156c: 4b4f ldr r3, [pc, #316] ; (80016ac <LEDDesign_Smile+0x5dc>)
800156e: 2200 movs r2, #0
8001570: f883 2099 strb.w r2, [r3, #153] ; 0x99
LEDData[51][1] = 0x00;
8001574: 4b4d ldr r3, [pc, #308] ; (80016ac <LEDDesign_Smile+0x5dc>)
8001576: 2200 movs r2, #0
8001578: f883 209a strb.w r2, [r3, #154] ; 0x9a
LEDData[51][2] = 0x00;
800157c: 4b4b ldr r3, [pc, #300] ; (80016ac <LEDDesign_Smile+0x5dc>)
800157e: 2200 movs r2, #0
8001580: f883 209b strb.w r2, [r3, #155] ; 0x9b
LEDData[52][0] = 0x00;
8001584: 4b49 ldr r3, [pc, #292] ; (80016ac <LEDDesign_Smile+0x5dc>)
8001586: 2200 movs r2, #0
8001588: f883 209c strb.w r2, [r3, #156] ; 0x9c
LEDData[52][1] = 0x00;
800158c: 4b47 ldr r3, [pc, #284] ; (80016ac <LEDDesign_Smile+0x5dc>)
800158e: 2200 movs r2, #0
8001590: f883 209d strb.w r2, [r3, #157] ; 0x9d
LEDData[52][2] = 0x00;
8001594: 4b45 ldr r3, [pc, #276] ; (80016ac <LEDDesign_Smile+0x5dc>)
8001596: 2200 movs r2, #0
8001598: f883 209e strb.w r2, [r3, #158] ; 0x9e
LEDData[53][0] = 0x00;
800159c: 4b43 ldr r3, [pc, #268] ; (80016ac <LEDDesign_Smile+0x5dc>)
800159e: 2200 movs r2, #0
80015a0: f883 209f strb.w r2, [r3, #159] ; 0x9f
LEDData[53][1] = 0x00;
80015a4: 4b41 ldr r3, [pc, #260] ; (80016ac <LEDDesign_Smile+0x5dc>)
80015a6: 2200 movs r2, #0
80015a8: f883 20a0 strb.w r2, [r3, #160] ; 0xa0
LEDData[53][2] = 0x7F;
80015ac: 4b3f ldr r3, [pc, #252] ; (80016ac <LEDDesign_Smile+0x5dc>)
80015ae: 227f movs r2, #127 ; 0x7f
80015b0: f883 20a1 strb.w r2, [r3, #161] ; 0xa1
LEDData[54][0] = 0x00;
80015b4: 4b3d ldr r3, [pc, #244] ; (80016ac <LEDDesign_Smile+0x5dc>)
80015b6: 2200 movs r2, #0
80015b8: f883 20a2 strb.w r2, [r3, #162] ; 0xa2
LEDData[54][1] = 0x00;
80015bc: 4b3b ldr r3, [pc, #236] ; (80016ac <LEDDesign_Smile+0x5dc>)
80015be: 2200 movs r2, #0
80015c0: f883 20a3 strb.w r2, [r3, #163] ; 0xa3
LEDData[54][2] = 0x00;
80015c4: 4b39 ldr r3, [pc, #228] ; (80016ac <LEDDesign_Smile+0x5dc>)
80015c6: 2200 movs r2, #0
80015c8: f883 20a4 strb.w r2, [r3, #164] ; 0xa4
LEDData[55][0] = 0x00;
80015cc: 4b37 ldr r3, [pc, #220] ; (80016ac <LEDDesign_Smile+0x5dc>)
80015ce: 2200 movs r2, #0
80015d0: f883 20a5 strb.w r2, [r3, #165] ; 0xa5
LEDData[55][1] = 0x00;
80015d4: 4b35 ldr r3, [pc, #212] ; (80016ac <LEDDesign_Smile+0x5dc>)
80015d6: 2200 movs r2, #0
80015d8: f883 20a6 strb.w r2, [r3, #166] ; 0xa6
LEDData[55][2] = 0x00;
80015dc: 4b33 ldr r3, [pc, #204] ; (80016ac <LEDDesign_Smile+0x5dc>)
80015de: 2200 movs r2, #0
80015e0: f883 20a7 strb.w r2, [r3, #167] ; 0xa7
LEDData[56][0] = 0x00;
80015e4: 4b31 ldr r3, [pc, #196] ; (80016ac <LEDDesign_Smile+0x5dc>)
80015e6: 2200 movs r2, #0
80015e8: f883 20a8 strb.w r2, [r3, #168] ; 0xa8
LEDData[56][1] = 0x00;
80015ec: 4b2f ldr r3, [pc, #188] ; (80016ac <LEDDesign_Smile+0x5dc>)
80015ee: 2200 movs r2, #0
80015f0: f883 20a9 strb.w r2, [r3, #169] ; 0xa9
LEDData[56][2] = 0x00;
80015f4: 4b2d ldr r3, [pc, #180] ; (80016ac <LEDDesign_Smile+0x5dc>)
80015f6: 2200 movs r2, #0
80015f8: f883 20aa strb.w r2, [r3, #170] ; 0xaa
LEDData[57][0] = 0x00;
80015fc: 4b2b ldr r3, [pc, #172] ; (80016ac <LEDDesign_Smile+0x5dc>)
80015fe: 2200 movs r2, #0
8001600: f883 20ab strb.w r2, [r3, #171] ; 0xab
LEDData[57][1] = 0x00;
8001604: 4b29 ldr r3, [pc, #164] ; (80016ac <LEDDesign_Smile+0x5dc>)
8001606: 2200 movs r2, #0
8001608: f883 20ac strb.w r2, [r3, #172] ; 0xac
LEDData[57][2] = 0x00;
800160c: 4b27 ldr r3, [pc, #156] ; (80016ac <LEDDesign_Smile+0x5dc>)
800160e: 2200 movs r2, #0
8001610: f883 20ad strb.w r2, [r3, #173] ; 0xad
LEDData[58][0] = 0x00;
8001614: 4b25 ldr r3, [pc, #148] ; (80016ac <LEDDesign_Smile+0x5dc>)
8001616: 2200 movs r2, #0
8001618: f883 20ae strb.w r2, [r3, #174] ; 0xae
LEDData[58][1] = 0x00;
800161c: 4b23 ldr r3, [pc, #140] ; (80016ac <LEDDesign_Smile+0x5dc>)
800161e: 2200 movs r2, #0
8001620: f883 20af strb.w r2, [r3, #175] ; 0xaf
LEDData[58][2] = 0x00;
8001624: 4b21 ldr r3, [pc, #132] ; (80016ac <LEDDesign_Smile+0x5dc>)
8001626: 2200 movs r2, #0
8001628: f883 20b0 strb.w r2, [r3, #176] ; 0xb0
LEDData[59][0] = 0x00;
800162c: 4b1f ldr r3, [pc, #124] ; (80016ac <LEDDesign_Smile+0x5dc>)
800162e: 2200 movs r2, #0
8001630: f883 20b1 strb.w r2, [r3, #177] ; 0xb1
LEDData[59][1] = 0x00;
8001634: 4b1d ldr r3, [pc, #116] ; (80016ac <LEDDesign_Smile+0x5dc>)
8001636: 2200 movs r2, #0
8001638: f883 20b2 strb.w r2, [r3, #178] ; 0xb2
LEDData[59][2] = 0x7F;
800163c: 4b1b ldr r3, [pc, #108] ; (80016ac <LEDDesign_Smile+0x5dc>)
800163e: 227f movs r2, #127 ; 0x7f
8001640: f883 20b3 strb.w r2, [r3, #179] ; 0xb3
LEDData[60][0] = 0x00;
8001644: 4b19 ldr r3, [pc, #100] ; (80016ac <LEDDesign_Smile+0x5dc>)
8001646: 2200 movs r2, #0
8001648: f883 20b4 strb.w r2, [r3, #180] ; 0xb4
LEDData[60][1] = 0x00;
800164c: 4b17 ldr r3, [pc, #92] ; (80016ac <LEDDesign_Smile+0x5dc>)
800164e: 2200 movs r2, #0
8001650: f883 20b5 strb.w r2, [r3, #181] ; 0xb5
LEDData[60][2] = 0x00;
8001654: 4b15 ldr r3, [pc, #84] ; (80016ac <LEDDesign_Smile+0x5dc>)
8001656: 2200 movs r2, #0
8001658: f883 20b6 strb.w r2, [r3, #182] ; 0xb6
LEDData[61][0] = 0x00;
800165c: 4b13 ldr r3, [pc, #76] ; (80016ac <LEDDesign_Smile+0x5dc>)
800165e: 2200 movs r2, #0
8001660: f883 20b7 strb.w r2, [r3, #183] ; 0xb7
LEDData[61][1] = 0x00;
8001664: 4b11 ldr r3, [pc, #68] ; (80016ac <LEDDesign_Smile+0x5dc>)
8001666: 2200 movs r2, #0
8001668: f883 20b8 strb.w r2, [r3, #184] ; 0xb8
LEDData[61][2] = 0x00;
800166c: 4b0f ldr r3, [pc, #60] ; (80016ac <LEDDesign_Smile+0x5dc>)
800166e: 2200 movs r2, #0
8001670: f883 20b9 strb.w r2, [r3, #185] ; 0xb9
LEDData[62][0] = 0x00;
8001674: 4b0d ldr r3, [pc, #52] ; (80016ac <LEDDesign_Smile+0x5dc>)
8001676: 2200 movs r2, #0
8001678: f883 20ba strb.w r2, [r3, #186] ; 0xba
LEDData[62][1] = 0x00;
800167c: 4b0b ldr r3, [pc, #44] ; (80016ac <LEDDesign_Smile+0x5dc>)
800167e: 2200 movs r2, #0
8001680: f883 20bb strb.w r2, [r3, #187] ; 0xbb
LEDData[62][2] = 0x00;
8001684: 4b09 ldr r3, [pc, #36] ; (80016ac <LEDDesign_Smile+0x5dc>)
8001686: 2200 movs r2, #0
8001688: f883 20bc strb.w r2, [r3, #188] ; 0xbc
LEDData[63][0] = 0x00;
800168c: 4b07 ldr r3, [pc, #28] ; (80016ac <LEDDesign_Smile+0x5dc>)
800168e: 2200 movs r2, #0
8001690: f883 20bd strb.w r2, [r3, #189] ; 0xbd
LEDData[63][1] = 0x00;
8001694: 4b05 ldr r3, [pc, #20] ; (80016ac <LEDDesign_Smile+0x5dc>)
8001696: 2200 movs r2, #0
8001698: f883 20be strb.w r2, [r3, #190] ; 0xbe
LEDData[63][2] = 0x00;
800169c: 4b03 ldr r3, [pc, #12] ; (80016ac <LEDDesign_Smile+0x5dc>)
800169e: 2200 movs r2, #0
80016a0: f883 20bf strb.w r2, [r3, #191] ; 0xbf
}
80016a4: bf00 nop
80016a6: 3708 adds r7, #8
80016a8: 46bd mov sp, r7
80016aa: bd80 pop {r7, pc}
80016ac: 20000094 .word 0x20000094
080016b0 <LEDDesign_SuperCrazy>:
void LEDDesign_SuperCrazy(void){
80016b0: b580 push {r7, lr}
80016b2: b084 sub sp, #16
80016b4: af00 add r7, sp, #0
HAL_Delay(50);
80016b6: 2032 movs r0, #50 ; 0x32
80016b8: f000 fc66 bl 8001f88 <HAL_Delay>
uint8_t randomByte = (uint8_t) (0xFF * (((float) rand()) / RAND_MAX));
80016bc: f002 fe2e bl 800431c <rand>
80016c0: ee07 0a90 vmov s15, r0
80016c4: eeb8 7ae7 vcvt.f32.s32 s14, s15
80016c8: eddf 6a37 vldr s13, [pc, #220] ; 80017a8 <LEDDesign_SuperCrazy+0xf8>
80016cc: eec7 7a26 vdiv.f32 s15, s14, s13
80016d0: ed9f 7a36 vldr s14, [pc, #216] ; 80017ac <LEDDesign_SuperCrazy+0xfc>
80016d4: ee67 7a87 vmul.f32 s15, s15, s14
80016d8: eefc 7ae7 vcvt.u32.f32 s15, s15
80016dc: edc7 7a01 vstr s15, [r7, #4]
80016e0: 793b ldrb r3, [r7, #4]
80016e2: 733b strb r3, [r7, #12]
for(uint8_t i = 0; i < 64; ++i){
80016e4: 2300 movs r3, #0
80016e6: 73fb strb r3, [r7, #15]
80016e8: e00a b.n 8001700 <LEDDesign_SuperCrazy+0x50>
LEDData[i][0] = randomByte;
80016ea: 7bfa ldrb r2, [r7, #15]
80016ec: 4930 ldr r1, [pc, #192] ; (80017b0 <LEDDesign_SuperCrazy+0x100>)
80016ee: 4613 mov r3, r2
80016f0: 005b lsls r3, r3, #1
80016f2: 4413 add r3, r2
80016f4: 440b add r3, r1
80016f6: 7b3a ldrb r2, [r7, #12]
80016f8: 701a strb r2, [r3, #0]
for(uint8_t i = 0; i < 64; ++i){
80016fa: 7bfb ldrb r3, [r7, #15]
80016fc: 3301 adds r3, #1
80016fe: 73fb strb r3, [r7, #15]
8001700: 7bfb ldrb r3, [r7, #15]
8001702: 2b3f cmp r3, #63 ; 0x3f
8001704: d9f1 bls.n 80016ea <LEDDesign_SuperCrazy+0x3a>
}
randomByte = (uint8_t) (0xFF * (((float) rand()) / RAND_MAX));
8001706: f002 fe09 bl 800431c <rand>
800170a: ee07 0a90 vmov s15, r0
800170e: eeb8 7ae7 vcvt.f32.s32 s14, s15
8001712: eddf 6a25 vldr s13, [pc, #148] ; 80017a8 <LEDDesign_SuperCrazy+0xf8>
8001716: eec7 7a26 vdiv.f32 s15, s14, s13
800171a: ed9f 7a24 vldr s14, [pc, #144] ; 80017ac <LEDDesign_SuperCrazy+0xfc>
800171e: ee67 7a87 vmul.f32 s15, s15, s14
8001722: eefc 7ae7 vcvt.u32.f32 s15, s15
8001726: edc7 7a01 vstr s15, [r7, #4]
800172a: 793b ldrb r3, [r7, #4]
800172c: 733b strb r3, [r7, #12]
for(uint8_t i = 0; i < 64; ++i){
800172e: 2300 movs r3, #0
8001730: 73bb strb r3, [r7, #14]
8001732: e00b b.n 800174c <LEDDesign_SuperCrazy+0x9c>
LEDData[i][1] = randomByte;
8001734: 7bba ldrb r2, [r7, #14]
8001736: 491e ldr r1, [pc, #120] ; (80017b0 <LEDDesign_SuperCrazy+0x100>)
8001738: 4613 mov r3, r2
800173a: 005b lsls r3, r3, #1
800173c: 4413 add r3, r2
800173e: 440b add r3, r1
8001740: 3301 adds r3, #1
8001742: 7b3a ldrb r2, [r7, #12]
8001744: 701a strb r2, [r3, #0]
for(uint8_t i = 0; i < 64; ++i){
8001746: 7bbb ldrb r3, [r7, #14]
8001748: 3301 adds r3, #1
800174a: 73bb strb r3, [r7, #14]
800174c: 7bbb ldrb r3, [r7, #14]
800174e: 2b3f cmp r3, #63 ; 0x3f
8001750: d9f0 bls.n 8001734 <LEDDesign_SuperCrazy+0x84>
}
randomByte = (uint8_t) (0xFF * (((float) rand()) / RAND_MAX));
8001752: f002 fde3 bl 800431c <rand>
8001756: ee07 0a90 vmov s15, r0
800175a: eeb8 7ae7 vcvt.f32.s32 s14, s15
800175e: eddf 6a12 vldr s13, [pc, #72] ; 80017a8 <LEDDesign_SuperCrazy+0xf8>
8001762: eec7 7a26 vdiv.f32 s15, s14, s13
8001766: ed9f 7a11 vldr s14, [pc, #68] ; 80017ac <LEDDesign_SuperCrazy+0xfc>
800176a: ee67 7a87 vmul.f32 s15, s15, s14
800176e: eefc 7ae7 vcvt.u32.f32 s15, s15
8001772: edc7 7a01 vstr s15, [r7, #4]
8001776: 793b ldrb r3, [r7, #4]
8001778: 733b strb r3, [r7, #12]
for(uint8_t i = 0; i < 64; ++i){
800177a: 2300 movs r3, #0
800177c: 737b strb r3, [r7, #13]
800177e: e00b b.n 8001798 <LEDDesign_SuperCrazy+0xe8>
LEDData[i][2] = randomByte;
8001780: 7b7a ldrb r2, [r7, #13]
8001782: 490b ldr r1, [pc, #44] ; (80017b0 <LEDDesign_SuperCrazy+0x100>)
8001784: 4613 mov r3, r2
8001786: 005b lsls r3, r3, #1
8001788: 4413 add r3, r2
800178a: 440b add r3, r1
800178c: 3302 adds r3, #2
800178e: 7b3a ldrb r2, [r7, #12]
8001790: 701a strb r2, [r3, #0]
for(uint8_t i = 0; i < 64; ++i){
8001792: 7b7b ldrb r3, [r7, #13]
8001794: 3301 adds r3, #1
8001796: 737b strb r3, [r7, #13]
8001798: 7b7b ldrb r3, [r7, #13]
800179a: 2b3f cmp r3, #63 ; 0x3f
800179c: d9f0 bls.n 8001780 <LEDDesign_SuperCrazy+0xd0>
}
}
800179e: bf00 nop
80017a0: 3710 adds r7, #16
80017a2: 46bd mov sp, r7
80017a4: bd80 pop {r7, pc}
80017a6: bf00 nop
80017a8: 4f000000 .word 0x4f000000
80017ac: 437f0000 .word 0x437f0000
80017b0: 20000094 .word 0x20000094
080017b4 <updateWS2812BData>:
void updateWS2812BData(void){
80017b4: b490 push {r4, r7}
80017b6: b082 sub sp, #8
80017b8: af00 add r7, sp, #0
uint8_t byteToConvert;
for (uint8_t i = 0; i < 64; ++i) {
80017ba: 2300 movs r3, #0
80017bc: 71fb strb r3, [r7, #7]
80017be: e18b b.n 8001ad8 <updateWS2812BData+0x324>
for (uint8_t j = 0; j < 3; ++j) {
80017c0: 2300 movs r3, #0
80017c2: 71bb strb r3, [r7, #6]
80017c4: e181 b.n 8001aca <updateWS2812BData+0x316>
byteToConvert = LEDData[i][j];
80017c6: 79fa ldrb r2, [r7, #7]
80017c8: 79b9 ldrb r1, [r7, #6]
80017ca: 488e ldr r0, [pc, #568] ; (8001a04 <updateWS2812BData+0x250>)
80017cc: 4613 mov r3, r2
80017ce: 005b lsls r3, r3, #1
80017d0: 4413 add r3, r2
80017d2: 4403 add r3, r0
80017d4: 440b add r3, r1
80017d6: 781b ldrb r3, [r3, #0]
80017d8: 717b strb r3, [r7, #5]
switch((byteToConvert & 0xF0) >> 4){
80017da: 797b ldrb r3, [r7, #5]
80017dc: 091b lsrs r3, r3, #4
80017de: b2db uxtb r3, r3
80017e0: 2b0e cmp r3, #14
80017e2: d85d bhi.n 80018a0 <updateWS2812BData+0xec>
80017e4: a201 add r2, pc, #4 ; (adr r2, 80017ec <updateWS2812BData+0x38>)
80017e6: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80017ea: bf00 nop
80017ec: 08001829 .word 0x08001829
80017f0: 08001831 .word 0x08001831
80017f4: 08001839 .word 0x08001839
80017f8: 08001841 .word 0x08001841
80017fc: 08001849 .word 0x08001849
8001800: 08001851 .word 0x08001851
8001804: 08001859 .word 0x08001859
8001808: 08001861 .word 0x08001861
800180c: 08001869 .word 0x08001869
8001810: 08001871 .word 0x08001871
8001814: 08001879 .word 0x08001879
8001818: 08001881 .word 0x08001881
800181c: 08001889 .word 0x08001889
8001820: 08001891 .word 0x08001891
8001824: 08001899 .word 0x08001899
case 0x00:
WS2812BConvertedData = 0x00924000;
8001828: 4b77 ldr r3, [pc, #476] ; (8001a08 <updateWS2812BData+0x254>)
800182a: 4a78 ldr r2, [pc, #480] ; (8001a0c <updateWS2812BData+0x258>)
800182c: 601a str r2, [r3, #0]
break;
800182e: e03a b.n 80018a6 <updateWS2812BData+0xf2>
case 0x01:
WS2812BConvertedData = 0x00926000;
8001830: 4b75 ldr r3, [pc, #468] ; (8001a08 <updateWS2812BData+0x254>)
8001832: 4a77 ldr r2, [pc, #476] ; (8001a10 <updateWS2812BData+0x25c>)
8001834: 601a str r2, [r3, #0]
break;
8001836: e036 b.n 80018a6 <updateWS2812BData+0xf2>
case 0x02:
WS2812BConvertedData = 0x00934000;
8001838: 4b73 ldr r3, [pc, #460] ; (8001a08 <updateWS2812BData+0x254>)
800183a: 4a76 ldr r2, [pc, #472] ; (8001a14 <updateWS2812BData+0x260>)
800183c: 601a str r2, [r3, #0]
break;
800183e: e032 b.n 80018a6 <updateWS2812BData+0xf2>
case 0x03:
WS2812BConvertedData = 0x00936000;
8001840: 4b71 ldr r3, [pc, #452] ; (8001a08 <updateWS2812BData+0x254>)
8001842: 4a75 ldr r2, [pc, #468] ; (8001a18 <updateWS2812BData+0x264>)
8001844: 601a str r2, [r3, #0]
break;
8001846: e02e b.n 80018a6 <updateWS2812BData+0xf2>
case 0x04:
WS2812BConvertedData = 0x009A4000;
8001848: 4b6f ldr r3, [pc, #444] ; (8001a08 <updateWS2812BData+0x254>)
800184a: 4a74 ldr r2, [pc, #464] ; (8001a1c <updateWS2812BData+0x268>)
800184c: 601a str r2, [r3, #0]
break;
800184e: e02a b.n 80018a6 <updateWS2812BData+0xf2>
case 0x05:
WS2812BConvertedData = 0x009A6000;
8001850: 4b6d ldr r3, [pc, #436] ; (8001a08 <updateWS2812BData+0x254>)
8001852: 4a73 ldr r2, [pc, #460] ; (8001a20 <updateWS2812BData+0x26c>)
8001854: 601a str r2, [r3, #0]
break;
8001856: e026 b.n 80018a6 <updateWS2812BData+0xf2>
case 0x06:
WS2812BConvertedData = 0x009B4000;
8001858: 4b6b ldr r3, [pc, #428] ; (8001a08 <updateWS2812BData+0x254>)
800185a: 4a72 ldr r2, [pc, #456] ; (8001a24 <updateWS2812BData+0x270>)
800185c: 601a str r2, [r3, #0]
break;
800185e: e022 b.n 80018a6 <updateWS2812BData+0xf2>
case 0x07:
WS2812BConvertedData = 0x009B6000;
8001860: 4b69 ldr r3, [pc, #420] ; (8001a08 <updateWS2812BData+0x254>)
8001862: 4a71 ldr r2, [pc, #452] ; (8001a28 <updateWS2812BData+0x274>)
8001864: 601a str r2, [r3, #0]
break;
8001866: e01e b.n 80018a6 <updateWS2812BData+0xf2>
case 0x08:
WS2812BConvertedData = 0x00D24000;
8001868: 4b67 ldr r3, [pc, #412] ; (8001a08 <updateWS2812BData+0x254>)
800186a: 4a70 ldr r2, [pc, #448] ; (8001a2c <updateWS2812BData+0x278>)
800186c: 601a str r2, [r3, #0]
break;
800186e: e01a b.n 80018a6 <updateWS2812BData+0xf2>
case 0x09:
WS2812BConvertedData = 0x00D26000;
8001870: 4b65 ldr r3, [pc, #404] ; (8001a08 <updateWS2812BData+0x254>)
8001872: 4a6f ldr r2, [pc, #444] ; (8001a30 <updateWS2812BData+0x27c>)
8001874: 601a str r2, [r3, #0]
break;
8001876: e016 b.n 80018a6 <updateWS2812BData+0xf2>
case 0x0A:
WS2812BConvertedData = 0x00D34000;
8001878: 4b63 ldr r3, [pc, #396] ; (8001a08 <updateWS2812BData+0x254>)
800187a: 4a6e ldr r2, [pc, #440] ; (8001a34 <updateWS2812BData+0x280>)
800187c: 601a str r2, [r3, #0]
break;
800187e: e012 b.n 80018a6 <updateWS2812BData+0xf2>
case 0x0B:
WS2812BConvertedData = 0x00D36000;
8001880: 4b61 ldr r3, [pc, #388] ; (8001a08 <updateWS2812BData+0x254>)
8001882: 4a6d ldr r2, [pc, #436] ; (8001a38 <updateWS2812BData+0x284>)
8001884: 601a str r2, [r3, #0]
break;
8001886: e00e b.n 80018a6 <updateWS2812BData+0xf2>
case 0x0C:
WS2812BConvertedData = 0x00DA4000;
8001888: 4b5f ldr r3, [pc, #380] ; (8001a08 <updateWS2812BData+0x254>)
800188a: 4a6c ldr r2, [pc, #432] ; (8001a3c <updateWS2812BData+0x288>)
800188c: 601a str r2, [r3, #0]
break;
800188e: e00a b.n 80018a6 <updateWS2812BData+0xf2>
case 0x0D:
WS2812BConvertedData = 0x00DA6000;
8001890: 4b5d ldr r3, [pc, #372] ; (8001a08 <updateWS2812BData+0x254>)
8001892: 4a6b ldr r2, [pc, #428] ; (8001a40 <updateWS2812BData+0x28c>)
8001894: 601a str r2, [r3, #0]
break;
8001896: e006 b.n 80018a6 <updateWS2812BData+0xf2>
case 0x0E:
WS2812BConvertedData = 0x00DB4000;
8001898: 4b5b ldr r3, [pc, #364] ; (8001a08 <updateWS2812BData+0x254>)
800189a: 4a6a ldr r2, [pc, #424] ; (8001a44 <updateWS2812BData+0x290>)
800189c: 601a str r2, [r3, #0]
break;
800189e: e002 b.n 80018a6 <updateWS2812BData+0xf2>
default: // 0x0F
WS2812BConvertedData = 0x00DB6000;
80018a0: 4b59 ldr r3, [pc, #356] ; (8001a08 <updateWS2812BData+0x254>)
80018a2: 4a69 ldr r2, [pc, #420] ; (8001a48 <updateWS2812BData+0x294>)
80018a4: 601a str r2, [r3, #0]
}
switch(byteToConvert & 0x0F){
80018a6: 797b ldrb r3, [r7, #5]
80018a8: f003 030f and.w r3, r3, #15
80018ac: 2b0e cmp r3, #14
80018ae: f200 80cd bhi.w 8001a4c <updateWS2812BData+0x298>
80018b2: a201 add r2, pc, #4 ; (adr r2, 80018b8 <updateWS2812BData+0x104>)
80018b4: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80018b8: 080018f5 .word 0x080018f5
80018bc: 08001907 .word 0x08001907
80018c0: 08001919 .word 0x08001919
80018c4: 0800192b .word 0x0800192b
80018c8: 0800193d .word 0x0800193d
80018cc: 0800194f .word 0x0800194f
80018d0: 08001961 .word 0x08001961
80018d4: 08001973 .word 0x08001973
80018d8: 08001985 .word 0x08001985
80018dc: 08001997 .word 0x08001997
80018e0: 080019a9 .word 0x080019a9
80018e4: 080019bb .word 0x080019bb
80018e8: 080019cd .word 0x080019cd
80018ec: 080019df .word 0x080019df
80018f0: 080019f1 .word 0x080019f1
case 0x00:
WS2812BConvertedData |= 0x00000924;
80018f4: 4b44 ldr r3, [pc, #272] ; (8001a08 <updateWS2812BData+0x254>)
80018f6: 681b ldr r3, [r3, #0]
80018f8: f443 6312 orr.w r3, r3, #2336 ; 0x920
80018fc: f043 0304 orr.w r3, r3, #4
8001900: 4a41 ldr r2, [pc, #260] ; (8001a08 <updateWS2812BData+0x254>)
8001902: 6013 str r3, [r2, #0]
break;
8001904: e0aa b.n 8001a5c <updateWS2812BData+0x2a8>
case 0x01:
WS2812BConvertedData |= 0x00000926;
8001906: 4b40 ldr r3, [pc, #256] ; (8001a08 <updateWS2812BData+0x254>)
8001908: 681b ldr r3, [r3, #0]
800190a: f443 6312 orr.w r3, r3, #2336 ; 0x920
800190e: f043 0306 orr.w r3, r3, #6
8001912: 4a3d ldr r2, [pc, #244] ; (8001a08 <updateWS2812BData+0x254>)
8001914: 6013 str r3, [r2, #0]
break;
8001916: e0a1 b.n 8001a5c <updateWS2812BData+0x2a8>
case 0x02:
WS2812BConvertedData |= 0x00000934;
8001918: 4b3b ldr r3, [pc, #236] ; (8001a08 <updateWS2812BData+0x254>)
800191a: 681b ldr r3, [r3, #0]
800191c: f443 6313 orr.w r3, r3, #2352 ; 0x930
8001920: f043 0304 orr.w r3, r3, #4
8001924: 4a38 ldr r2, [pc, #224] ; (8001a08 <updateWS2812BData+0x254>)
8001926: 6013 str r3, [r2, #0]
break;
8001928: e098 b.n 8001a5c <updateWS2812BData+0x2a8>
case 0x03:
WS2812BConvertedData |= 0x00000936;
800192a: 4b37 ldr r3, [pc, #220] ; (8001a08 <updateWS2812BData+0x254>)
800192c: 681b ldr r3, [r3, #0]
800192e: f443 6313 orr.w r3, r3, #2352 ; 0x930
8001932: f043 0306 orr.w r3, r3, #6
8001936: 4a34 ldr r2, [pc, #208] ; (8001a08 <updateWS2812BData+0x254>)
8001938: 6013 str r3, [r2, #0]
break;
800193a: e08f b.n 8001a5c <updateWS2812BData+0x2a8>
case 0x04:
WS2812BConvertedData |= 0x000009A4;
800193c: 4b32 ldr r3, [pc, #200] ; (8001a08 <updateWS2812BData+0x254>)
800193e: 681b ldr r3, [r3, #0]
8001940: f443 631a orr.w r3, r3, #2464 ; 0x9a0
8001944: f043 0304 orr.w r3, r3, #4
8001948: 4a2f ldr r2, [pc, #188] ; (8001a08 <updateWS2812BData+0x254>)
800194a: 6013 str r3, [r2, #0]
break;
800194c: e086 b.n 8001a5c <updateWS2812BData+0x2a8>
case 0x05:
WS2812BConvertedData |= 0x000009A6;
800194e: 4b2e ldr r3, [pc, #184] ; (8001a08 <updateWS2812BData+0x254>)
8001950: 681b ldr r3, [r3, #0]
8001952: f443 631a orr.w r3, r3, #2464 ; 0x9a0
8001956: f043 0306 orr.w r3, r3, #6
800195a: 4a2b ldr r2, [pc, #172] ; (8001a08 <updateWS2812BData+0x254>)
800195c: 6013 str r3, [r2, #0]
break;
800195e: e07d b.n 8001a5c <updateWS2812BData+0x2a8>
case 0x06:
WS2812BConvertedData |= 0x000009B4;
8001960: 4b29 ldr r3, [pc, #164] ; (8001a08 <updateWS2812BData+0x254>)
8001962: 681b ldr r3, [r3, #0]
8001964: f443 631b orr.w r3, r3, #2480 ; 0x9b0
8001968: f043 0304 orr.w r3, r3, #4
800196c: 4a26 ldr r2, [pc, #152] ; (8001a08 <updateWS2812BData+0x254>)
800196e: 6013 str r3, [r2, #0]
break;
8001970: e074 b.n 8001a5c <updateWS2812BData+0x2a8>
case 0x07:
WS2812BConvertedData |= 0x000009B6;
8001972: 4b25 ldr r3, [pc, #148] ; (8001a08 <updateWS2812BData+0x254>)
8001974: 681b ldr r3, [r3, #0]
8001976: f443 631b orr.w r3, r3, #2480 ; 0x9b0
800197a: f043 0306 orr.w r3, r3, #6
800197e: 4a22 ldr r2, [pc, #136] ; (8001a08 <updateWS2812BData+0x254>)
8001980: 6013 str r3, [r2, #0]
break;
8001982: e06b b.n 8001a5c <updateWS2812BData+0x2a8>
case 0x08:
WS2812BConvertedData |= 0x00000D24;
8001984: 4b20 ldr r3, [pc, #128] ; (8001a08 <updateWS2812BData+0x254>)
8001986: 681b ldr r3, [r3, #0]
8001988: f443 6352 orr.w r3, r3, #3360 ; 0xd20
800198c: f043 0304 orr.w r3, r3, #4
8001990: 4a1d ldr r2, [pc, #116] ; (8001a08 <updateWS2812BData+0x254>)
8001992: 6013 str r3, [r2, #0]
break;
8001994: e062 b.n 8001a5c <updateWS2812BData+0x2a8>
case 0x09:
WS2812BConvertedData |= 0x00000D26;
8001996: 4b1c ldr r3, [pc, #112] ; (8001a08 <updateWS2812BData+0x254>)
8001998: 681b ldr r3, [r3, #0]
800199a: f443 6352 orr.w r3, r3, #3360 ; 0xd20
800199e: f043 0306 orr.w r3, r3, #6
80019a2: 4a19 ldr r2, [pc, #100] ; (8001a08 <updateWS2812BData+0x254>)
80019a4: 6013 str r3, [r2, #0]
break;
80019a6: e059 b.n 8001a5c <updateWS2812BData+0x2a8>
case 0x0A:
WS2812BConvertedData |= 0x00000D34;
80019a8: 4b17 ldr r3, [pc, #92] ; (8001a08 <updateWS2812BData+0x254>)
80019aa: 681b ldr r3, [r3, #0]
80019ac: f443 6353 orr.w r3, r3, #3376 ; 0xd30
80019b0: f043 0304 orr.w r3, r3, #4
80019b4: 4a14 ldr r2, [pc, #80] ; (8001a08 <updateWS2812BData+0x254>)
80019b6: 6013 str r3, [r2, #0]
break;
80019b8: e050 b.n 8001a5c <updateWS2812BData+0x2a8>
case 0x0B:
WS2812BConvertedData |= 0x00000D36;
80019ba: 4b13 ldr r3, [pc, #76] ; (8001a08 <updateWS2812BData+0x254>)
80019bc: 681b ldr r3, [r3, #0]
80019be: f443 6353 orr.w r3, r3, #3376 ; 0xd30
80019c2: f043 0306 orr.w r3, r3, #6
80019c6: 4a10 ldr r2, [pc, #64] ; (8001a08 <updateWS2812BData+0x254>)
80019c8: 6013 str r3, [r2, #0]
break;
80019ca: e047 b.n 8001a5c <updateWS2812BData+0x2a8>
case 0x0C:
WS2812BConvertedData |= 0x00000DA4;
80019cc: 4b0e ldr r3, [pc, #56] ; (8001a08 <updateWS2812BData+0x254>)
80019ce: 681b ldr r3, [r3, #0]
80019d0: f443 635a orr.w r3, r3, #3488 ; 0xda0
80019d4: f043 0304 orr.w r3, r3, #4
80019d8: 4a0b ldr r2, [pc, #44] ; (8001a08 <updateWS2812BData+0x254>)
80019da: 6013 str r3, [r2, #0]
break;
80019dc: e03e b.n 8001a5c <updateWS2812BData+0x2a8>
case 0x0D:
WS2812BConvertedData |= 0x00000DA6;
80019de: 4b0a ldr r3, [pc, #40] ; (8001a08 <updateWS2812BData+0x254>)
80019e0: 681b ldr r3, [r3, #0]
80019e2: f443 635a orr.w r3, r3, #3488 ; 0xda0
80019e6: f043 0306 orr.w r3, r3, #6
80019ea: 4a07 ldr r2, [pc, #28] ; (8001a08 <updateWS2812BData+0x254>)
80019ec: 6013 str r3, [r2, #0]
break;
80019ee: e035 b.n 8001a5c <updateWS2812BData+0x2a8>
case 0x0E:
WS2812BConvertedData |= 0x00000DB4;
80019f0: 4b05 ldr r3, [pc, #20] ; (8001a08 <updateWS2812BData+0x254>)
80019f2: 681b ldr r3, [r3, #0]
80019f4: f443 635b orr.w r3, r3, #3504 ; 0xdb0
80019f8: f043 0304 orr.w r3, r3, #4
80019fc: 4a02 ldr r2, [pc, #8] ; (8001a08 <updateWS2812BData+0x254>)
80019fe: 6013 str r3, [r2, #0]
break;
8001a00: e02c b.n 8001a5c <updateWS2812BData+0x2a8>
8001a02: bf00 nop
8001a04: 20000094 .word 0x20000094
8001a08: 20000498 .word 0x20000498
8001a0c: 00924000 .word 0x00924000
8001a10: 00926000 .word 0x00926000
8001a14: 00934000 .word 0x00934000
8001a18: 00936000 .word 0x00936000
8001a1c: 009a4000 .word 0x009a4000
8001a20: 009a6000 .word 0x009a6000
8001a24: 009b4000 .word 0x009b4000
8001a28: 009b6000 .word 0x009b6000
8001a2c: 00d24000 .word 0x00d24000
8001a30: 00d26000 .word 0x00d26000
8001a34: 00d34000 .word 0x00d34000
8001a38: 00d36000 .word 0x00d36000
8001a3c: 00da4000 .word 0x00da4000
8001a40: 00da6000 .word 0x00da6000
8001a44: 00db4000 .word 0x00db4000
8001a48: 00db6000 .word 0x00db6000
default: // 0x0F
WS2812BConvertedData |= 0x00000DB6;
8001a4c: 4b27 ldr r3, [pc, #156] ; (8001aec <updateWS2812BData+0x338>)
8001a4e: 681b ldr r3, [r3, #0]
8001a50: f443 635b orr.w r3, r3, #3504 ; 0xdb0
8001a54: f043 0306 orr.w r3, r3, #6
8001a58: 4a24 ldr r2, [pc, #144] ; (8001aec <updateWS2812BData+0x338>)
8001a5a: 6013 str r3, [r2, #0]
}
LEDData_WS2812B[i][j][0] = (WS2812BConvertedData & 0x00FF0000) >> 16;
8001a5c: 4b23 ldr r3, [pc, #140] ; (8001aec <updateWS2812BData+0x338>)
8001a5e: 681b ldr r3, [r3, #0]
8001a60: 0c1a lsrs r2, r3, #16
8001a62: 79f9 ldrb r1, [r7, #7]
8001a64: 79bb ldrb r3, [r7, #6]
8001a66: b2d4 uxtb r4, r2
8001a68: 4821 ldr r0, [pc, #132] ; (8001af0 <updateWS2812BData+0x33c>)
8001a6a: 461a mov r2, r3
8001a6c: 0052 lsls r2, r2, #1
8001a6e: 441a add r2, r3
8001a70: 460b mov r3, r1
8001a72: 00db lsls r3, r3, #3
8001a74: 440b add r3, r1
8001a76: 4413 add r3, r2
8001a78: 4403 add r3, r0
8001a7a: 4622 mov r2, r4
8001a7c: 701a strb r2, [r3, #0]
LEDData_WS2812B[i][j][1] = (WS2812BConvertedData & 0x0000FF00) >> 8;
8001a7e: 4b1b ldr r3, [pc, #108] ; (8001aec <updateWS2812BData+0x338>)
8001a80: 681b ldr r3, [r3, #0]
8001a82: 0a1a lsrs r2, r3, #8
8001a84: 79f9 ldrb r1, [r7, #7]
8001a86: 79bb ldrb r3, [r7, #6]
8001a88: b2d4 uxtb r4, r2
8001a8a: 4819 ldr r0, [pc, #100] ; (8001af0 <updateWS2812BData+0x33c>)
8001a8c: 461a mov r2, r3
8001a8e: 0052 lsls r2, r2, #1
8001a90: 441a add r2, r3
8001a92: 460b mov r3, r1
8001a94: 00db lsls r3, r3, #3
8001a96: 440b add r3, r1
8001a98: 4413 add r3, r2
8001a9a: 4403 add r3, r0
8001a9c: 3301 adds r3, #1
8001a9e: 4622 mov r2, r4
8001aa0: 701a strb r2, [r3, #0]
LEDData_WS2812B[i][j][2] = WS2812BConvertedData & 0x000000FF;
8001aa2: 4b12 ldr r3, [pc, #72] ; (8001aec <updateWS2812BData+0x338>)
8001aa4: 681a ldr r2, [r3, #0]
8001aa6: 79f9 ldrb r1, [r7, #7]
8001aa8: 79bb ldrb r3, [r7, #6]
8001aaa: b2d4 uxtb r4, r2
8001aac: 4810 ldr r0, [pc, #64] ; (8001af0 <updateWS2812BData+0x33c>)
8001aae: 461a mov r2, r3
8001ab0: 0052 lsls r2, r2, #1
8001ab2: 441a add r2, r3
8001ab4: 460b mov r3, r1
8001ab6: 00db lsls r3, r3, #3
8001ab8: 440b add r3, r1
8001aba: 4413 add r3, r2
8001abc: 4403 add r3, r0
8001abe: 3302 adds r3, #2
8001ac0: 4622 mov r2, r4
8001ac2: 701a strb r2, [r3, #0]
for (uint8_t j = 0; j < 3; ++j) {
8001ac4: 79bb ldrb r3, [r7, #6]
8001ac6: 3301 adds r3, #1
8001ac8: 71bb strb r3, [r7, #6]
8001aca: 79bb ldrb r3, [r7, #6]
8001acc: 2b02 cmp r3, #2
8001ace: f67f ae7a bls.w 80017c6 <updateWS2812BData+0x12>
for (uint8_t i = 0; i < 64; ++i) {
8001ad2: 79fb ldrb r3, [r7, #7]
8001ad4: 3301 adds r3, #1
8001ad6: 71fb strb r3, [r7, #7]
8001ad8: 79fb ldrb r3, [r7, #7]
8001ada: 2b3f cmp r3, #63 ; 0x3f
8001adc: f67f ae70 bls.w 80017c0 <updateWS2812BData+0xc>
}
}
}
8001ae0: bf00 nop
8001ae2: 3708 adds r7, #8
8001ae4: 46bd mov sp, r7
8001ae6: bc90 pop {r4, r7}
8001ae8: 4770 bx lr
8001aea: bf00 nop
8001aec: 20000498 .word 0x20000498
8001af0: 20000154 .word 0x20000154
08001af4 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
8001af4: b480 push {r7}
8001af6: af00 add r7, sp, #0
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
/* USER CODE END Error_Handler_Debug */
}
8001af8: bf00 nop
8001afa: 46bd mov sp, r7
8001afc: f85d 7b04 ldr.w r7, [sp], #4
8001b00: 4770 bx lr
...
08001b04 <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8001b04: b580 push {r7, lr}
8001b06: b082 sub sp, #8
8001b08: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8001b0a: 2300 movs r3, #0
8001b0c: 607b str r3, [r7, #4]
8001b0e: 4b10 ldr r3, [pc, #64] ; (8001b50 <HAL_MspInit+0x4c>)
8001b10: 6c5b ldr r3, [r3, #68] ; 0x44
8001b12: 4a0f ldr r2, [pc, #60] ; (8001b50 <HAL_MspInit+0x4c>)
8001b14: f443 4380 orr.w r3, r3, #16384 ; 0x4000
8001b18: 6453 str r3, [r2, #68] ; 0x44
8001b1a: 4b0d ldr r3, [pc, #52] ; (8001b50 <HAL_MspInit+0x4c>)
8001b1c: 6c5b ldr r3, [r3, #68] ; 0x44
8001b1e: f403 4380 and.w r3, r3, #16384 ; 0x4000
8001b22: 607b str r3, [r7, #4]
8001b24: 687b ldr r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
8001b26: 2300 movs r3, #0
8001b28: 603b str r3, [r7, #0]
8001b2a: 4b09 ldr r3, [pc, #36] ; (8001b50 <HAL_MspInit+0x4c>)
8001b2c: 6c1b ldr r3, [r3, #64] ; 0x40
8001b2e: 4a08 ldr r2, [pc, #32] ; (8001b50 <HAL_MspInit+0x4c>)
8001b30: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8001b34: 6413 str r3, [r2, #64] ; 0x40
8001b36: 4b06 ldr r3, [pc, #24] ; (8001b50 <HAL_MspInit+0x4c>)
8001b38: 6c1b ldr r3, [r3, #64] ; 0x40
8001b3a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8001b3e: 603b str r3, [r7, #0]
8001b40: 683b ldr r3, [r7, #0]
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_0);
8001b42: 2007 movs r0, #7
8001b44: f000 fedc bl 8002900 <HAL_NVIC_SetPriorityGrouping>
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
8001b48: bf00 nop
8001b4a: 3708 adds r7, #8
8001b4c: 46bd mov sp, r7
8001b4e: bd80 pop {r7, pc}
8001b50: 40023800 .word 0x40023800
08001b54 <HAL_ADC_MspInit>:
* This function configures the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
{
8001b54: b580 push {r7, lr}
8001b56: b08a sub sp, #40 ; 0x28
8001b58: af00 add r7, sp, #0
8001b5a: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001b5c: f107 0314 add.w r3, r7, #20
8001b60: 2200 movs r2, #0
8001b62: 601a str r2, [r3, #0]
8001b64: 605a str r2, [r3, #4]
8001b66: 609a str r2, [r3, #8]
8001b68: 60da str r2, [r3, #12]
8001b6a: 611a str r2, [r3, #16]
if(hadc->Instance==ADC3)
8001b6c: 687b ldr r3, [r7, #4]
8001b6e: 681b ldr r3, [r3, #0]
8001b70: 4a17 ldr r2, [pc, #92] ; (8001bd0 <HAL_ADC_MspInit+0x7c>)
8001b72: 4293 cmp r3, r2
8001b74: d127 bne.n 8001bc6 <HAL_ADC_MspInit+0x72>
{
/* USER CODE BEGIN ADC3_MspInit 0 */
/* USER CODE END ADC3_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_ADC3_CLK_ENABLE();
8001b76: 2300 movs r3, #0
8001b78: 613b str r3, [r7, #16]
8001b7a: 4b16 ldr r3, [pc, #88] ; (8001bd4 <HAL_ADC_MspInit+0x80>)
8001b7c: 6c5b ldr r3, [r3, #68] ; 0x44
8001b7e: 4a15 ldr r2, [pc, #84] ; (8001bd4 <HAL_ADC_MspInit+0x80>)
8001b80: f443 6380 orr.w r3, r3, #1024 ; 0x400
8001b84: 6453 str r3, [r2, #68] ; 0x44
8001b86: 4b13 ldr r3, [pc, #76] ; (8001bd4 <HAL_ADC_MspInit+0x80>)
8001b88: 6c5b ldr r3, [r3, #68] ; 0x44
8001b8a: f403 6380 and.w r3, r3, #1024 ; 0x400
8001b8e: 613b str r3, [r7, #16]
8001b90: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOF_CLK_ENABLE();
8001b92: 2300 movs r3, #0
8001b94: 60fb str r3, [r7, #12]
8001b96: 4b0f ldr r3, [pc, #60] ; (8001bd4 <HAL_ADC_MspInit+0x80>)
8001b98: 6b1b ldr r3, [r3, #48] ; 0x30
8001b9a: 4a0e ldr r2, [pc, #56] ; (8001bd4 <HAL_ADC_MspInit+0x80>)
8001b9c: f043 0320 orr.w r3, r3, #32
8001ba0: 6313 str r3, [r2, #48] ; 0x30
8001ba2: 4b0c ldr r3, [pc, #48] ; (8001bd4 <HAL_ADC_MspInit+0x80>)
8001ba4: 6b1b ldr r3, [r3, #48] ; 0x30
8001ba6: f003 0320 and.w r3, r3, #32
8001baa: 60fb str r3, [r7, #12]
8001bac: 68fb ldr r3, [r7, #12]
/**ADC3 GPIO Configuration
PF6 ------> ADC3_IN4
*/
GPIO_InitStruct.Pin = GPIO_PIN_6;
8001bae: 2340 movs r3, #64 ; 0x40
8001bb0: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8001bb2: 2303 movs r3, #3
8001bb4: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001bb6: 2300 movs r3, #0
8001bb8: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
8001bba: f107 0314 add.w r3, r7, #20
8001bbe: 4619 mov r1, r3
8001bc0: 4805 ldr r0, [pc, #20] ; (8001bd8 <HAL_ADC_MspInit+0x84>)
8001bc2: f000 ff01 bl 80029c8 <HAL_GPIO_Init>
/* USER CODE BEGIN ADC3_MspInit 1 */
/* USER CODE END ADC3_MspInit 1 */
}
}
8001bc6: bf00 nop
8001bc8: 3728 adds r7, #40 ; 0x28
8001bca: 46bd mov sp, r7
8001bcc: bd80 pop {r7, pc}
8001bce: bf00 nop
8001bd0: 40012200 .word 0x40012200
8001bd4: 40023800 .word 0x40023800
8001bd8: 40021400 .word 0x40021400
08001bdc <HAL_SPI_MspInit>:
* This function configures the hardware resources used in this example
* @param hspi: SPI handle pointer
* @retval None
*/
void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
{
8001bdc: b580 push {r7, lr}
8001bde: b08a sub sp, #40 ; 0x28
8001be0: af00 add r7, sp, #0
8001be2: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001be4: f107 0314 add.w r3, r7, #20
8001be8: 2200 movs r2, #0
8001bea: 601a str r2, [r3, #0]
8001bec: 605a str r2, [r3, #4]
8001bee: 609a str r2, [r3, #8]
8001bf0: 60da str r2, [r3, #12]
8001bf2: 611a str r2, [r3, #16]
if(hspi->Instance==SPI4)
8001bf4: 687b ldr r3, [r7, #4]
8001bf6: 681b ldr r3, [r3, #0]
8001bf8: 4a1d ldr r2, [pc, #116] ; (8001c70 <HAL_SPI_MspInit+0x94>)
8001bfa: 4293 cmp r3, r2
8001bfc: d133 bne.n 8001c66 <HAL_SPI_MspInit+0x8a>
{
/* USER CODE BEGIN SPI4_MspInit 0 */
/* USER CODE END SPI4_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_SPI4_CLK_ENABLE();
8001bfe: 2300 movs r3, #0
8001c00: 613b str r3, [r7, #16]
8001c02: 4b1c ldr r3, [pc, #112] ; (8001c74 <HAL_SPI_MspInit+0x98>)
8001c04: 6c5b ldr r3, [r3, #68] ; 0x44
8001c06: 4a1b ldr r2, [pc, #108] ; (8001c74 <HAL_SPI_MspInit+0x98>)
8001c08: f443 5300 orr.w r3, r3, #8192 ; 0x2000
8001c0c: 6453 str r3, [r2, #68] ; 0x44
8001c0e: 4b19 ldr r3, [pc, #100] ; (8001c74 <HAL_SPI_MspInit+0x98>)
8001c10: 6c5b ldr r3, [r3, #68] ; 0x44
8001c12: f403 5300 and.w r3, r3, #8192 ; 0x2000
8001c16: 613b str r3, [r7, #16]
8001c18: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOE_CLK_ENABLE();
8001c1a: 2300 movs r3, #0
8001c1c: 60fb str r3, [r7, #12]
8001c1e: 4b15 ldr r3, [pc, #84] ; (8001c74 <HAL_SPI_MspInit+0x98>)
8001c20: 6b1b ldr r3, [r3, #48] ; 0x30
8001c22: 4a14 ldr r2, [pc, #80] ; (8001c74 <HAL_SPI_MspInit+0x98>)
8001c24: f043 0310 orr.w r3, r3, #16
8001c28: 6313 str r3, [r2, #48] ; 0x30
8001c2a: 4b12 ldr r3, [pc, #72] ; (8001c74 <HAL_SPI_MspInit+0x98>)
8001c2c: 6b1b ldr r3, [r3, #48] ; 0x30
8001c2e: f003 0310 and.w r3, r3, #16
8001c32: 60fb str r3, [r7, #12]
8001c34: 68fb ldr r3, [r7, #12]
/**SPI4 GPIO Configuration
PE2 ------> SPI4_SCK
PE6 ------> SPI4_MOSI
*/
GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_6;
8001c36: 2344 movs r3, #68 ; 0x44
8001c38: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001c3a: 2302 movs r3, #2
8001c3c: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001c3e: 2300 movs r3, #0
8001c40: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001c42: 2303 movs r3, #3
8001c44: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF5_SPI4;
8001c46: 2305 movs r3, #5
8001c48: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
8001c4a: f107 0314 add.w r3, r7, #20
8001c4e: 4619 mov r1, r3
8001c50: 4809 ldr r0, [pc, #36] ; (8001c78 <HAL_SPI_MspInit+0x9c>)
8001c52: f000 feb9 bl 80029c8 <HAL_GPIO_Init>
/* SPI4 interrupt Init */
HAL_NVIC_SetPriority(SPI4_IRQn, 0, 0);
8001c56: 2200 movs r2, #0
8001c58: 2100 movs r1, #0
8001c5a: 2054 movs r0, #84 ; 0x54
8001c5c: f000 fe5b bl 8002916 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(SPI4_IRQn);
8001c60: 2054 movs r0, #84 ; 0x54
8001c62: f000 fe74 bl 800294e <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN SPI4_MspInit 1 */
/* USER CODE END SPI4_MspInit 1 */
}
}
8001c66: bf00 nop
8001c68: 3728 adds r7, #40 ; 0x28
8001c6a: 46bd mov sp, r7
8001c6c: bd80 pop {r7, pc}
8001c6e: bf00 nop
8001c70: 40013400 .word 0x40013400
8001c74: 40023800 .word 0x40023800
8001c78: 40021000 .word 0x40021000
08001c7c <HAL_TIM_Base_MspInit>:
* This function configures the hardware resources used in this example
* @param htim_base: TIM_Base handle pointer
* @retval None
*/
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
{
8001c7c: b580 push {r7, lr}
8001c7e: b084 sub sp, #16
8001c80: af00 add r7, sp, #0
8001c82: 6078 str r0, [r7, #4]
if(htim_base->Instance==TIM6)
8001c84: 687b ldr r3, [r7, #4]
8001c86: 681b ldr r3, [r3, #0]
8001c88: 4a0e ldr r2, [pc, #56] ; (8001cc4 <HAL_TIM_Base_MspInit+0x48>)
8001c8a: 4293 cmp r3, r2
8001c8c: d115 bne.n 8001cba <HAL_TIM_Base_MspInit+0x3e>
{
/* USER CODE BEGIN TIM6_MspInit 0 */
/* USER CODE END TIM6_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_TIM6_CLK_ENABLE();
8001c8e: 2300 movs r3, #0
8001c90: 60fb str r3, [r7, #12]
8001c92: 4b0d ldr r3, [pc, #52] ; (8001cc8 <HAL_TIM_Base_MspInit+0x4c>)
8001c94: 6c1b ldr r3, [r3, #64] ; 0x40
8001c96: 4a0c ldr r2, [pc, #48] ; (8001cc8 <HAL_TIM_Base_MspInit+0x4c>)
8001c98: f043 0310 orr.w r3, r3, #16
8001c9c: 6413 str r3, [r2, #64] ; 0x40
8001c9e: 4b0a ldr r3, [pc, #40] ; (8001cc8 <HAL_TIM_Base_MspInit+0x4c>)
8001ca0: 6c1b ldr r3, [r3, #64] ; 0x40
8001ca2: f003 0310 and.w r3, r3, #16
8001ca6: 60fb str r3, [r7, #12]
8001ca8: 68fb ldr r3, [r7, #12]
/* TIM6 interrupt Init */
HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 0, 0);
8001caa: 2200 movs r2, #0
8001cac: 2100 movs r1, #0
8001cae: 2036 movs r0, #54 ; 0x36
8001cb0: f000 fe31 bl 8002916 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
8001cb4: 2036 movs r0, #54 ; 0x36
8001cb6: f000 fe4a bl 800294e <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN TIM6_MspInit 1 */
/* USER CODE END TIM6_MspInit 1 */
}
}
8001cba: bf00 nop
8001cbc: 3710 adds r7, #16
8001cbe: 46bd mov sp, r7
8001cc0: bd80 pop {r7, pc}
8001cc2: bf00 nop
8001cc4: 40001000 .word 0x40001000
8001cc8: 40023800 .word 0x40023800
08001ccc <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8001ccc: b480 push {r7}
8001cce: af00 add r7, sp, #0
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
/* USER CODE END NonMaskableInt_IRQn 1 */
}
8001cd0: bf00 nop
8001cd2: 46bd mov sp, r7
8001cd4: f85d 7b04 ldr.w r7, [sp], #4
8001cd8: 4770 bx lr
08001cda <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8001cda: b480 push {r7}
8001cdc: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8001cde: e7fe b.n 8001cde <HardFault_Handler+0x4>
08001ce0 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
8001ce0: b480 push {r7}
8001ce2: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8001ce4: e7fe b.n 8001ce4 <MemManage_Handler+0x4>
08001ce6 <BusFault_Handler>:
/**
* @brief This function handles Pre-fetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
8001ce6: b480 push {r7}
8001ce8: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
8001cea: e7fe b.n 8001cea <BusFault_Handler+0x4>
08001cec <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
8001cec: b480 push {r7}
8001cee: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8001cf0: e7fe b.n 8001cf0 <UsageFault_Handler+0x4>
08001cf2 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
8001cf2: b480 push {r7}
8001cf4: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
8001cf6: bf00 nop
8001cf8: 46bd mov sp, r7
8001cfa: f85d 7b04 ldr.w r7, [sp], #4
8001cfe: 4770 bx lr
08001d00 <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
8001d00: b480 push {r7}
8001d02: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
8001d04: bf00 nop
8001d06: 46bd mov sp, r7
8001d08: f85d 7b04 ldr.w r7, [sp], #4
8001d0c: 4770 bx lr
08001d0e <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
8001d0e: b480 push {r7}
8001d10: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
8001d12: bf00 nop
8001d14: 46bd mov sp, r7
8001d16: f85d 7b04 ldr.w r7, [sp], #4
8001d1a: 4770 bx lr
08001d1c <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
8001d1c: b580 push {r7, lr}
8001d1e: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
8001d20: f000 f912 bl 8001f48 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
8001d24: bf00 nop
8001d26: bd80 pop {r7, pc}
08001d28 <EXTI0_IRQHandler>:
/**
* @brief This function handles EXTI line0 interrupt.
*/
void EXTI0_IRQHandler(void)
{
8001d28: b580 push {r7, lr}
8001d2a: af00 add r7, sp, #0
/* USER CODE BEGIN EXTI0_IRQn 0 */
/* USER CODE END EXTI0_IRQn 0 */
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_0);
8001d2c: 2001 movs r0, #1
8001d2e: f001 f80f bl 8002d50 <HAL_GPIO_EXTI_IRQHandler>
/* USER CODE BEGIN EXTI0_IRQn 1 */
HAL_TIM_Base_Start_IT(&htim6);
8001d32: 4804 ldr r0, [pc, #16] ; (8001d44 <EXTI0_IRQHandler+0x1c>)
8001d34: f001 ffeb bl 8003d0e <HAL_TIM_Base_Start_IT>
LEDDesign_PendingChange = true;
8001d38: 4b03 ldr r3, [pc, #12] ; (8001d48 <EXTI0_IRQHandler+0x20>)
8001d3a: 2201 movs r2, #1
8001d3c: 701a strb r2, [r3, #0]
/* USER CODE END EXTI0_IRQn 1 */
}
8001d3e: bf00 nop
8001d40: bd80 pop {r7, pc}
8001d42: bf00 nop
8001d44: 20000458 .word 0x20000458
8001d48: 20000091 .word 0x20000091
08001d4c <TIM6_DAC_IRQHandler>:
/**
* @brief This function handles TIM6 global interrupt, DAC1 and DAC2 underrun error interrupts.
*/
void TIM6_DAC_IRQHandler(void)
{
8001d4c: b580 push {r7, lr}
8001d4e: af00 add r7, sp, #0
/* USER CODE BEGIN TIM6_DAC_IRQn 0 */
/* USER CODE END TIM6_DAC_IRQn 0 */
HAL_TIM_IRQHandler(&htim6);
8001d50: 480c ldr r0, [pc, #48] ; (8001d84 <TIM6_DAC_IRQHandler+0x38>)
8001d52: f002 f846 bl 8003de2 <HAL_TIM_IRQHandler>
/* USER CODE BEGIN TIM6_DAC_IRQn 1 */
LEDMode = (LEDMode + 1) % 7;
8001d56: 4b0c ldr r3, [pc, #48] ; (8001d88 <TIM6_DAC_IRQHandler+0x3c>)
8001d58: 781b ldrb r3, [r3, #0]
8001d5a: 1c5a adds r2, r3, #1
8001d5c: 4b0b ldr r3, [pc, #44] ; (8001d8c <TIM6_DAC_IRQHandler+0x40>)
8001d5e: fb83 1302 smull r1, r3, r3, r2
8001d62: 4413 add r3, r2
8001d64: 1099 asrs r1, r3, #2
8001d66: 17d3 asrs r3, r2, #31
8001d68: 1ac9 subs r1, r1, r3
8001d6a: 460b mov r3, r1
8001d6c: 00db lsls r3, r3, #3
8001d6e: 1a5b subs r3, r3, r1
8001d70: 1ad1 subs r1, r2, r3
8001d72: b2ca uxtb r2, r1
8001d74: 4b04 ldr r3, [pc, #16] ; (8001d88 <TIM6_DAC_IRQHandler+0x3c>)
8001d76: 701a strb r2, [r3, #0]
LEDDesign_PendingChange = false;
8001d78: 4b05 ldr r3, [pc, #20] ; (8001d90 <TIM6_DAC_IRQHandler+0x44>)
8001d7a: 2200 movs r2, #0
8001d7c: 701a strb r2, [r3, #0]
/* USER CODE END TIM6_DAC_IRQn 1 */
}
8001d7e: bf00 nop
8001d80: bd80 pop {r7, pc}
8001d82: bf00 nop
8001d84: 20000458 .word 0x20000458
8001d88: 20000090 .word 0x20000090
8001d8c: 92492493 .word 0x92492493
8001d90: 20000091 .word 0x20000091
08001d94 <SPI4_IRQHandler>:
/**
* @brief This function handles SPI4 global interrupt.
*/
void SPI4_IRQHandler(void)
{
8001d94: b580 push {r7, lr}
8001d96: af00 add r7, sp, #0
/* USER CODE BEGIN SPI4_IRQn 0 */
/* USER CODE END SPI4_IRQn 0 */
HAL_SPI_IRQHandler(&hspi4);
8001d98: 4805 ldr r0, [pc, #20] ; (8001db0 <SPI4_IRQHandler+0x1c>)
8001d9a: f001 fd11 bl 80037c0 <HAL_SPI_IRQHandler>
/* USER CODE BEGIN SPI4_IRQn 1 */
HAL_SPI_Transmit_IT(&hspi4, (uint8_t *) &LEDData_WS2812B, (uint16_t) 66 * 3 * 3);
8001d9e: f240 2252 movw r2, #594 ; 0x252
8001da2: 4904 ldr r1, [pc, #16] ; (8001db4 <SPI4_IRQHandler+0x20>)
8001da4: 4802 ldr r0, [pc, #8] ; (8001db0 <SPI4_IRQHandler+0x1c>)
8001da6: f001 fc89 bl 80036bc <HAL_SPI_Transmit_IT>
/* USER CODE END SPI4_IRQn 1 */
}
8001daa: bf00 nop
8001dac: bd80 pop {r7, pc}
8001dae: bf00 nop
8001db0: 20000400 .word 0x20000400
8001db4: 20000154 .word 0x20000154
08001db8 <_sbrk>:
*
* @param incr Memory size
* @return Pointer to allocated memory
*/
void *_sbrk(ptrdiff_t incr)
{
8001db8: b580 push {r7, lr}
8001dba: b086 sub sp, #24
8001dbc: af00 add r7, sp, #0
8001dbe: 6078 str r0, [r7, #4]
extern uint8_t _end; /* Symbol defined in the linker script */
extern uint8_t _estack; /* Symbol defined in the linker script */
extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
8001dc0: 4a14 ldr r2, [pc, #80] ; (8001e14 <_sbrk+0x5c>)
8001dc2: 4b15 ldr r3, [pc, #84] ; (8001e18 <_sbrk+0x60>)
8001dc4: 1ad3 subs r3, r2, r3
8001dc6: 617b str r3, [r7, #20]
const uint8_t *max_heap = (uint8_t *)stack_limit;
8001dc8: 697b ldr r3, [r7, #20]
8001dca: 613b str r3, [r7, #16]
uint8_t *prev_heap_end;
/* Initalize heap end at first call */
if (NULL == __sbrk_heap_end)
8001dcc: 4b13 ldr r3, [pc, #76] ; (8001e1c <_sbrk+0x64>)
8001dce: 681b ldr r3, [r3, #0]
8001dd0: 2b00 cmp r3, #0
8001dd2: d102 bne.n 8001dda <_sbrk+0x22>
{
__sbrk_heap_end = &_end;
8001dd4: 4b11 ldr r3, [pc, #68] ; (8001e1c <_sbrk+0x64>)
8001dd6: 4a12 ldr r2, [pc, #72] ; (8001e20 <_sbrk+0x68>)
8001dd8: 601a str r2, [r3, #0]
}
/* Protect heap from growing into the reserved MSP stack */
if (__sbrk_heap_end + incr > max_heap)
8001dda: 4b10 ldr r3, [pc, #64] ; (8001e1c <_sbrk+0x64>)
8001ddc: 681a ldr r2, [r3, #0]
8001dde: 687b ldr r3, [r7, #4]
8001de0: 4413 add r3, r2
8001de2: 693a ldr r2, [r7, #16]
8001de4: 429a cmp r2, r3
8001de6: d207 bcs.n 8001df8 <_sbrk+0x40>
{
errno = ENOMEM;
8001de8: f002 fa66 bl 80042b8 <__errno>
8001dec: 4602 mov r2, r0
8001dee: 230c movs r3, #12
8001df0: 6013 str r3, [r2, #0]
return (void *)-1;
8001df2: f04f 33ff mov.w r3, #4294967295
8001df6: e009 b.n 8001e0c <_sbrk+0x54>
}
prev_heap_end = __sbrk_heap_end;
8001df8: 4b08 ldr r3, [pc, #32] ; (8001e1c <_sbrk+0x64>)
8001dfa: 681b ldr r3, [r3, #0]
8001dfc: 60fb str r3, [r7, #12]
__sbrk_heap_end += incr;
8001dfe: 4b07 ldr r3, [pc, #28] ; (8001e1c <_sbrk+0x64>)
8001e00: 681a ldr r2, [r3, #0]
8001e02: 687b ldr r3, [r7, #4]
8001e04: 4413 add r3, r2
8001e06: 4a05 ldr r2, [pc, #20] ; (8001e1c <_sbrk+0x64>)
8001e08: 6013 str r3, [r2, #0]
return (void *)prev_heap_end;
8001e0a: 68fb ldr r3, [r7, #12]
}
8001e0c: 4618 mov r0, r3
8001e0e: 3718 adds r7, #24
8001e10: 46bd mov sp, r7
8001e12: bd80 pop {r7, pc}
8001e14: 20030000 .word 0x20030000
8001e18: 00000400 .word 0x00000400
8001e1c: 200003ac .word 0x200003ac
8001e20: 200004a8 .word 0x200004a8
08001e24 <SystemInit>:
* configuration.
* @param None
* @retval None
*/
void SystemInit(void)
{
8001e24: b480 push {r7}
8001e26: af00 add r7, sp, #0
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
8001e28: 4b08 ldr r3, [pc, #32] ; (8001e4c <SystemInit+0x28>)
8001e2a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
8001e2e: 4a07 ldr r2, [pc, #28] ; (8001e4c <SystemInit+0x28>)
8001e30: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
8001e34: f8c2 3088 str.w r3, [r2, #136] ; 0x88
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
8001e38: 4b04 ldr r3, [pc, #16] ; (8001e4c <SystemInit+0x28>)
8001e3a: f04f 6200 mov.w r2, #134217728 ; 0x8000000
8001e3e: 609a str r2, [r3, #8]
#endif
}
8001e40: bf00 nop
8001e42: 46bd mov sp, r7
8001e44: f85d 7b04 ldr.w r7, [sp], #4
8001e48: 4770 bx lr
8001e4a: bf00 nop
8001e4c: e000ed00 .word 0xe000ed00
08001e50 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
8001e50: f8df d034 ldr.w sp, [pc, #52] ; 8001e88 <LoopFillZerobss+0x14>
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
8001e54: 2100 movs r1, #0
b LoopCopyDataInit
8001e56: e003 b.n 8001e60 <LoopCopyDataInit>
08001e58 <CopyDataInit>:
CopyDataInit:
ldr r3, =_sidata
8001e58: 4b0c ldr r3, [pc, #48] ; (8001e8c <LoopFillZerobss+0x18>)
ldr r3, [r3, r1]
8001e5a: 585b ldr r3, [r3, r1]
str r3, [r0, r1]
8001e5c: 5043 str r3, [r0, r1]
adds r1, r1, #4
8001e5e: 3104 adds r1, #4
08001e60 <LoopCopyDataInit>:
LoopCopyDataInit:
ldr r0, =_sdata
8001e60: 480b ldr r0, [pc, #44] ; (8001e90 <LoopFillZerobss+0x1c>)
ldr r3, =_edata
8001e62: 4b0c ldr r3, [pc, #48] ; (8001e94 <LoopFillZerobss+0x20>)
adds r2, r0, r1
8001e64: 1842 adds r2, r0, r1
cmp r2, r3
8001e66: 429a cmp r2, r3
bcc CopyDataInit
8001e68: d3f6 bcc.n 8001e58 <CopyDataInit>
ldr r2, =_sbss
8001e6a: 4a0b ldr r2, [pc, #44] ; (8001e98 <LoopFillZerobss+0x24>)
b LoopFillZerobss
8001e6c: e002 b.n 8001e74 <LoopFillZerobss>
08001e6e <FillZerobss>:
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
8001e6e: 2300 movs r3, #0
str r3, [r2], #4
8001e70: f842 3b04 str.w r3, [r2], #4
08001e74 <LoopFillZerobss>:
LoopFillZerobss:
ldr r3, = _ebss
8001e74: 4b09 ldr r3, [pc, #36] ; (8001e9c <LoopFillZerobss+0x28>)
cmp r2, r3
8001e76: 429a cmp r2, r3
bcc FillZerobss
8001e78: d3f9 bcc.n 8001e6e <FillZerobss>
/* Call the clock system intitialization function.*/
bl SystemInit
8001e7a: f7ff ffd3 bl 8001e24 <SystemInit>
/* Call static constructors */
bl __libc_init_array
8001e7e: f002 fa21 bl 80042c4 <__libc_init_array>
/* Call the application's entry point.*/
bl main
8001e82: f7fe fb33 bl 80004ec <main>
bx lr
8001e86: 4770 bx lr
ldr sp, =_estack /* set stack pointer */
8001e88: 20030000 .word 0x20030000
ldr r3, =_sidata
8001e8c: 080044a4 .word 0x080044a4
ldr r0, =_sdata
8001e90: 20000000 .word 0x20000000
ldr r3, =_edata
8001e94: 20000074 .word 0x20000074
ldr r2, =_sbss
8001e98: 20000074 .word 0x20000074
ldr r3, = _ebss
8001e9c: 200004a4 .word 0x200004a4
08001ea0 <ADC_IRQHandler>:
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8001ea0: e7fe b.n 8001ea0 <ADC_IRQHandler>
...
08001ea4 <HAL_Init>:
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
8001ea4: b580 push {r7, lr}
8001ea6: af00 add r7, sp, #0
/* Configure Flash prefetch, Instruction cache, Data cache */
#if (INSTRUCTION_CACHE_ENABLE != 0U)
__HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
8001ea8: 4b0e ldr r3, [pc, #56] ; (8001ee4 <HAL_Init+0x40>)
8001eaa: 681b ldr r3, [r3, #0]
8001eac: 4a0d ldr r2, [pc, #52] ; (8001ee4 <HAL_Init+0x40>)
8001eae: f443 7300 orr.w r3, r3, #512 ; 0x200
8001eb2: 6013 str r3, [r2, #0]
#endif /* INSTRUCTION_CACHE_ENABLE */
#if (DATA_CACHE_ENABLE != 0U)
__HAL_FLASH_DATA_CACHE_ENABLE();
8001eb4: 4b0b ldr r3, [pc, #44] ; (8001ee4 <HAL_Init+0x40>)
8001eb6: 681b ldr r3, [r3, #0]
8001eb8: 4a0a ldr r2, [pc, #40] ; (8001ee4 <HAL_Init+0x40>)
8001eba: f443 6380 orr.w r3, r3, #1024 ; 0x400
8001ebe: 6013 str r3, [r2, #0]
#endif /* DATA_CACHE_ENABLE */
#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
8001ec0: 4b08 ldr r3, [pc, #32] ; (8001ee4 <HAL_Init+0x40>)
8001ec2: 681b ldr r3, [r3, #0]
8001ec4: 4a07 ldr r2, [pc, #28] ; (8001ee4 <HAL_Init+0x40>)
8001ec6: f443 7380 orr.w r3, r3, #256 ; 0x100
8001eca: 6013 str r3, [r2, #0]
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
8001ecc: 2003 movs r0, #3
8001ece: f000 fd17 bl 8002900 <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
8001ed2: 2000 movs r0, #0
8001ed4: f000 f808 bl 8001ee8 <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
8001ed8: f7ff fe14 bl 8001b04 <HAL_MspInit>
/* Return function status */
return HAL_OK;
8001edc: 2300 movs r3, #0
}
8001ede: 4618 mov r0, r3
8001ee0: bd80 pop {r7, pc}
8001ee2: bf00 nop
8001ee4: 40023c00 .word 0x40023c00
08001ee8 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8001ee8: b580 push {r7, lr}
8001eea: b082 sub sp, #8
8001eec: af00 add r7, sp, #0
8001eee: 6078 str r0, [r7, #4]
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
8001ef0: 4b12 ldr r3, [pc, #72] ; (8001f3c <HAL_InitTick+0x54>)
8001ef2: 681a ldr r2, [r3, #0]
8001ef4: 4b12 ldr r3, [pc, #72] ; (8001f40 <HAL_InitTick+0x58>)
8001ef6: 781b ldrb r3, [r3, #0]
8001ef8: 4619 mov r1, r3
8001efa: f44f 737a mov.w r3, #1000 ; 0x3e8
8001efe: fbb3 f3f1 udiv r3, r3, r1
8001f02: fbb2 f3f3 udiv r3, r2, r3
8001f06: 4618 mov r0, r3
8001f08: f000 fd2f bl 800296a <HAL_SYSTICK_Config>
8001f0c: 4603 mov r3, r0
8001f0e: 2b00 cmp r3, #0
8001f10: d001 beq.n 8001f16 <HAL_InitTick+0x2e>
{
return HAL_ERROR;
8001f12: 2301 movs r3, #1
8001f14: e00e b.n 8001f34 <HAL_InitTick+0x4c>
}
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8001f16: 687b ldr r3, [r7, #4]
8001f18: 2b0f cmp r3, #15
8001f1a: d80a bhi.n 8001f32 <HAL_InitTick+0x4a>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
8001f1c: 2200 movs r2, #0
8001f1e: 6879 ldr r1, [r7, #4]
8001f20: f04f 30ff mov.w r0, #4294967295
8001f24: f000 fcf7 bl 8002916 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8001f28: 4a06 ldr r2, [pc, #24] ; (8001f44 <HAL_InitTick+0x5c>)
8001f2a: 687b ldr r3, [r7, #4]
8001f2c: 6013 str r3, [r2, #0]
{
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
8001f2e: 2300 movs r3, #0
8001f30: e000 b.n 8001f34 <HAL_InitTick+0x4c>
return HAL_ERROR;
8001f32: 2301 movs r3, #1
}
8001f34: 4618 mov r0, r3
8001f36: 3708 adds r7, #8
8001f38: 46bd mov sp, r7
8001f3a: bd80 pop {r7, pc}
8001f3c: 20000004 .word 0x20000004
8001f40: 2000000c .word 0x2000000c
8001f44: 20000008 .word 0x20000008
08001f48 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8001f48: b480 push {r7}
8001f4a: af00 add r7, sp, #0
uwTick += uwTickFreq;
8001f4c: 4b06 ldr r3, [pc, #24] ; (8001f68 <HAL_IncTick+0x20>)
8001f4e: 781b ldrb r3, [r3, #0]
8001f50: 461a mov r2, r3
8001f52: 4b06 ldr r3, [pc, #24] ; (8001f6c <HAL_IncTick+0x24>)
8001f54: 681b ldr r3, [r3, #0]
8001f56: 4413 add r3, r2
8001f58: 4a04 ldr r2, [pc, #16] ; (8001f6c <HAL_IncTick+0x24>)
8001f5a: 6013 str r3, [r2, #0]
}
8001f5c: bf00 nop
8001f5e: 46bd mov sp, r7
8001f60: f85d 7b04 ldr.w r7, [sp], #4
8001f64: 4770 bx lr
8001f66: bf00 nop
8001f68: 2000000c .word 0x2000000c
8001f6c: 2000049c .word 0x2000049c
08001f70 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8001f70: b480 push {r7}
8001f72: af00 add r7, sp, #0
return uwTick;
8001f74: 4b03 ldr r3, [pc, #12] ; (8001f84 <HAL_GetTick+0x14>)
8001f76: 681b ldr r3, [r3, #0]
}
8001f78: 4618 mov r0, r3
8001f7a: 46bd mov sp, r7
8001f7c: f85d 7b04 ldr.w r7, [sp], #4
8001f80: 4770 bx lr
8001f82: bf00 nop
8001f84: 2000049c .word 0x2000049c
08001f88 <HAL_Delay>:
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
8001f88: b580 push {r7, lr}
8001f8a: b084 sub sp, #16
8001f8c: af00 add r7, sp, #0
8001f8e: 6078 str r0, [r7, #4]
uint32_t tickstart = HAL_GetTick();
8001f90: f7ff ffee bl 8001f70 <HAL_GetTick>
8001f94: 60b8 str r0, [r7, #8]
uint32_t wait = Delay;
8001f96: 687b ldr r3, [r7, #4]
8001f98: 60fb str r3, [r7, #12]
/* Add a freq to guarantee minimum wait */
if (wait < HAL_MAX_DELAY)
8001f9a: 68fb ldr r3, [r7, #12]
8001f9c: f1b3 3fff cmp.w r3, #4294967295
8001fa0: d005 beq.n 8001fae <HAL_Delay+0x26>
{
wait += (uint32_t)(uwTickFreq);
8001fa2: 4b09 ldr r3, [pc, #36] ; (8001fc8 <HAL_Delay+0x40>)
8001fa4: 781b ldrb r3, [r3, #0]
8001fa6: 461a mov r2, r3
8001fa8: 68fb ldr r3, [r7, #12]
8001faa: 4413 add r3, r2
8001fac: 60fb str r3, [r7, #12]
}
while((HAL_GetTick() - tickstart) < wait)
8001fae: bf00 nop
8001fb0: f7ff ffde bl 8001f70 <HAL_GetTick>
8001fb4: 4602 mov r2, r0
8001fb6: 68bb ldr r3, [r7, #8]
8001fb8: 1ad3 subs r3, r2, r3
8001fba: 68fa ldr r2, [r7, #12]
8001fbc: 429a cmp r2, r3
8001fbe: d8f7 bhi.n 8001fb0 <HAL_Delay+0x28>
{
}
}
8001fc0: bf00 nop
8001fc2: 3710 adds r7, #16
8001fc4: 46bd mov sp, r7
8001fc6: bd80 pop {r7, pc}
8001fc8: 2000000c .word 0x2000000c
08001fcc <HAL_ADC_Init>:
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
{
8001fcc: b580 push {r7, lr}
8001fce: b084 sub sp, #16
8001fd0: af00 add r7, sp, #0
8001fd2: 6078 str r0, [r7, #4]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8001fd4: 2300 movs r3, #0
8001fd6: 73fb strb r3, [r7, #15]
/* Check ADC handle */
if(hadc == NULL)
8001fd8: 687b ldr r3, [r7, #4]
8001fda: 2b00 cmp r3, #0
8001fdc: d101 bne.n 8001fe2 <HAL_ADC_Init+0x16>
{
return HAL_ERROR;
8001fde: 2301 movs r3, #1
8001fe0: e033 b.n 800204a <HAL_ADC_Init+0x7e>
if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
{
assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
}
if(hadc->State == HAL_ADC_STATE_RESET)
8001fe2: 687b ldr r3, [r7, #4]
8001fe4: 6c1b ldr r3, [r3, #64] ; 0x40
8001fe6: 2b00 cmp r3, #0
8001fe8: d109 bne.n 8001ffe <HAL_ADC_Init+0x32>
/* Init the low level hardware */
hadc->MspInitCallback(hadc);
#else
/* Init the low level hardware */
HAL_ADC_MspInit(hadc);
8001fea: 6878 ldr r0, [r7, #4]
8001fec: f7ff fdb2 bl 8001b54 <HAL_ADC_MspInit>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Initialize ADC error code */
ADC_CLEAR_ERRORCODE(hadc);
8001ff0: 687b ldr r3, [r7, #4]
8001ff2: 2200 movs r2, #0
8001ff4: 645a str r2, [r3, #68] ; 0x44
/* Allocate lock resource and initialize it */
hadc->Lock = HAL_UNLOCKED;
8001ff6: 687b ldr r3, [r7, #4]
8001ff8: 2200 movs r2, #0
8001ffa: f883 203c strb.w r2, [r3, #60] ; 0x3c
}
/* Configuration of ADC parameters if previous preliminary actions are */
/* correctly completed. */
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
8001ffe: 687b ldr r3, [r7, #4]
8002000: 6c1b ldr r3, [r3, #64] ; 0x40
8002002: f003 0310 and.w r3, r3, #16
8002006: 2b00 cmp r3, #0
8002008: d118 bne.n 800203c <HAL_ADC_Init+0x70>
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
800200a: 687b ldr r3, [r7, #4]
800200c: 6c1b ldr r3, [r3, #64] ; 0x40
800200e: f423 5388 bic.w r3, r3, #4352 ; 0x1100
8002012: f023 0302 bic.w r3, r3, #2
8002016: f043 0202 orr.w r2, r3, #2
800201a: 687b ldr r3, [r7, #4]
800201c: 641a str r2, [r3, #64] ; 0x40
HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
HAL_ADC_STATE_BUSY_INTERNAL);
/* Set ADC parameters */
ADC_Init(hadc);
800201e: 6878 ldr r0, [r7, #4]
8002020: f000 faa2 bl 8002568 <ADC_Init>
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
8002024: 687b ldr r3, [r7, #4]
8002026: 2200 movs r2, #0
8002028: 645a str r2, [r3, #68] ; 0x44
/* Set the ADC state */
ADC_STATE_CLR_SET(hadc->State,
800202a: 687b ldr r3, [r7, #4]
800202c: 6c1b ldr r3, [r3, #64] ; 0x40
800202e: f023 0303 bic.w r3, r3, #3
8002032: f043 0201 orr.w r2, r3, #1
8002036: 687b ldr r3, [r7, #4]
8002038: 641a str r2, [r3, #64] ; 0x40
800203a: e001 b.n 8002040 <HAL_ADC_Init+0x74>
HAL_ADC_STATE_BUSY_INTERNAL,
HAL_ADC_STATE_READY);
}
else
{
tmp_hal_status = HAL_ERROR;
800203c: 2301 movs r3, #1
800203e: 73fb strb r3, [r7, #15]
}
/* Release Lock */
__HAL_UNLOCK(hadc);
8002040: 687b ldr r3, [r7, #4]
8002042: 2200 movs r2, #0
8002044: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Return function status */
return tmp_hal_status;
8002048: 7bfb ldrb r3, [r7, #15]
}
800204a: 4618 mov r0, r3
800204c: 3710 adds r7, #16
800204e: 46bd mov sp, r7
8002050: bd80 pop {r7, pc}
...
08002054 <HAL_ADC_Start>:
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
{
8002054: b480 push {r7}
8002056: b085 sub sp, #20
8002058: af00 add r7, sp, #0
800205a: 6078 str r0, [r7, #4]
__IO uint32_t counter = 0U;
800205c: 2300 movs r3, #0
800205e: 60bb str r3, [r7, #8]
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
/* Process locked */
__HAL_LOCK(hadc);
8002060: 687b ldr r3, [r7, #4]
8002062: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
8002066: 2b01 cmp r3, #1
8002068: d101 bne.n 800206e <HAL_ADC_Start+0x1a>
800206a: 2302 movs r3, #2
800206c: e0a5 b.n 80021ba <HAL_ADC_Start+0x166>
800206e: 687b ldr r3, [r7, #4]
8002070: 2201 movs r2, #1
8002072: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Enable the ADC peripheral */
/* Check if ADC peripheral is disabled in order to enable it and wait during
Tstab time the ADC's stabilization */
if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
8002076: 687b ldr r3, [r7, #4]
8002078: 681b ldr r3, [r3, #0]
800207a: 689b ldr r3, [r3, #8]
800207c: f003 0301 and.w r3, r3, #1
8002080: 2b01 cmp r3, #1
8002082: d018 beq.n 80020b6 <HAL_ADC_Start+0x62>
{
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
8002084: 687b ldr r3, [r7, #4]
8002086: 681b ldr r3, [r3, #0]
8002088: 689a ldr r2, [r3, #8]
800208a: 687b ldr r3, [r7, #4]
800208c: 681b ldr r3, [r3, #0]
800208e: f042 0201 orr.w r2, r2, #1
8002092: 609a str r2, [r3, #8]
/* Delay for ADC stabilization time */
/* Compute number of CPU cycles to wait for */
counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
8002094: 4b4c ldr r3, [pc, #304] ; (80021c8 <HAL_ADC_Start+0x174>)
8002096: 681b ldr r3, [r3, #0]
8002098: 4a4c ldr r2, [pc, #304] ; (80021cc <HAL_ADC_Start+0x178>)
800209a: fba2 2303 umull r2, r3, r2, r3
800209e: 0c9a lsrs r2, r3, #18
80020a0: 4613 mov r3, r2
80020a2: 005b lsls r3, r3, #1
80020a4: 4413 add r3, r2
80020a6: 60bb str r3, [r7, #8]
while(counter != 0U)
80020a8: e002 b.n 80020b0 <HAL_ADC_Start+0x5c>
{
counter--;
80020aa: 68bb ldr r3, [r7, #8]
80020ac: 3b01 subs r3, #1
80020ae: 60bb str r3, [r7, #8]
while(counter != 0U)
80020b0: 68bb ldr r3, [r7, #8]
80020b2: 2b00 cmp r3, #0
80020b4: d1f9 bne.n 80020aa <HAL_ADC_Start+0x56>
}
}
/* Start conversion if ADC is effectively enabled */
if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
80020b6: 687b ldr r3, [r7, #4]
80020b8: 681b ldr r3, [r3, #0]
80020ba: 689b ldr r3, [r3, #8]
80020bc: f003 0301 and.w r3, r3, #1
80020c0: 2b01 cmp r3, #1
80020c2: d179 bne.n 80021b8 <HAL_ADC_Start+0x164>
{
/* Set ADC state */
/* - Clear state bitfield related to regular group conversion results */
/* - Set state bitfield related to regular group operation */
ADC_STATE_CLR_SET(hadc->State,
80020c4: 687b ldr r3, [r7, #4]
80020c6: 6c1b ldr r3, [r3, #64] ; 0x40
80020c8: f423 63e0 bic.w r3, r3, #1792 ; 0x700
80020cc: f023 0301 bic.w r3, r3, #1
80020d0: f443 7280 orr.w r2, r3, #256 ; 0x100
80020d4: 687b ldr r3, [r7, #4]
80020d6: 641a str r2, [r3, #64] ; 0x40
HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
HAL_ADC_STATE_REG_BUSY);
/* If conversions on group regular are also triggering group injected, */
/* update ADC state. */
if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
80020d8: 687b ldr r3, [r7, #4]
80020da: 681b ldr r3, [r3, #0]
80020dc: 685b ldr r3, [r3, #4]
80020de: f403 6380 and.w r3, r3, #1024 ; 0x400
80020e2: 2b00 cmp r3, #0
80020e4: d007 beq.n 80020f6 <HAL_ADC_Start+0xa2>
{
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
80020e6: 687b ldr r3, [r7, #4]
80020e8: 6c1b ldr r3, [r3, #64] ; 0x40
80020ea: f423 5340 bic.w r3, r3, #12288 ; 0x3000
80020ee: f443 5280 orr.w r2, r3, #4096 ; 0x1000
80020f2: 687b ldr r3, [r7, #4]
80020f4: 641a str r2, [r3, #64] ; 0x40
}
/* State machine update: Check if an injected conversion is ongoing */
if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
80020f6: 687b ldr r3, [r7, #4]
80020f8: 6c1b ldr r3, [r3, #64] ; 0x40
80020fa: f403 5380 and.w r3, r3, #4096 ; 0x1000
80020fe: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
8002102: d106 bne.n 8002112 <HAL_ADC_Start+0xbe>
{
/* Reset ADC error code fields related to conversions on group regular */
CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
8002104: 687b ldr r3, [r7, #4]
8002106: 6c5b ldr r3, [r3, #68] ; 0x44
8002108: f023 0206 bic.w r2, r3, #6
800210c: 687b ldr r3, [r7, #4]
800210e: 645a str r2, [r3, #68] ; 0x44
8002110: e002 b.n 8002118 <HAL_ADC_Start+0xc4>
}
else
{
/* Reset ADC all error code fields */
ADC_CLEAR_ERRORCODE(hadc);
8002112: 687b ldr r3, [r7, #4]
8002114: 2200 movs r2, #0
8002116: 645a str r2, [r3, #68] ; 0x44
}
/* Process unlocked */
/* Unlock before starting ADC conversions: in case of potential */
/* interruption, to let the process to ADC IRQ Handler. */
__HAL_UNLOCK(hadc);
8002118: 687b ldr r3, [r7, #4]
800211a: 2200 movs r2, #0
800211c: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Pointer to the common control register to which is belonging hadc */
/* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */
/* control register) */
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
8002120: 4b2b ldr r3, [pc, #172] ; (80021d0 <HAL_ADC_Start+0x17c>)
8002122: 60fb str r3, [r7, #12]
/* Clear regular group conversion flag and overrun flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
8002124: 687b ldr r3, [r7, #4]
8002126: 681b ldr r3, [r3, #0]
8002128: f06f 0222 mvn.w r2, #34 ; 0x22
800212c: 601a str r2, [r3, #0]
/* Check if Multimode enabled */
if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI))
800212e: 68fb ldr r3, [r7, #12]
8002130: 685b ldr r3, [r3, #4]
8002132: f003 031f and.w r3, r3, #31
8002136: 2b00 cmp r3, #0
8002138: d12a bne.n 8002190 <HAL_ADC_Start+0x13c>
{
#if defined(ADC2) && defined(ADC3)
if((hadc->Instance == ADC1) || ((hadc->Instance == ADC2) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_0)) \
800213a: 687b ldr r3, [r7, #4]
800213c: 681b ldr r3, [r3, #0]
800213e: 4a25 ldr r2, [pc, #148] ; (80021d4 <HAL_ADC_Start+0x180>)
8002140: 4293 cmp r3, r2
8002142: d015 beq.n 8002170 <HAL_ADC_Start+0x11c>
8002144: 687b ldr r3, [r7, #4]
8002146: 681b ldr r3, [r3, #0]
8002148: 4a23 ldr r2, [pc, #140] ; (80021d8 <HAL_ADC_Start+0x184>)
800214a: 4293 cmp r3, r2
800214c: d105 bne.n 800215a <HAL_ADC_Start+0x106>
800214e: 4b20 ldr r3, [pc, #128] ; (80021d0 <HAL_ADC_Start+0x17c>)
8002150: 685b ldr r3, [r3, #4]
8002152: f003 031f and.w r3, r3, #31
8002156: 2b00 cmp r3, #0
8002158: d00a beq.n 8002170 <HAL_ADC_Start+0x11c>
|| ((hadc->Instance == ADC3) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_4)))
800215a: 687b ldr r3, [r7, #4]
800215c: 681b ldr r3, [r3, #0]
800215e: 4a1f ldr r2, [pc, #124] ; (80021dc <HAL_ADC_Start+0x188>)
8002160: 4293 cmp r3, r2
8002162: d129 bne.n 80021b8 <HAL_ADC_Start+0x164>
8002164: 4b1a ldr r3, [pc, #104] ; (80021d0 <HAL_ADC_Start+0x17c>)
8002166: 685b ldr r3, [r3, #4]
8002168: f003 031f and.w r3, r3, #31
800216c: 2b0f cmp r3, #15
800216e: d823 bhi.n 80021b8 <HAL_ADC_Start+0x164>
{
#endif /* ADC2 || ADC3 */
/* if no external trigger present enable software conversion of regular channels */
if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
8002170: 687b ldr r3, [r7, #4]
8002172: 681b ldr r3, [r3, #0]
8002174: 689b ldr r3, [r3, #8]
8002176: f003 5340 and.w r3, r3, #805306368 ; 0x30000000
800217a: 2b00 cmp r3, #0
800217c: d11c bne.n 80021b8 <HAL_ADC_Start+0x164>
{
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
800217e: 687b ldr r3, [r7, #4]
8002180: 681b ldr r3, [r3, #0]
8002182: 689a ldr r2, [r3, #8]
8002184: 687b ldr r3, [r7, #4]
8002186: 681b ldr r3, [r3, #0]
8002188: f042 4280 orr.w r2, r2, #1073741824 ; 0x40000000
800218c: 609a str r2, [r3, #8]
800218e: e013 b.n 80021b8 <HAL_ADC_Start+0x164>
#endif /* ADC2 || ADC3 */
}
else
{
/* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
8002190: 687b ldr r3, [r7, #4]
8002192: 681b ldr r3, [r3, #0]
8002194: 4a0f ldr r2, [pc, #60] ; (80021d4 <HAL_ADC_Start+0x180>)
8002196: 4293 cmp r3, r2
8002198: d10e bne.n 80021b8 <HAL_ADC_Start+0x164>
800219a: 687b ldr r3, [r7, #4]
800219c: 681b ldr r3, [r3, #0]
800219e: 689b ldr r3, [r3, #8]
80021a0: f003 5340 and.w r3, r3, #805306368 ; 0x30000000
80021a4: 2b00 cmp r3, #0
80021a6: d107 bne.n 80021b8 <HAL_ADC_Start+0x164>
{
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
80021a8: 687b ldr r3, [r7, #4]
80021aa: 681b ldr r3, [r3, #0]
80021ac: 689a ldr r2, [r3, #8]
80021ae: 687b ldr r3, [r7, #4]
80021b0: 681b ldr r3, [r3, #0]
80021b2: f042 4280 orr.w r2, r2, #1073741824 ; 0x40000000
80021b6: 609a str r2, [r3, #8]
}
}
}
/* Return function status */
return HAL_OK;
80021b8: 2300 movs r3, #0
}
80021ba: 4618 mov r0, r3
80021bc: 3714 adds r7, #20
80021be: 46bd mov sp, r7
80021c0: f85d 7b04 ldr.w r7, [sp], #4
80021c4: 4770 bx lr
80021c6: bf00 nop
80021c8: 20000004 .word 0x20000004
80021cc: 431bde83 .word 0x431bde83
80021d0: 40012300 .word 0x40012300
80021d4: 40012000 .word 0x40012000
80021d8: 40012100 .word 0x40012100
80021dc: 40012200 .word 0x40012200
080021e0 <HAL_ADC_PollForConversion>:
* the configuration information for the specified ADC.
* @param Timeout Timeout value in millisecond.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
{
80021e0: b580 push {r7, lr}
80021e2: b084 sub sp, #16
80021e4: af00 add r7, sp, #0
80021e6: 6078 str r0, [r7, #4]
80021e8: 6039 str r1, [r7, #0]
uint32_t tickstart = 0U;
80021ea: 2300 movs r3, #0
80021ec: 60fb str r3, [r7, #12]
/* each conversion: */
/* Particular case is ADC configured in DMA mode and ADC sequencer with */
/* several ranks and polling for end of each conversion. */
/* For code simplicity sake, this particular case is generalized to */
/* ADC configured in DMA mode and polling for end of each conversion. */
if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) &&
80021ee: 687b ldr r3, [r7, #4]
80021f0: 681b ldr r3, [r3, #0]
80021f2: 689b ldr r3, [r3, #8]
80021f4: f403 6380 and.w r3, r3, #1024 ; 0x400
80021f8: f5b3 6f80 cmp.w r3, #1024 ; 0x400
80021fc: d113 bne.n 8002226 <HAL_ADC_PollForConversion+0x46>
HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA) )
80021fe: 687b ldr r3, [r7, #4]
8002200: 681b ldr r3, [r3, #0]
8002202: 689b ldr r3, [r3, #8]
8002204: f403 7380 and.w r3, r3, #256 ; 0x100
if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) &&
8002208: f5b3 7f80 cmp.w r3, #256 ; 0x100
800220c: d10b bne.n 8002226 <HAL_ADC_PollForConversion+0x46>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
800220e: 687b ldr r3, [r7, #4]
8002210: 6c1b ldr r3, [r3, #64] ; 0x40
8002212: f043 0220 orr.w r2, r3, #32
8002216: 687b ldr r3, [r7, #4]
8002218: 641a str r2, [r3, #64] ; 0x40
/* Process unlocked */
__HAL_UNLOCK(hadc);
800221a: 687b ldr r3, [r7, #4]
800221c: 2200 movs r2, #0
800221e: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_ERROR;
8002222: 2301 movs r3, #1
8002224: e05c b.n 80022e0 <HAL_ADC_PollForConversion+0x100>
}
/* Get tick */
tickstart = HAL_GetTick();
8002226: f7ff fea3 bl 8001f70 <HAL_GetTick>
800222a: 60f8 str r0, [r7, #12]
/* Check End of conversion flag */
while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))
800222c: e01a b.n 8002264 <HAL_ADC_PollForConversion+0x84>
{
/* Check if timeout is disabled (set to infinite wait) */
if(Timeout != HAL_MAX_DELAY)
800222e: 683b ldr r3, [r7, #0]
8002230: f1b3 3fff cmp.w r3, #4294967295
8002234: d016 beq.n 8002264 <HAL_ADC_PollForConversion+0x84>
{
if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))
8002236: 683b ldr r3, [r7, #0]
8002238: 2b00 cmp r3, #0
800223a: d007 beq.n 800224c <HAL_ADC_PollForConversion+0x6c>
800223c: f7ff fe98 bl 8001f70 <HAL_GetTick>
8002240: 4602 mov r2, r0
8002242: 68fb ldr r3, [r7, #12]
8002244: 1ad3 subs r3, r2, r3
8002246: 683a ldr r2, [r7, #0]
8002248: 429a cmp r2, r3
800224a: d20b bcs.n 8002264 <HAL_ADC_PollForConversion+0x84>
{
/* Update ADC state machine to timeout */
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
800224c: 687b ldr r3, [r7, #4]
800224e: 6c1b ldr r3, [r3, #64] ; 0x40
8002250: f043 0204 orr.w r2, r3, #4
8002254: 687b ldr r3, [r7, #4]
8002256: 641a str r2, [r3, #64] ; 0x40
/* Process unlocked */
__HAL_UNLOCK(hadc);
8002258: 687b ldr r3, [r7, #4]
800225a: 2200 movs r2, #0
800225c: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_TIMEOUT;
8002260: 2303 movs r3, #3
8002262: e03d b.n 80022e0 <HAL_ADC_PollForConversion+0x100>
while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))
8002264: 687b ldr r3, [r7, #4]
8002266: 681b ldr r3, [r3, #0]
8002268: 681b ldr r3, [r3, #0]
800226a: f003 0302 and.w r3, r3, #2
800226e: 2b02 cmp r3, #2
8002270: d1dd bne.n 800222e <HAL_ADC_PollForConversion+0x4e>
}
}
}
/* Clear regular group conversion flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
8002272: 687b ldr r3, [r7, #4]
8002274: 681b ldr r3, [r3, #0]
8002276: f06f 0212 mvn.w r2, #18
800227a: 601a str r2, [r3, #0]
/* Update ADC state machine */
SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
800227c: 687b ldr r3, [r7, #4]
800227e: 6c1b ldr r3, [r3, #64] ; 0x40
8002280: f443 7200 orr.w r2, r3, #512 ; 0x200
8002284: 687b ldr r3, [r7, #4]
8002286: 641a str r2, [r3, #64] ; 0x40
/* by external trigger, continuous mode or scan sequence on going. */
/* Note: On STM32F4, there is no independent flag of end of sequence. */
/* The test of scan sequence on going is done either with scan */
/* sequence disabled or with end of conversion flag set to */
/* of end of sequence. */
if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
8002288: 687b ldr r3, [r7, #4]
800228a: 681b ldr r3, [r3, #0]
800228c: 689b ldr r3, [r3, #8]
800228e: f003 5340 and.w r3, r3, #805306368 ; 0x30000000
8002292: 2b00 cmp r3, #0
8002294: d123 bne.n 80022de <HAL_ADC_PollForConversion+0xfe>
(hadc->Init.ContinuousConvMode == DISABLE) &&
8002296: 687b ldr r3, [r7, #4]
8002298: 7e1b ldrb r3, [r3, #24]
if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
800229a: 2b00 cmp r3, #0
800229c: d11f bne.n 80022de <HAL_ADC_PollForConversion+0xfe>
(HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
800229e: 687b ldr r3, [r7, #4]
80022a0: 681b ldr r3, [r3, #0]
80022a2: 6adb ldr r3, [r3, #44] ; 0x2c
80022a4: f403 0370 and.w r3, r3, #15728640 ; 0xf00000
(hadc->Init.ContinuousConvMode == DISABLE) &&
80022a8: 2b00 cmp r3, #0
80022aa: d006 beq.n 80022ba <HAL_ADC_PollForConversion+0xda>
HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
80022ac: 687b ldr r3, [r7, #4]
80022ae: 681b ldr r3, [r3, #0]
80022b0: 689b ldr r3, [r3, #8]
80022b2: f403 6380 and.w r3, r3, #1024 ; 0x400
(HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
80022b6: 2b00 cmp r3, #0
80022b8: d111 bne.n 80022de <HAL_ADC_PollForConversion+0xfe>
{
/* Set ADC state */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
80022ba: 687b ldr r3, [r7, #4]
80022bc: 6c1b ldr r3, [r3, #64] ; 0x40
80022be: f423 7280 bic.w r2, r3, #256 ; 0x100
80022c2: 687b ldr r3, [r7, #4]
80022c4: 641a str r2, [r3, #64] ; 0x40
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
80022c6: 687b ldr r3, [r7, #4]
80022c8: 6c1b ldr r3, [r3, #64] ; 0x40
80022ca: f403 5380 and.w r3, r3, #4096 ; 0x1000
80022ce: 2b00 cmp r3, #0
80022d0: d105 bne.n 80022de <HAL_ADC_PollForConversion+0xfe>
{
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
80022d2: 687b ldr r3, [r7, #4]
80022d4: 6c1b ldr r3, [r3, #64] ; 0x40
80022d6: f043 0201 orr.w r2, r3, #1
80022da: 687b ldr r3, [r7, #4]
80022dc: 641a str r2, [r3, #64] ; 0x40
}
}
/* Return ADC state */
return HAL_OK;
80022de: 2300 movs r3, #0
}
80022e0: 4618 mov r0, r3
80022e2: 3710 adds r7, #16
80022e4: 46bd mov sp, r7
80022e6: bd80 pop {r7, pc}
080022e8 <HAL_ADC_GetValue>:
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval Converted value
*/
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
{
80022e8: b480 push {r7}
80022ea: b083 sub sp, #12
80022ec: af00 add r7, sp, #0
80022ee: 6078 str r0, [r7, #4]
/* Return the selected ADC converted value */
return hadc->Instance->DR;
80022f0: 687b ldr r3, [r7, #4]
80022f2: 681b ldr r3, [r3, #0]
80022f4: 6cdb ldr r3, [r3, #76] ; 0x4c
}
80022f6: 4618 mov r0, r3
80022f8: 370c adds r7, #12
80022fa: 46bd mov sp, r7
80022fc: f85d 7b04 ldr.w r7, [sp], #4
8002300: 4770 bx lr
...
08002304 <HAL_ADC_ConfigChannel>:
* the configuration information for the specified ADC.
* @param sConfig ADC configuration structure.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
{
8002304: b480 push {r7}
8002306: b085 sub sp, #20
8002308: af00 add r7, sp, #0
800230a: 6078 str r0, [r7, #4]
800230c: 6039 str r1, [r7, #0]
__IO uint32_t counter = 0U;
800230e: 2300 movs r3, #0
8002310: 60bb str r3, [r7, #8]
assert_param(IS_ADC_CHANNEL(sConfig->Channel));
assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
/* Process locked */
__HAL_LOCK(hadc);
8002312: 687b ldr r3, [r7, #4]
8002314: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
8002318: 2b01 cmp r3, #1
800231a: d101 bne.n 8002320 <HAL_ADC_ConfigChannel+0x1c>
800231c: 2302 movs r3, #2
800231e: e113 b.n 8002548 <HAL_ADC_ConfigChannel+0x244>
8002320: 687b ldr r3, [r7, #4]
8002322: 2201 movs r2, #1
8002324: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* if ADC_Channel_10 ... ADC_Channel_18 is selected */
if (sConfig->Channel > ADC_CHANNEL_9)
8002328: 683b ldr r3, [r7, #0]
800232a: 681b ldr r3, [r3, #0]
800232c: 2b09 cmp r3, #9
800232e: d925 bls.n 800237c <HAL_ADC_ConfigChannel+0x78>
{
/* Clear the old sample time */
hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel);
8002330: 687b ldr r3, [r7, #4]
8002332: 681b ldr r3, [r3, #0]
8002334: 68d9 ldr r1, [r3, #12]
8002336: 683b ldr r3, [r7, #0]
8002338: 681b ldr r3, [r3, #0]
800233a: b29b uxth r3, r3
800233c: 461a mov r2, r3
800233e: 4613 mov r3, r2
8002340: 005b lsls r3, r3, #1
8002342: 4413 add r3, r2
8002344: 3b1e subs r3, #30
8002346: 2207 movs r2, #7
8002348: fa02 f303 lsl.w r3, r2, r3
800234c: 43da mvns r2, r3
800234e: 687b ldr r3, [r7, #4]
8002350: 681b ldr r3, [r3, #0]
8002352: 400a ands r2, r1
8002354: 60da str r2, [r3, #12]
/* Set the new sample time */
hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel);
8002356: 687b ldr r3, [r7, #4]
8002358: 681b ldr r3, [r3, #0]
800235a: 68d9 ldr r1, [r3, #12]
800235c: 683b ldr r3, [r7, #0]
800235e: 689a ldr r2, [r3, #8]
8002360: 683b ldr r3, [r7, #0]
8002362: 681b ldr r3, [r3, #0]
8002364: b29b uxth r3, r3
8002366: 4618 mov r0, r3
8002368: 4603 mov r3, r0
800236a: 005b lsls r3, r3, #1
800236c: 4403 add r3, r0
800236e: 3b1e subs r3, #30
8002370: 409a lsls r2, r3
8002372: 687b ldr r3, [r7, #4]
8002374: 681b ldr r3, [r3, #0]
8002376: 430a orrs r2, r1
8002378: 60da str r2, [r3, #12]
800237a: e022 b.n 80023c2 <HAL_ADC_ConfigChannel+0xbe>
}
else /* ADC_Channel include in ADC_Channel_[0..9] */
{
/* Clear the old sample time */
hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel);
800237c: 687b ldr r3, [r7, #4]
800237e: 681b ldr r3, [r3, #0]
8002380: 6919 ldr r1, [r3, #16]
8002382: 683b ldr r3, [r7, #0]
8002384: 681b ldr r3, [r3, #0]
8002386: b29b uxth r3, r3
8002388: 461a mov r2, r3
800238a: 4613 mov r3, r2
800238c: 005b lsls r3, r3, #1
800238e: 4413 add r3, r2
8002390: 2207 movs r2, #7
8002392: fa02 f303 lsl.w r3, r2, r3
8002396: 43da mvns r2, r3
8002398: 687b ldr r3, [r7, #4]
800239a: 681b ldr r3, [r3, #0]
800239c: 400a ands r2, r1
800239e: 611a str r2, [r3, #16]
/* Set the new sample time */
hadc->Instance->SMPR2 |= ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel);
80023a0: 687b ldr r3, [r7, #4]
80023a2: 681b ldr r3, [r3, #0]
80023a4: 6919 ldr r1, [r3, #16]
80023a6: 683b ldr r3, [r7, #0]
80023a8: 689a ldr r2, [r3, #8]
80023aa: 683b ldr r3, [r7, #0]
80023ac: 681b ldr r3, [r3, #0]
80023ae: b29b uxth r3, r3
80023b0: 4618 mov r0, r3
80023b2: 4603 mov r3, r0
80023b4: 005b lsls r3, r3, #1
80023b6: 4403 add r3, r0
80023b8: 409a lsls r2, r3
80023ba: 687b ldr r3, [r7, #4]
80023bc: 681b ldr r3, [r3, #0]
80023be: 430a orrs r2, r1
80023c0: 611a str r2, [r3, #16]
}
/* For Rank 1 to 6 */
if (sConfig->Rank < 7U)
80023c2: 683b ldr r3, [r7, #0]
80023c4: 685b ldr r3, [r3, #4]
80023c6: 2b06 cmp r3, #6
80023c8: d824 bhi.n 8002414 <HAL_ADC_ConfigChannel+0x110>
{
/* Clear the old SQx bits for the selected rank */
hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank);
80023ca: 687b ldr r3, [r7, #4]
80023cc: 681b ldr r3, [r3, #0]
80023ce: 6b59 ldr r1, [r3, #52] ; 0x34
80023d0: 683b ldr r3, [r7, #0]
80023d2: 685a ldr r2, [r3, #4]
80023d4: 4613 mov r3, r2
80023d6: 009b lsls r3, r3, #2
80023d8: 4413 add r3, r2
80023da: 3b05 subs r3, #5
80023dc: 221f movs r2, #31
80023de: fa02 f303 lsl.w r3, r2, r3
80023e2: 43da mvns r2, r3
80023e4: 687b ldr r3, [r7, #4]
80023e6: 681b ldr r3, [r3, #0]
80023e8: 400a ands r2, r1
80023ea: 635a str r2, [r3, #52] ; 0x34
/* Set the SQx bits for the selected rank */
hadc->Instance->SQR3 |= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank);
80023ec: 687b ldr r3, [r7, #4]
80023ee: 681b ldr r3, [r3, #0]
80023f0: 6b59 ldr r1, [r3, #52] ; 0x34
80023f2: 683b ldr r3, [r7, #0]
80023f4: 681b ldr r3, [r3, #0]
80023f6: b29b uxth r3, r3
80023f8: 4618 mov r0, r3
80023fa: 683b ldr r3, [r7, #0]
80023fc: 685a ldr r2, [r3, #4]
80023fe: 4613 mov r3, r2
8002400: 009b lsls r3, r3, #2
8002402: 4413 add r3, r2
8002404: 3b05 subs r3, #5
8002406: fa00 f203 lsl.w r2, r0, r3
800240a: 687b ldr r3, [r7, #4]
800240c: 681b ldr r3, [r3, #0]
800240e: 430a orrs r2, r1
8002410: 635a str r2, [r3, #52] ; 0x34
8002412: e04c b.n 80024ae <HAL_ADC_ConfigChannel+0x1aa>
}
/* For Rank 7 to 12 */
else if (sConfig->Rank < 13U)
8002414: 683b ldr r3, [r7, #0]
8002416: 685b ldr r3, [r3, #4]
8002418: 2b0c cmp r3, #12
800241a: d824 bhi.n 8002466 <HAL_ADC_ConfigChannel+0x162>
{
/* Clear the old SQx bits for the selected rank */
hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank);
800241c: 687b ldr r3, [r7, #4]
800241e: 681b ldr r3, [r3, #0]
8002420: 6b19 ldr r1, [r3, #48] ; 0x30
8002422: 683b ldr r3, [r7, #0]
8002424: 685a ldr r2, [r3, #4]
8002426: 4613 mov r3, r2
8002428: 009b lsls r3, r3, #2
800242a: 4413 add r3, r2
800242c: 3b23 subs r3, #35 ; 0x23
800242e: 221f movs r2, #31
8002430: fa02 f303 lsl.w r3, r2, r3
8002434: 43da mvns r2, r3
8002436: 687b ldr r3, [r7, #4]
8002438: 681b ldr r3, [r3, #0]
800243a: 400a ands r2, r1
800243c: 631a str r2, [r3, #48] ; 0x30
/* Set the SQx bits for the selected rank */
hadc->Instance->SQR2 |= ADC_SQR2_RK(sConfig->Channel, sConfig->Rank);
800243e: 687b ldr r3, [r7, #4]
8002440: 681b ldr r3, [r3, #0]
8002442: 6b19 ldr r1, [r3, #48] ; 0x30
8002444: 683b ldr r3, [r7, #0]
8002446: 681b ldr r3, [r3, #0]
8002448: b29b uxth r3, r3
800244a: 4618 mov r0, r3
800244c: 683b ldr r3, [r7, #0]
800244e: 685a ldr r2, [r3, #4]
8002450: 4613 mov r3, r2
8002452: 009b lsls r3, r3, #2
8002454: 4413 add r3, r2
8002456: 3b23 subs r3, #35 ; 0x23
8002458: fa00 f203 lsl.w r2, r0, r3
800245c: 687b ldr r3, [r7, #4]
800245e: 681b ldr r3, [r3, #0]
8002460: 430a orrs r2, r1
8002462: 631a str r2, [r3, #48] ; 0x30
8002464: e023 b.n 80024ae <HAL_ADC_ConfigChannel+0x1aa>
}
/* For Rank 13 to 16 */
else
{
/* Clear the old SQx bits for the selected rank */
hadc->Instance->SQR1 &= ~ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank);
8002466: 687b ldr r3, [r7, #4]
8002468: 681b ldr r3, [r3, #0]
800246a: 6ad9 ldr r1, [r3, #44] ; 0x2c
800246c: 683b ldr r3, [r7, #0]
800246e: 685a ldr r2, [r3, #4]
8002470: 4613 mov r3, r2
8002472: 009b lsls r3, r3, #2
8002474: 4413 add r3, r2
8002476: 3b41 subs r3, #65 ; 0x41
8002478: 221f movs r2, #31
800247a: fa02 f303 lsl.w r3, r2, r3
800247e: 43da mvns r2, r3
8002480: 687b ldr r3, [r7, #4]
8002482: 681b ldr r3, [r3, #0]
8002484: 400a ands r2, r1
8002486: 62da str r2, [r3, #44] ; 0x2c
/* Set the SQx bits for the selected rank */
hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank);
8002488: 687b ldr r3, [r7, #4]
800248a: 681b ldr r3, [r3, #0]
800248c: 6ad9 ldr r1, [r3, #44] ; 0x2c
800248e: 683b ldr r3, [r7, #0]
8002490: 681b ldr r3, [r3, #0]
8002492: b29b uxth r3, r3
8002494: 4618 mov r0, r3
8002496: 683b ldr r3, [r7, #0]
8002498: 685a ldr r2, [r3, #4]
800249a: 4613 mov r3, r2
800249c: 009b lsls r3, r3, #2
800249e: 4413 add r3, r2
80024a0: 3b41 subs r3, #65 ; 0x41
80024a2: fa00 f203 lsl.w r2, r0, r3
80024a6: 687b ldr r3, [r7, #4]
80024a8: 681b ldr r3, [r3, #0]
80024aa: 430a orrs r2, r1
80024ac: 62da str r2, [r3, #44] ; 0x2c
}
/* Pointer to the common control register to which is belonging hadc */
/* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */
/* control register) */
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
80024ae: 4b29 ldr r3, [pc, #164] ; (8002554 <HAL_ADC_ConfigChannel+0x250>)
80024b0: 60fb str r3, [r7, #12]
/* if ADC1 Channel_18 is selected for VBAT Channel ennable VBATE */
if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT))
80024b2: 687b ldr r3, [r7, #4]
80024b4: 681b ldr r3, [r3, #0]
80024b6: 4a28 ldr r2, [pc, #160] ; (8002558 <HAL_ADC_ConfigChannel+0x254>)
80024b8: 4293 cmp r3, r2
80024ba: d10f bne.n 80024dc <HAL_ADC_ConfigChannel+0x1d8>
80024bc: 683b ldr r3, [r7, #0]
80024be: 681b ldr r3, [r3, #0]
80024c0: 2b12 cmp r3, #18
80024c2: d10b bne.n 80024dc <HAL_ADC_ConfigChannel+0x1d8>
{
/* Disable the TEMPSENSOR channel in case of using board with multiplixed ADC_CHANNEL_VBAT & ADC_CHANNEL_TEMPSENSOR*/
if ((uint16_t)ADC_CHANNEL_TEMPSENSOR == (uint16_t)ADC_CHANNEL_VBAT)
{
tmpADC_Common->CCR &= ~ADC_CCR_TSVREFE;
80024c4: 68fb ldr r3, [r7, #12]
80024c6: 685b ldr r3, [r3, #4]
80024c8: f423 0200 bic.w r2, r3, #8388608 ; 0x800000
80024cc: 68fb ldr r3, [r7, #12]
80024ce: 605a str r2, [r3, #4]
}
/* Enable the VBAT channel*/
tmpADC_Common->CCR |= ADC_CCR_VBATE;
80024d0: 68fb ldr r3, [r7, #12]
80024d2: 685b ldr r3, [r3, #4]
80024d4: f443 0280 orr.w r2, r3, #4194304 ; 0x400000
80024d8: 68fb ldr r3, [r7, #12]
80024da: 605a str r2, [r3, #4]
}
/* if ADC1 Channel_16 or Channel_18 is selected for Temperature sensor or
Channel_17 is selected for VREFINT enable TSVREFE */
if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT)))
80024dc: 687b ldr r3, [r7, #4]
80024de: 681b ldr r3, [r3, #0]
80024e0: 4a1d ldr r2, [pc, #116] ; (8002558 <HAL_ADC_ConfigChannel+0x254>)
80024e2: 4293 cmp r3, r2
80024e4: d12b bne.n 800253e <HAL_ADC_ConfigChannel+0x23a>
80024e6: 683b ldr r3, [r7, #0]
80024e8: 681b ldr r3, [r3, #0]
80024ea: 4a1c ldr r2, [pc, #112] ; (800255c <HAL_ADC_ConfigChannel+0x258>)
80024ec: 4293 cmp r3, r2
80024ee: d003 beq.n 80024f8 <HAL_ADC_ConfigChannel+0x1f4>
80024f0: 683b ldr r3, [r7, #0]
80024f2: 681b ldr r3, [r3, #0]
80024f4: 2b11 cmp r3, #17
80024f6: d122 bne.n 800253e <HAL_ADC_ConfigChannel+0x23a>
{
/* Disable the VBAT channel in case of using board with multiplixed ADC_CHANNEL_VBAT & ADC_CHANNEL_TEMPSENSOR*/
if ((uint16_t)ADC_CHANNEL_TEMPSENSOR == (uint16_t)ADC_CHANNEL_VBAT)
{
tmpADC_Common->CCR &= ~ADC_CCR_VBATE;
80024f8: 68fb ldr r3, [r7, #12]
80024fa: 685b ldr r3, [r3, #4]
80024fc: f423 0280 bic.w r2, r3, #4194304 ; 0x400000
8002500: 68fb ldr r3, [r7, #12]
8002502: 605a str r2, [r3, #4]
}
/* Enable the Temperature sensor and VREFINT channel*/
tmpADC_Common->CCR |= ADC_CCR_TSVREFE;
8002504: 68fb ldr r3, [r7, #12]
8002506: 685b ldr r3, [r3, #4]
8002508: f443 0200 orr.w r2, r3, #8388608 ; 0x800000
800250c: 68fb ldr r3, [r7, #12]
800250e: 605a str r2, [r3, #4]
if((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))
8002510: 683b ldr r3, [r7, #0]
8002512: 681b ldr r3, [r3, #0]
8002514: 4a11 ldr r2, [pc, #68] ; (800255c <HAL_ADC_ConfigChannel+0x258>)
8002516: 4293 cmp r3, r2
8002518: d111 bne.n 800253e <HAL_ADC_ConfigChannel+0x23a>
{
/* Delay for temperature sensor stabilization time */
/* Compute number of CPU cycles to wait for */
counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
800251a: 4b11 ldr r3, [pc, #68] ; (8002560 <HAL_ADC_ConfigChannel+0x25c>)
800251c: 681b ldr r3, [r3, #0]
800251e: 4a11 ldr r2, [pc, #68] ; (8002564 <HAL_ADC_ConfigChannel+0x260>)
8002520: fba2 2303 umull r2, r3, r2, r3
8002524: 0c9a lsrs r2, r3, #18
8002526: 4613 mov r3, r2
8002528: 009b lsls r3, r3, #2
800252a: 4413 add r3, r2
800252c: 005b lsls r3, r3, #1
800252e: 60bb str r3, [r7, #8]
while(counter != 0U)
8002530: e002 b.n 8002538 <HAL_ADC_ConfigChannel+0x234>
{
counter--;
8002532: 68bb ldr r3, [r7, #8]
8002534: 3b01 subs r3, #1
8002536: 60bb str r3, [r7, #8]
while(counter != 0U)
8002538: 68bb ldr r3, [r7, #8]
800253a: 2b00 cmp r3, #0
800253c: d1f9 bne.n 8002532 <HAL_ADC_ConfigChannel+0x22e>
}
}
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
800253e: 687b ldr r3, [r7, #4]
8002540: 2200 movs r2, #0
8002542: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Return function status */
return HAL_OK;
8002546: 2300 movs r3, #0
}
8002548: 4618 mov r0, r3
800254a: 3714 adds r7, #20
800254c: 46bd mov sp, r7
800254e: f85d 7b04 ldr.w r7, [sp], #4
8002552: 4770 bx lr
8002554: 40012300 .word 0x40012300
8002558: 40012000 .word 0x40012000
800255c: 10000012 .word 0x10000012
8002560: 20000004 .word 0x20000004
8002564: 431bde83 .word 0x431bde83
08002568 <ADC_Init>:
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval None
*/
static void ADC_Init(ADC_HandleTypeDef* hadc)
{
8002568: b480 push {r7}
800256a: b085 sub sp, #20
800256c: af00 add r7, sp, #0
800256e: 6078 str r0, [r7, #4]
/* Set ADC parameters */
/* Pointer to the common control register to which is belonging hadc */
/* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */
/* control register) */
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
8002570: 4b79 ldr r3, [pc, #484] ; (8002758 <ADC_Init+0x1f0>)
8002572: 60fb str r3, [r7, #12]
/* Set the ADC clock prescaler */
tmpADC_Common->CCR &= ~(ADC_CCR_ADCPRE);
8002574: 68fb ldr r3, [r7, #12]
8002576: 685b ldr r3, [r3, #4]
8002578: f423 3240 bic.w r2, r3, #196608 ; 0x30000
800257c: 68fb ldr r3, [r7, #12]
800257e: 605a str r2, [r3, #4]
tmpADC_Common->CCR |= hadc->Init.ClockPrescaler;
8002580: 68fb ldr r3, [r7, #12]
8002582: 685a ldr r2, [r3, #4]
8002584: 687b ldr r3, [r7, #4]
8002586: 685b ldr r3, [r3, #4]
8002588: 431a orrs r2, r3
800258a: 68fb ldr r3, [r7, #12]
800258c: 605a str r2, [r3, #4]
/* Set ADC scan mode */
hadc->Instance->CR1 &= ~(ADC_CR1_SCAN);
800258e: 687b ldr r3, [r7, #4]
8002590: 681b ldr r3, [r3, #0]
8002592: 685a ldr r2, [r3, #4]
8002594: 687b ldr r3, [r7, #4]
8002596: 681b ldr r3, [r3, #0]
8002598: f422 7280 bic.w r2, r2, #256 ; 0x100
800259c: 605a str r2, [r3, #4]
hadc->Instance->CR1 |= ADC_CR1_SCANCONV(hadc->Init.ScanConvMode);
800259e: 687b ldr r3, [r7, #4]
80025a0: 681b ldr r3, [r3, #0]
80025a2: 6859 ldr r1, [r3, #4]
80025a4: 687b ldr r3, [r7, #4]
80025a6: 691b ldr r3, [r3, #16]
80025a8: 021a lsls r2, r3, #8
80025aa: 687b ldr r3, [r7, #4]
80025ac: 681b ldr r3, [r3, #0]
80025ae: 430a orrs r2, r1
80025b0: 605a str r2, [r3, #4]
/* Set ADC resolution */
hadc->Instance->CR1 &= ~(ADC_CR1_RES);
80025b2: 687b ldr r3, [r7, #4]
80025b4: 681b ldr r3, [r3, #0]
80025b6: 685a ldr r2, [r3, #4]
80025b8: 687b ldr r3, [r7, #4]
80025ba: 681b ldr r3, [r3, #0]
80025bc: f022 7240 bic.w r2, r2, #50331648 ; 0x3000000
80025c0: 605a str r2, [r3, #4]
hadc->Instance->CR1 |= hadc->Init.Resolution;
80025c2: 687b ldr r3, [r7, #4]
80025c4: 681b ldr r3, [r3, #0]
80025c6: 6859 ldr r1, [r3, #4]
80025c8: 687b ldr r3, [r7, #4]
80025ca: 689a ldr r2, [r3, #8]
80025cc: 687b ldr r3, [r7, #4]
80025ce: 681b ldr r3, [r3, #0]
80025d0: 430a orrs r2, r1
80025d2: 605a str r2, [r3, #4]
/* Set ADC data alignment */
hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN);
80025d4: 687b ldr r3, [r7, #4]
80025d6: 681b ldr r3, [r3, #0]
80025d8: 689a ldr r2, [r3, #8]
80025da: 687b ldr r3, [r7, #4]
80025dc: 681b ldr r3, [r3, #0]
80025de: f422 6200 bic.w r2, r2, #2048 ; 0x800
80025e2: 609a str r2, [r3, #8]
hadc->Instance->CR2 |= hadc->Init.DataAlign;
80025e4: 687b ldr r3, [r7, #4]
80025e6: 681b ldr r3, [r3, #0]
80025e8: 6899 ldr r1, [r3, #8]
80025ea: 687b ldr r3, [r7, #4]
80025ec: 68da ldr r2, [r3, #12]
80025ee: 687b ldr r3, [r7, #4]
80025f0: 681b ldr r3, [r3, #0]
80025f2: 430a orrs r2, r1
80025f4: 609a str r2, [r3, #8]
/* Enable external trigger if trigger selection is different of software */
/* start. */
/* Note: This configuration keeps the hardware feature of parameter */
/* ExternalTrigConvEdge "trigger edge none" equivalent to */
/* software start. */
if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
80025f6: 687b ldr r3, [r7, #4]
80025f8: 6a9b ldr r3, [r3, #40] ; 0x28
80025fa: 4a58 ldr r2, [pc, #352] ; (800275c <ADC_Init+0x1f4>)
80025fc: 4293 cmp r3, r2
80025fe: d022 beq.n 8002646 <ADC_Init+0xde>
{
/* Select external trigger to start conversion */
hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
8002600: 687b ldr r3, [r7, #4]
8002602: 681b ldr r3, [r3, #0]
8002604: 689a ldr r2, [r3, #8]
8002606: 687b ldr r3, [r7, #4]
8002608: 681b ldr r3, [r3, #0]
800260a: f022 6270 bic.w r2, r2, #251658240 ; 0xf000000
800260e: 609a str r2, [r3, #8]
hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv;
8002610: 687b ldr r3, [r7, #4]
8002612: 681b ldr r3, [r3, #0]
8002614: 6899 ldr r1, [r3, #8]
8002616: 687b ldr r3, [r7, #4]
8002618: 6a9a ldr r2, [r3, #40] ; 0x28
800261a: 687b ldr r3, [r7, #4]
800261c: 681b ldr r3, [r3, #0]
800261e: 430a orrs r2, r1
8002620: 609a str r2, [r3, #8]
/* Select external trigger polarity */
hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
8002622: 687b ldr r3, [r7, #4]
8002624: 681b ldr r3, [r3, #0]
8002626: 689a ldr r2, [r3, #8]
8002628: 687b ldr r3, [r7, #4]
800262a: 681b ldr r3, [r3, #0]
800262c: f022 5240 bic.w r2, r2, #805306368 ; 0x30000000
8002630: 609a str r2, [r3, #8]
hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge;
8002632: 687b ldr r3, [r7, #4]
8002634: 681b ldr r3, [r3, #0]
8002636: 6899 ldr r1, [r3, #8]
8002638: 687b ldr r3, [r7, #4]
800263a: 6ada ldr r2, [r3, #44] ; 0x2c
800263c: 687b ldr r3, [r7, #4]
800263e: 681b ldr r3, [r3, #0]
8002640: 430a orrs r2, r1
8002642: 609a str r2, [r3, #8]
8002644: e00f b.n 8002666 <ADC_Init+0xfe>
}
else
{
/* Reset the external trigger */
hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
8002646: 687b ldr r3, [r7, #4]
8002648: 681b ldr r3, [r3, #0]
800264a: 689a ldr r2, [r3, #8]
800264c: 687b ldr r3, [r7, #4]
800264e: 681b ldr r3, [r3, #0]
8002650: f022 6270 bic.w r2, r2, #251658240 ; 0xf000000
8002654: 609a str r2, [r3, #8]
hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
8002656: 687b ldr r3, [r7, #4]
8002658: 681b ldr r3, [r3, #0]
800265a: 689a ldr r2, [r3, #8]
800265c: 687b ldr r3, [r7, #4]
800265e: 681b ldr r3, [r3, #0]
8002660: f022 5240 bic.w r2, r2, #805306368 ; 0x30000000
8002664: 609a str r2, [r3, #8]
}
/* Enable or disable ADC continuous conversion mode */
hadc->Instance->CR2 &= ~(ADC_CR2_CONT);
8002666: 687b ldr r3, [r7, #4]
8002668: 681b ldr r3, [r3, #0]
800266a: 689a ldr r2, [r3, #8]
800266c: 687b ldr r3, [r7, #4]
800266e: 681b ldr r3, [r3, #0]
8002670: f022 0202 bic.w r2, r2, #2
8002674: 609a str r2, [r3, #8]
hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode);
8002676: 687b ldr r3, [r7, #4]
8002678: 681b ldr r3, [r3, #0]
800267a: 6899 ldr r1, [r3, #8]
800267c: 687b ldr r3, [r7, #4]
800267e: 7e1b ldrb r3, [r3, #24]
8002680: 005a lsls r2, r3, #1
8002682: 687b ldr r3, [r7, #4]
8002684: 681b ldr r3, [r3, #0]
8002686: 430a orrs r2, r1
8002688: 609a str r2, [r3, #8]
if(hadc->Init.DiscontinuousConvMode != DISABLE)
800268a: 687b ldr r3, [r7, #4]
800268c: f893 3020 ldrb.w r3, [r3, #32]
8002690: 2b00 cmp r3, #0
8002692: d01b beq.n 80026cc <ADC_Init+0x164>
{
assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion));
/* Enable the selected ADC regular discontinuous mode */
hadc->Instance->CR1 |= (uint32_t)ADC_CR1_DISCEN;
8002694: 687b ldr r3, [r7, #4]
8002696: 681b ldr r3, [r3, #0]
8002698: 685a ldr r2, [r3, #4]
800269a: 687b ldr r3, [r7, #4]
800269c: 681b ldr r3, [r3, #0]
800269e: f442 6200 orr.w r2, r2, #2048 ; 0x800
80026a2: 605a str r2, [r3, #4]
/* Set the number of channels to be converted in discontinuous mode */
hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM);
80026a4: 687b ldr r3, [r7, #4]
80026a6: 681b ldr r3, [r3, #0]
80026a8: 685a ldr r2, [r3, #4]
80026aa: 687b ldr r3, [r7, #4]
80026ac: 681b ldr r3, [r3, #0]
80026ae: f422 4260 bic.w r2, r2, #57344 ; 0xe000
80026b2: 605a str r2, [r3, #4]
hadc->Instance->CR1 |= ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion);
80026b4: 687b ldr r3, [r7, #4]
80026b6: 681b ldr r3, [r3, #0]
80026b8: 6859 ldr r1, [r3, #4]
80026ba: 687b ldr r3, [r7, #4]
80026bc: 6a5b ldr r3, [r3, #36] ; 0x24
80026be: 3b01 subs r3, #1
80026c0: 035a lsls r2, r3, #13
80026c2: 687b ldr r3, [r7, #4]
80026c4: 681b ldr r3, [r3, #0]
80026c6: 430a orrs r2, r1
80026c8: 605a str r2, [r3, #4]
80026ca: e007 b.n 80026dc <ADC_Init+0x174>
}
else
{
/* Disable the selected ADC regular discontinuous mode */
hadc->Instance->CR1 &= ~(ADC_CR1_DISCEN);
80026cc: 687b ldr r3, [r7, #4]
80026ce: 681b ldr r3, [r3, #0]
80026d0: 685a ldr r2, [r3, #4]
80026d2: 687b ldr r3, [r7, #4]
80026d4: 681b ldr r3, [r3, #0]
80026d6: f422 6200 bic.w r2, r2, #2048 ; 0x800
80026da: 605a str r2, [r3, #4]
}
/* Set ADC number of conversion */
hadc->Instance->SQR1 &= ~(ADC_SQR1_L);
80026dc: 687b ldr r3, [r7, #4]
80026de: 681b ldr r3, [r3, #0]
80026e0: 6ada ldr r2, [r3, #44] ; 0x2c
80026e2: 687b ldr r3, [r7, #4]
80026e4: 681b ldr r3, [r3, #0]
80026e6: f422 0270 bic.w r2, r2, #15728640 ; 0xf00000
80026ea: 62da str r2, [r3, #44] ; 0x2c
hadc->Instance->SQR1 |= ADC_SQR1(hadc->Init.NbrOfConversion);
80026ec: 687b ldr r3, [r7, #4]
80026ee: 681b ldr r3, [r3, #0]
80026f0: 6ad9 ldr r1, [r3, #44] ; 0x2c
80026f2: 687b ldr r3, [r7, #4]
80026f4: 69db ldr r3, [r3, #28]
80026f6: 3b01 subs r3, #1
80026f8: 051a lsls r2, r3, #20
80026fa: 687b ldr r3, [r7, #4]
80026fc: 681b ldr r3, [r3, #0]
80026fe: 430a orrs r2, r1
8002700: 62da str r2, [r3, #44] ; 0x2c
/* Enable or disable ADC DMA continuous request */
hadc->Instance->CR2 &= ~(ADC_CR2_DDS);
8002702: 687b ldr r3, [r7, #4]
8002704: 681b ldr r3, [r3, #0]
8002706: 689a ldr r2, [r3, #8]
8002708: 687b ldr r3, [r7, #4]
800270a: 681b ldr r3, [r3, #0]
800270c: f422 7200 bic.w r2, r2, #512 ; 0x200
8002710: 609a str r2, [r3, #8]
hadc->Instance->CR2 |= ADC_CR2_DMAContReq((uint32_t)hadc->Init.DMAContinuousRequests);
8002712: 687b ldr r3, [r7, #4]
8002714: 681b ldr r3, [r3, #0]
8002716: 6899 ldr r1, [r3, #8]
8002718: 687b ldr r3, [r7, #4]
800271a: f893 3030 ldrb.w r3, [r3, #48] ; 0x30
800271e: 025a lsls r2, r3, #9
8002720: 687b ldr r3, [r7, #4]
8002722: 681b ldr r3, [r3, #0]
8002724: 430a orrs r2, r1
8002726: 609a str r2, [r3, #8]
/* Enable or disable ADC end of conversion selection */
hadc->Instance->CR2 &= ~(ADC_CR2_EOCS);
8002728: 687b ldr r3, [r7, #4]
800272a: 681b ldr r3, [r3, #0]
800272c: 689a ldr r2, [r3, #8]
800272e: 687b ldr r3, [r7, #4]
8002730: 681b ldr r3, [r3, #0]
8002732: f422 6280 bic.w r2, r2, #1024 ; 0x400
8002736: 609a str r2, [r3, #8]
hadc->Instance->CR2 |= ADC_CR2_EOCSelection(hadc->Init.EOCSelection);
8002738: 687b ldr r3, [r7, #4]
800273a: 681b ldr r3, [r3, #0]
800273c: 6899 ldr r1, [r3, #8]
800273e: 687b ldr r3, [r7, #4]
8002740: 695b ldr r3, [r3, #20]
8002742: 029a lsls r2, r3, #10
8002744: 687b ldr r3, [r7, #4]
8002746: 681b ldr r3, [r3, #0]
8002748: 430a orrs r2, r1
800274a: 609a str r2, [r3, #8]
}
800274c: bf00 nop
800274e: 3714 adds r7, #20
8002750: 46bd mov sp, r7
8002752: f85d 7b04 ldr.w r7, [sp], #4
8002756: 4770 bx lr
8002758: 40012300 .word 0x40012300
800275c: 0f000001 .word 0x0f000001
08002760 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8002760: b480 push {r7}
8002762: b085 sub sp, #20
8002764: af00 add r7, sp, #0
8002766: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8002768: 687b ldr r3, [r7, #4]
800276a: f003 0307 and.w r3, r3, #7
800276e: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
8002770: 4b0c ldr r3, [pc, #48] ; (80027a4 <__NVIC_SetPriorityGrouping+0x44>)
8002772: 68db ldr r3, [r3, #12]
8002774: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
8002776: 68ba ldr r2, [r7, #8]
8002778: f64f 03ff movw r3, #63743 ; 0xf8ff
800277c: 4013 ands r3, r2
800277e: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
8002780: 68fb ldr r3, [r7, #12]
8002782: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
8002784: 68bb ldr r3, [r7, #8]
8002786: 4313 orrs r3, r2
reg_value = (reg_value |
8002788: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000
800278c: f443 3300 orr.w r3, r3, #131072 ; 0x20000
8002790: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
8002792: 4a04 ldr r2, [pc, #16] ; (80027a4 <__NVIC_SetPriorityGrouping+0x44>)
8002794: 68bb ldr r3, [r7, #8]
8002796: 60d3 str r3, [r2, #12]
}
8002798: bf00 nop
800279a: 3714 adds r7, #20
800279c: 46bd mov sp, r7
800279e: f85d 7b04 ldr.w r7, [sp], #4
80027a2: 4770 bx lr
80027a4: e000ed00 .word 0xe000ed00
080027a8 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
80027a8: b480 push {r7}
80027aa: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
80027ac: 4b04 ldr r3, [pc, #16] ; (80027c0 <__NVIC_GetPriorityGrouping+0x18>)
80027ae: 68db ldr r3, [r3, #12]
80027b0: 0a1b lsrs r3, r3, #8
80027b2: f003 0307 and.w r3, r3, #7
}
80027b6: 4618 mov r0, r3
80027b8: 46bd mov sp, r7
80027ba: f85d 7b04 ldr.w r7, [sp], #4
80027be: 4770 bx lr
80027c0: e000ed00 .word 0xe000ed00
080027c4 <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
80027c4: b480 push {r7}
80027c6: b083 sub sp, #12
80027c8: af00 add r7, sp, #0
80027ca: 4603 mov r3, r0
80027cc: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
80027ce: f997 3007 ldrsb.w r3, [r7, #7]
80027d2: 2b00 cmp r3, #0
80027d4: db0b blt.n 80027ee <__NVIC_EnableIRQ+0x2a>
{
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
80027d6: 79fb ldrb r3, [r7, #7]
80027d8: f003 021f and.w r2, r3, #31
80027dc: 4907 ldr r1, [pc, #28] ; (80027fc <__NVIC_EnableIRQ+0x38>)
80027de: f997 3007 ldrsb.w r3, [r7, #7]
80027e2: 095b lsrs r3, r3, #5
80027e4: 2001 movs r0, #1
80027e6: fa00 f202 lsl.w r2, r0, r2
80027ea: f841 2023 str.w r2, [r1, r3, lsl #2]
}
}
80027ee: bf00 nop
80027f0: 370c adds r7, #12
80027f2: 46bd mov sp, r7
80027f4: f85d 7b04 ldr.w r7, [sp], #4
80027f8: 4770 bx lr
80027fa: bf00 nop
80027fc: e000e100 .word 0xe000e100
08002800 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8002800: b480 push {r7}
8002802: b083 sub sp, #12
8002804: af00 add r7, sp, #0
8002806: 4603 mov r3, r0
8002808: 6039 str r1, [r7, #0]
800280a: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
800280c: f997 3007 ldrsb.w r3, [r7, #7]
8002810: 2b00 cmp r3, #0
8002812: db0a blt.n 800282a <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8002814: 683b ldr r3, [r7, #0]
8002816: b2da uxtb r2, r3
8002818: 490c ldr r1, [pc, #48] ; (800284c <__NVIC_SetPriority+0x4c>)
800281a: f997 3007 ldrsb.w r3, [r7, #7]
800281e: 0112 lsls r2, r2, #4
8002820: b2d2 uxtb r2, r2
8002822: 440b add r3, r1
8002824: f883 2300 strb.w r2, [r3, #768] ; 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
8002828: e00a b.n 8002840 <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
800282a: 683b ldr r3, [r7, #0]
800282c: b2da uxtb r2, r3
800282e: 4908 ldr r1, [pc, #32] ; (8002850 <__NVIC_SetPriority+0x50>)
8002830: 79fb ldrb r3, [r7, #7]
8002832: f003 030f and.w r3, r3, #15
8002836: 3b04 subs r3, #4
8002838: 0112 lsls r2, r2, #4
800283a: b2d2 uxtb r2, r2
800283c: 440b add r3, r1
800283e: 761a strb r2, [r3, #24]
}
8002840: bf00 nop
8002842: 370c adds r7, #12
8002844: 46bd mov sp, r7
8002846: f85d 7b04 ldr.w r7, [sp], #4
800284a: 4770 bx lr
800284c: e000e100 .word 0xe000e100
8002850: e000ed00 .word 0xe000ed00
08002854 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
8002854: b480 push {r7}
8002856: b089 sub sp, #36 ; 0x24
8002858: af00 add r7, sp, #0
800285a: 60f8 str r0, [r7, #12]
800285c: 60b9 str r1, [r7, #8]
800285e: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8002860: 68fb ldr r3, [r7, #12]
8002862: f003 0307 and.w r3, r3, #7
8002866: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
8002868: 69fb ldr r3, [r7, #28]
800286a: f1c3 0307 rsb r3, r3, #7
800286e: 2b04 cmp r3, #4
8002870: bf28 it cs
8002872: 2304 movcs r3, #4
8002874: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
8002876: 69fb ldr r3, [r7, #28]
8002878: 3304 adds r3, #4
800287a: 2b06 cmp r3, #6
800287c: d902 bls.n 8002884 <NVIC_EncodePriority+0x30>
800287e: 69fb ldr r3, [r7, #28]
8002880: 3b03 subs r3, #3
8002882: e000 b.n 8002886 <NVIC_EncodePriority+0x32>
8002884: 2300 movs r3, #0
8002886: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8002888: f04f 32ff mov.w r2, #4294967295
800288c: 69bb ldr r3, [r7, #24]
800288e: fa02 f303 lsl.w r3, r2, r3
8002892: 43da mvns r2, r3
8002894: 68bb ldr r3, [r7, #8]
8002896: 401a ands r2, r3
8002898: 697b ldr r3, [r7, #20]
800289a: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
800289c: f04f 31ff mov.w r1, #4294967295
80028a0: 697b ldr r3, [r7, #20]
80028a2: fa01 f303 lsl.w r3, r1, r3
80028a6: 43d9 mvns r1, r3
80028a8: 687b ldr r3, [r7, #4]
80028aa: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
80028ac: 4313 orrs r3, r2
);
}
80028ae: 4618 mov r0, r3
80028b0: 3724 adds r7, #36 ; 0x24
80028b2: 46bd mov sp, r7
80028b4: f85d 7b04 ldr.w r7, [sp], #4
80028b8: 4770 bx lr
...
080028bc <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
80028bc: b580 push {r7, lr}
80028be: b082 sub sp, #8
80028c0: af00 add r7, sp, #0
80028c2: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
80028c4: 687b ldr r3, [r7, #4]
80028c6: 3b01 subs r3, #1
80028c8: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
80028cc: d301 bcc.n 80028d2 <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
80028ce: 2301 movs r3, #1
80028d0: e00f b.n 80028f2 <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
80028d2: 4a0a ldr r2, [pc, #40] ; (80028fc <SysTick_Config+0x40>)
80028d4: 687b ldr r3, [r7, #4]
80028d6: 3b01 subs r3, #1
80028d8: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
80028da: 210f movs r1, #15
80028dc: f04f 30ff mov.w r0, #4294967295
80028e0: f7ff ff8e bl 8002800 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
80028e4: 4b05 ldr r3, [pc, #20] ; (80028fc <SysTick_Config+0x40>)
80028e6: 2200 movs r2, #0
80028e8: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
80028ea: 4b04 ldr r3, [pc, #16] ; (80028fc <SysTick_Config+0x40>)
80028ec: 2207 movs r2, #7
80028ee: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
80028f0: 2300 movs r3, #0
}
80028f2: 4618 mov r0, r3
80028f4: 3708 adds r7, #8
80028f6: 46bd mov sp, r7
80028f8: bd80 pop {r7, pc}
80028fa: bf00 nop
80028fc: e000e010 .word 0xe000e010
08002900 <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8002900: b580 push {r7, lr}
8002902: b082 sub sp, #8
8002904: af00 add r7, sp, #0
8002906: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
8002908: 6878 ldr r0, [r7, #4]
800290a: f7ff ff29 bl 8002760 <__NVIC_SetPriorityGrouping>
}
800290e: bf00 nop
8002910: 3708 adds r7, #8
8002912: 46bd mov sp, r7
8002914: bd80 pop {r7, pc}
08002916 <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8002916: b580 push {r7, lr}
8002918: b086 sub sp, #24
800291a: af00 add r7, sp, #0
800291c: 4603 mov r3, r0
800291e: 60b9 str r1, [r7, #8]
8002920: 607a str r2, [r7, #4]
8002922: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00U;
8002924: 2300 movs r3, #0
8002926: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
8002928: f7ff ff3e bl 80027a8 <__NVIC_GetPriorityGrouping>
800292c: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
800292e: 687a ldr r2, [r7, #4]
8002930: 68b9 ldr r1, [r7, #8]
8002932: 6978 ldr r0, [r7, #20]
8002934: f7ff ff8e bl 8002854 <NVIC_EncodePriority>
8002938: 4602 mov r2, r0
800293a: f997 300f ldrsb.w r3, [r7, #15]
800293e: 4611 mov r1, r2
8002940: 4618 mov r0, r3
8002942: f7ff ff5d bl 8002800 <__NVIC_SetPriority>
}
8002946: bf00 nop
8002948: 3718 adds r7, #24
800294a: 46bd mov sp, r7
800294c: bd80 pop {r7, pc}
0800294e <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
800294e: b580 push {r7, lr}
8002950: b082 sub sp, #8
8002952: af00 add r7, sp, #0
8002954: 4603 mov r3, r0
8002956: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
8002958: f997 3007 ldrsb.w r3, [r7, #7]
800295c: 4618 mov r0, r3
800295e: f7ff ff31 bl 80027c4 <__NVIC_EnableIRQ>
}
8002962: bf00 nop
8002964: 3708 adds r7, #8
8002966: 46bd mov sp, r7
8002968: bd80 pop {r7, pc}
0800296a <HAL_SYSTICK_Config>:
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
800296a: b580 push {r7, lr}
800296c: b082 sub sp, #8
800296e: af00 add r7, sp, #0
8002970: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
8002972: 6878 ldr r0, [r7, #4]
8002974: f7ff ffa2 bl 80028bc <SysTick_Config>
8002978: 4603 mov r3, r0
}
800297a: 4618 mov r0, r3
800297c: 3708 adds r7, #8
800297e: 46bd mov sp, r7
8002980: bd80 pop {r7, pc}
08002982 <HAL_DMA_Abort_IT>:
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
{
8002982: b480 push {r7}
8002984: b083 sub sp, #12
8002986: af00 add r7, sp, #0
8002988: 6078 str r0, [r7, #4]
if(hdma->State != HAL_DMA_STATE_BUSY)
800298a: 687b ldr r3, [r7, #4]
800298c: f893 3035 ldrb.w r3, [r3, #53] ; 0x35
8002990: b2db uxtb r3, r3
8002992: 2b02 cmp r3, #2
8002994: d004 beq.n 80029a0 <HAL_DMA_Abort_IT+0x1e>
{
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
8002996: 687b ldr r3, [r7, #4]
8002998: 2280 movs r2, #128 ; 0x80
800299a: 655a str r2, [r3, #84] ; 0x54
return HAL_ERROR;
800299c: 2301 movs r3, #1
800299e: e00c b.n 80029ba <HAL_DMA_Abort_IT+0x38>
}
else
{
/* Set Abort State */
hdma->State = HAL_DMA_STATE_ABORT;
80029a0: 687b ldr r3, [r7, #4]
80029a2: 2205 movs r2, #5
80029a4: f883 2035 strb.w r2, [r3, #53] ; 0x35
/* Disable the stream */
__HAL_DMA_DISABLE(hdma);
80029a8: 687b ldr r3, [r7, #4]
80029aa: 681b ldr r3, [r3, #0]
80029ac: 681a ldr r2, [r3, #0]
80029ae: 687b ldr r3, [r7, #4]
80029b0: 681b ldr r3, [r3, #0]
80029b2: f022 0201 bic.w r2, r2, #1
80029b6: 601a str r2, [r3, #0]
}
return HAL_OK;
80029b8: 2300 movs r3, #0
}
80029ba: 4618 mov r0, r3
80029bc: 370c adds r7, #12
80029be: 46bd mov sp, r7
80029c0: f85d 7b04 ldr.w r7, [sp], #4
80029c4: 4770 bx lr
...
080029c8 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
80029c8: b480 push {r7}
80029ca: b089 sub sp, #36 ; 0x24
80029cc: af00 add r7, sp, #0
80029ce: 6078 str r0, [r7, #4]
80029d0: 6039 str r1, [r7, #0]
uint32_t position;
uint32_t ioposition = 0x00U;
80029d2: 2300 movs r3, #0
80029d4: 617b str r3, [r7, #20]
uint32_t iocurrent = 0x00U;
80029d6: 2300 movs r3, #0
80029d8: 613b str r3, [r7, #16]
uint32_t temp = 0x00U;
80029da: 2300 movs r3, #0
80029dc: 61bb str r3, [r7, #24]
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Configure the port pins */
for(position = 0U; position < GPIO_NUMBER; position++)
80029de: 2300 movs r3, #0
80029e0: 61fb str r3, [r7, #28]
80029e2: e177 b.n 8002cd4 <HAL_GPIO_Init+0x30c>
{
/* Get the IO position */
ioposition = 0x01U << position;
80029e4: 2201 movs r2, #1
80029e6: 69fb ldr r3, [r7, #28]
80029e8: fa02 f303 lsl.w r3, r2, r3
80029ec: 617b str r3, [r7, #20]
/* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
80029ee: 683b ldr r3, [r7, #0]
80029f0: 681b ldr r3, [r3, #0]
80029f2: 697a ldr r2, [r7, #20]
80029f4: 4013 ands r3, r2
80029f6: 613b str r3, [r7, #16]
if(iocurrent == ioposition)
80029f8: 693a ldr r2, [r7, #16]
80029fa: 697b ldr r3, [r7, #20]
80029fc: 429a cmp r2, r3
80029fe: f040 8166 bne.w 8002cce <HAL_GPIO_Init+0x306>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
8002a02: 683b ldr r3, [r7, #0]
8002a04: 685b ldr r3, [r3, #4]
8002a06: 2b01 cmp r3, #1
8002a08: d00b beq.n 8002a22 <HAL_GPIO_Init+0x5a>
8002a0a: 683b ldr r3, [r7, #0]
8002a0c: 685b ldr r3, [r3, #4]
8002a0e: 2b02 cmp r3, #2
8002a10: d007 beq.n 8002a22 <HAL_GPIO_Init+0x5a>
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
8002a12: 683b ldr r3, [r7, #0]
8002a14: 685b ldr r3, [r3, #4]
if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
8002a16: 2b11 cmp r3, #17
8002a18: d003 beq.n 8002a22 <HAL_GPIO_Init+0x5a>
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
8002a1a: 683b ldr r3, [r7, #0]
8002a1c: 685b ldr r3, [r3, #4]
8002a1e: 2b12 cmp r3, #18
8002a20: d130 bne.n 8002a84 <HAL_GPIO_Init+0xbc>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
8002a22: 687b ldr r3, [r7, #4]
8002a24: 689b ldr r3, [r3, #8]
8002a26: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
8002a28: 69fb ldr r3, [r7, #28]
8002a2a: 005b lsls r3, r3, #1
8002a2c: 2203 movs r2, #3
8002a2e: fa02 f303 lsl.w r3, r2, r3
8002a32: 43db mvns r3, r3
8002a34: 69ba ldr r2, [r7, #24]
8002a36: 4013 ands r3, r2
8002a38: 61bb str r3, [r7, #24]
temp |= (GPIO_Init->Speed << (position * 2U));
8002a3a: 683b ldr r3, [r7, #0]
8002a3c: 68da ldr r2, [r3, #12]
8002a3e: 69fb ldr r3, [r7, #28]
8002a40: 005b lsls r3, r3, #1
8002a42: fa02 f303 lsl.w r3, r2, r3
8002a46: 69ba ldr r2, [r7, #24]
8002a48: 4313 orrs r3, r2
8002a4a: 61bb str r3, [r7, #24]
GPIOx->OSPEEDR = temp;
8002a4c: 687b ldr r3, [r7, #4]
8002a4e: 69ba ldr r2, [r7, #24]
8002a50: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
8002a52: 687b ldr r3, [r7, #4]
8002a54: 685b ldr r3, [r3, #4]
8002a56: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
8002a58: 2201 movs r2, #1
8002a5a: 69fb ldr r3, [r7, #28]
8002a5c: fa02 f303 lsl.w r3, r2, r3
8002a60: 43db mvns r3, r3
8002a62: 69ba ldr r2, [r7, #24]
8002a64: 4013 ands r3, r2
8002a66: 61bb str r3, [r7, #24]
temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
8002a68: 683b ldr r3, [r7, #0]
8002a6a: 685b ldr r3, [r3, #4]
8002a6c: 091b lsrs r3, r3, #4
8002a6e: f003 0201 and.w r2, r3, #1
8002a72: 69fb ldr r3, [r7, #28]
8002a74: fa02 f303 lsl.w r3, r2, r3
8002a78: 69ba ldr r2, [r7, #24]
8002a7a: 4313 orrs r3, r2
8002a7c: 61bb str r3, [r7, #24]
GPIOx->OTYPER = temp;
8002a7e: 687b ldr r3, [r7, #4]
8002a80: 69ba ldr r2, [r7, #24]
8002a82: 605a str r2, [r3, #4]
}
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
8002a84: 687b ldr r3, [r7, #4]
8002a86: 68db ldr r3, [r3, #12]
8002a88: 61bb str r3, [r7, #24]
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
8002a8a: 69fb ldr r3, [r7, #28]
8002a8c: 005b lsls r3, r3, #1
8002a8e: 2203 movs r2, #3
8002a90: fa02 f303 lsl.w r3, r2, r3
8002a94: 43db mvns r3, r3
8002a96: 69ba ldr r2, [r7, #24]
8002a98: 4013 ands r3, r2
8002a9a: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Pull) << (position * 2U));
8002a9c: 683b ldr r3, [r7, #0]
8002a9e: 689a ldr r2, [r3, #8]
8002aa0: 69fb ldr r3, [r7, #28]
8002aa2: 005b lsls r3, r3, #1
8002aa4: fa02 f303 lsl.w r3, r2, r3
8002aa8: 69ba ldr r2, [r7, #24]
8002aaa: 4313 orrs r3, r2
8002aac: 61bb str r3, [r7, #24]
GPIOx->PUPDR = temp;
8002aae: 687b ldr r3, [r7, #4]
8002ab0: 69ba ldr r2, [r7, #24]
8002ab2: 60da str r2, [r3, #12]
/* In case of Alternate function mode selection */
if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
8002ab4: 683b ldr r3, [r7, #0]
8002ab6: 685b ldr r3, [r3, #4]
8002ab8: 2b02 cmp r3, #2
8002aba: d003 beq.n 8002ac4 <HAL_GPIO_Init+0xfc>
8002abc: 683b ldr r3, [r7, #0]
8002abe: 685b ldr r3, [r3, #4]
8002ac0: 2b12 cmp r3, #18
8002ac2: d123 bne.n 8002b0c <HAL_GPIO_Init+0x144>
{
/* Check the Alternate function parameter */
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3U];
8002ac4: 69fb ldr r3, [r7, #28]
8002ac6: 08da lsrs r2, r3, #3
8002ac8: 687b ldr r3, [r7, #4]
8002aca: 3208 adds r2, #8
8002acc: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8002ad0: 61bb str r3, [r7, #24]
temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
8002ad2: 69fb ldr r3, [r7, #28]
8002ad4: f003 0307 and.w r3, r3, #7
8002ad8: 009b lsls r3, r3, #2
8002ada: 220f movs r2, #15
8002adc: fa02 f303 lsl.w r3, r2, r3
8002ae0: 43db mvns r3, r3
8002ae2: 69ba ldr r2, [r7, #24]
8002ae4: 4013 ands r3, r2
8002ae6: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
8002ae8: 683b ldr r3, [r7, #0]
8002aea: 691a ldr r2, [r3, #16]
8002aec: 69fb ldr r3, [r7, #28]
8002aee: f003 0307 and.w r3, r3, #7
8002af2: 009b lsls r3, r3, #2
8002af4: fa02 f303 lsl.w r3, r2, r3
8002af8: 69ba ldr r2, [r7, #24]
8002afa: 4313 orrs r3, r2
8002afc: 61bb str r3, [r7, #24]
GPIOx->AFR[position >> 3U] = temp;
8002afe: 69fb ldr r3, [r7, #28]
8002b00: 08da lsrs r2, r3, #3
8002b02: 687b ldr r3, [r7, #4]
8002b04: 3208 adds r2, #8
8002b06: 69b9 ldr r1, [r7, #24]
8002b08: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
8002b0c: 687b ldr r3, [r7, #4]
8002b0e: 681b ldr r3, [r3, #0]
8002b10: 61bb str r3, [r7, #24]
temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
8002b12: 69fb ldr r3, [r7, #28]
8002b14: 005b lsls r3, r3, #1
8002b16: 2203 movs r2, #3
8002b18: fa02 f303 lsl.w r3, r2, r3
8002b1c: 43db mvns r3, r3
8002b1e: 69ba ldr r2, [r7, #24]
8002b20: 4013 ands r3, r2
8002b22: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
8002b24: 683b ldr r3, [r7, #0]
8002b26: 685b ldr r3, [r3, #4]
8002b28: f003 0203 and.w r2, r3, #3
8002b2c: 69fb ldr r3, [r7, #28]
8002b2e: 005b lsls r3, r3, #1
8002b30: fa02 f303 lsl.w r3, r2, r3
8002b34: 69ba ldr r2, [r7, #24]
8002b36: 4313 orrs r3, r2
8002b38: 61bb str r3, [r7, #24]
GPIOx->MODER = temp;
8002b3a: 687b ldr r3, [r7, #4]
8002b3c: 69ba ldr r2, [r7, #24]
8002b3e: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
8002b40: 683b ldr r3, [r7, #0]
8002b42: 685b ldr r3, [r3, #4]
8002b44: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8002b48: 2b00 cmp r3, #0
8002b4a: f000 80c0 beq.w 8002cce <HAL_GPIO_Init+0x306>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8002b4e: 2300 movs r3, #0
8002b50: 60fb str r3, [r7, #12]
8002b52: 4b65 ldr r3, [pc, #404] ; (8002ce8 <HAL_GPIO_Init+0x320>)
8002b54: 6c5b ldr r3, [r3, #68] ; 0x44
8002b56: 4a64 ldr r2, [pc, #400] ; (8002ce8 <HAL_GPIO_Init+0x320>)
8002b58: f443 4380 orr.w r3, r3, #16384 ; 0x4000
8002b5c: 6453 str r3, [r2, #68] ; 0x44
8002b5e: 4b62 ldr r3, [pc, #392] ; (8002ce8 <HAL_GPIO_Init+0x320>)
8002b60: 6c5b ldr r3, [r3, #68] ; 0x44
8002b62: f403 4380 and.w r3, r3, #16384 ; 0x4000
8002b66: 60fb str r3, [r7, #12]
8002b68: 68fb ldr r3, [r7, #12]
temp = SYSCFG->EXTICR[position >> 2U];
8002b6a: 4a60 ldr r2, [pc, #384] ; (8002cec <HAL_GPIO_Init+0x324>)
8002b6c: 69fb ldr r3, [r7, #28]
8002b6e: 089b lsrs r3, r3, #2
8002b70: 3302 adds r3, #2
8002b72: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8002b76: 61bb str r3, [r7, #24]
temp &= ~(0x0FU << (4U * (position & 0x03U)));
8002b78: 69fb ldr r3, [r7, #28]
8002b7a: f003 0303 and.w r3, r3, #3
8002b7e: 009b lsls r3, r3, #2
8002b80: 220f movs r2, #15
8002b82: fa02 f303 lsl.w r3, r2, r3
8002b86: 43db mvns r3, r3
8002b88: 69ba ldr r2, [r7, #24]
8002b8a: 4013 ands r3, r2
8002b8c: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
8002b8e: 687b ldr r3, [r7, #4]
8002b90: 4a57 ldr r2, [pc, #348] ; (8002cf0 <HAL_GPIO_Init+0x328>)
8002b92: 4293 cmp r3, r2
8002b94: d037 beq.n 8002c06 <HAL_GPIO_Init+0x23e>
8002b96: 687b ldr r3, [r7, #4]
8002b98: 4a56 ldr r2, [pc, #344] ; (8002cf4 <HAL_GPIO_Init+0x32c>)
8002b9a: 4293 cmp r3, r2
8002b9c: d031 beq.n 8002c02 <HAL_GPIO_Init+0x23a>
8002b9e: 687b ldr r3, [r7, #4]
8002ba0: 4a55 ldr r2, [pc, #340] ; (8002cf8 <HAL_GPIO_Init+0x330>)
8002ba2: 4293 cmp r3, r2
8002ba4: d02b beq.n 8002bfe <HAL_GPIO_Init+0x236>
8002ba6: 687b ldr r3, [r7, #4]
8002ba8: 4a54 ldr r2, [pc, #336] ; (8002cfc <HAL_GPIO_Init+0x334>)
8002baa: 4293 cmp r3, r2
8002bac: d025 beq.n 8002bfa <HAL_GPIO_Init+0x232>
8002bae: 687b ldr r3, [r7, #4]
8002bb0: 4a53 ldr r2, [pc, #332] ; (8002d00 <HAL_GPIO_Init+0x338>)
8002bb2: 4293 cmp r3, r2
8002bb4: d01f beq.n 8002bf6 <HAL_GPIO_Init+0x22e>
8002bb6: 687b ldr r3, [r7, #4]
8002bb8: 4a52 ldr r2, [pc, #328] ; (8002d04 <HAL_GPIO_Init+0x33c>)
8002bba: 4293 cmp r3, r2
8002bbc: d019 beq.n 8002bf2 <HAL_GPIO_Init+0x22a>
8002bbe: 687b ldr r3, [r7, #4]
8002bc0: 4a51 ldr r2, [pc, #324] ; (8002d08 <HAL_GPIO_Init+0x340>)
8002bc2: 4293 cmp r3, r2
8002bc4: d013 beq.n 8002bee <HAL_GPIO_Init+0x226>
8002bc6: 687b ldr r3, [r7, #4]
8002bc8: 4a50 ldr r2, [pc, #320] ; (8002d0c <HAL_GPIO_Init+0x344>)
8002bca: 4293 cmp r3, r2
8002bcc: d00d beq.n 8002bea <HAL_GPIO_Init+0x222>
8002bce: 687b ldr r3, [r7, #4]
8002bd0: 4a4f ldr r2, [pc, #316] ; (8002d10 <HAL_GPIO_Init+0x348>)
8002bd2: 4293 cmp r3, r2
8002bd4: d007 beq.n 8002be6 <HAL_GPIO_Init+0x21e>
8002bd6: 687b ldr r3, [r7, #4]
8002bd8: 4a4e ldr r2, [pc, #312] ; (8002d14 <HAL_GPIO_Init+0x34c>)
8002bda: 4293 cmp r3, r2
8002bdc: d101 bne.n 8002be2 <HAL_GPIO_Init+0x21a>
8002bde: 2309 movs r3, #9
8002be0: e012 b.n 8002c08 <HAL_GPIO_Init+0x240>
8002be2: 230a movs r3, #10
8002be4: e010 b.n 8002c08 <HAL_GPIO_Init+0x240>
8002be6: 2308 movs r3, #8
8002be8: e00e b.n 8002c08 <HAL_GPIO_Init+0x240>
8002bea: 2307 movs r3, #7
8002bec: e00c b.n 8002c08 <HAL_GPIO_Init+0x240>
8002bee: 2306 movs r3, #6
8002bf0: e00a b.n 8002c08 <HAL_GPIO_Init+0x240>
8002bf2: 2305 movs r3, #5
8002bf4: e008 b.n 8002c08 <HAL_GPIO_Init+0x240>
8002bf6: 2304 movs r3, #4
8002bf8: e006 b.n 8002c08 <HAL_GPIO_Init+0x240>
8002bfa: 2303 movs r3, #3
8002bfc: e004 b.n 8002c08 <HAL_GPIO_Init+0x240>
8002bfe: 2302 movs r3, #2
8002c00: e002 b.n 8002c08 <HAL_GPIO_Init+0x240>
8002c02: 2301 movs r3, #1
8002c04: e000 b.n 8002c08 <HAL_GPIO_Init+0x240>
8002c06: 2300 movs r3, #0
8002c08: 69fa ldr r2, [r7, #28]
8002c0a: f002 0203 and.w r2, r2, #3
8002c0e: 0092 lsls r2, r2, #2
8002c10: 4093 lsls r3, r2
8002c12: 69ba ldr r2, [r7, #24]
8002c14: 4313 orrs r3, r2
8002c16: 61bb str r3, [r7, #24]
SYSCFG->EXTICR[position >> 2U] = temp;
8002c18: 4934 ldr r1, [pc, #208] ; (8002cec <HAL_GPIO_Init+0x324>)
8002c1a: 69fb ldr r3, [r7, #28]
8002c1c: 089b lsrs r3, r3, #2
8002c1e: 3302 adds r3, #2
8002c20: 69ba ldr r2, [r7, #24]
8002c22: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear EXTI line configuration */
temp = EXTI->IMR;
8002c26: 4b3c ldr r3, [pc, #240] ; (8002d18 <HAL_GPIO_Init+0x350>)
8002c28: 681b ldr r3, [r3, #0]
8002c2a: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8002c2c: 693b ldr r3, [r7, #16]
8002c2e: 43db mvns r3, r3
8002c30: 69ba ldr r2, [r7, #24]
8002c32: 4013 ands r3, r2
8002c34: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
8002c36: 683b ldr r3, [r7, #0]
8002c38: 685b ldr r3, [r3, #4]
8002c3a: f403 3380 and.w r3, r3, #65536 ; 0x10000
8002c3e: 2b00 cmp r3, #0
8002c40: d003 beq.n 8002c4a <HAL_GPIO_Init+0x282>
{
temp |= iocurrent;
8002c42: 69ba ldr r2, [r7, #24]
8002c44: 693b ldr r3, [r7, #16]
8002c46: 4313 orrs r3, r2
8002c48: 61bb str r3, [r7, #24]
}
EXTI->IMR = temp;
8002c4a: 4a33 ldr r2, [pc, #204] ; (8002d18 <HAL_GPIO_Init+0x350>)
8002c4c: 69bb ldr r3, [r7, #24]
8002c4e: 6013 str r3, [r2, #0]
temp = EXTI->EMR;
8002c50: 4b31 ldr r3, [pc, #196] ; (8002d18 <HAL_GPIO_Init+0x350>)
8002c52: 685b ldr r3, [r3, #4]
8002c54: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8002c56: 693b ldr r3, [r7, #16]
8002c58: 43db mvns r3, r3
8002c5a: 69ba ldr r2, [r7, #24]
8002c5c: 4013 ands r3, r2
8002c5e: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
8002c60: 683b ldr r3, [r7, #0]
8002c62: 685b ldr r3, [r3, #4]
8002c64: f403 3300 and.w r3, r3, #131072 ; 0x20000
8002c68: 2b00 cmp r3, #0
8002c6a: d003 beq.n 8002c74 <HAL_GPIO_Init+0x2ac>
{
temp |= iocurrent;
8002c6c: 69ba ldr r2, [r7, #24]
8002c6e: 693b ldr r3, [r7, #16]
8002c70: 4313 orrs r3, r2
8002c72: 61bb str r3, [r7, #24]
}
EXTI->EMR = temp;
8002c74: 4a28 ldr r2, [pc, #160] ; (8002d18 <HAL_GPIO_Init+0x350>)
8002c76: 69bb ldr r3, [r7, #24]
8002c78: 6053 str r3, [r2, #4]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
8002c7a: 4b27 ldr r3, [pc, #156] ; (8002d18 <HAL_GPIO_Init+0x350>)
8002c7c: 689b ldr r3, [r3, #8]
8002c7e: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8002c80: 693b ldr r3, [r7, #16]
8002c82: 43db mvns r3, r3
8002c84: 69ba ldr r2, [r7, #24]
8002c86: 4013 ands r3, r2
8002c88: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
8002c8a: 683b ldr r3, [r7, #0]
8002c8c: 685b ldr r3, [r3, #4]
8002c8e: f403 1380 and.w r3, r3, #1048576 ; 0x100000
8002c92: 2b00 cmp r3, #0
8002c94: d003 beq.n 8002c9e <HAL_GPIO_Init+0x2d6>
{
temp |= iocurrent;
8002c96: 69ba ldr r2, [r7, #24]
8002c98: 693b ldr r3, [r7, #16]
8002c9a: 4313 orrs r3, r2
8002c9c: 61bb str r3, [r7, #24]
}
EXTI->RTSR = temp;
8002c9e: 4a1e ldr r2, [pc, #120] ; (8002d18 <HAL_GPIO_Init+0x350>)
8002ca0: 69bb ldr r3, [r7, #24]
8002ca2: 6093 str r3, [r2, #8]
temp = EXTI->FTSR;
8002ca4: 4b1c ldr r3, [pc, #112] ; (8002d18 <HAL_GPIO_Init+0x350>)
8002ca6: 68db ldr r3, [r3, #12]
8002ca8: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8002caa: 693b ldr r3, [r7, #16]
8002cac: 43db mvns r3, r3
8002cae: 69ba ldr r2, [r7, #24]
8002cb0: 4013 ands r3, r2
8002cb2: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
8002cb4: 683b ldr r3, [r7, #0]
8002cb6: 685b ldr r3, [r3, #4]
8002cb8: f403 1300 and.w r3, r3, #2097152 ; 0x200000
8002cbc: 2b00 cmp r3, #0
8002cbe: d003 beq.n 8002cc8 <HAL_GPIO_Init+0x300>
{
temp |= iocurrent;
8002cc0: 69ba ldr r2, [r7, #24]
8002cc2: 693b ldr r3, [r7, #16]
8002cc4: 4313 orrs r3, r2
8002cc6: 61bb str r3, [r7, #24]
}
EXTI->FTSR = temp;
8002cc8: 4a13 ldr r2, [pc, #76] ; (8002d18 <HAL_GPIO_Init+0x350>)
8002cca: 69bb ldr r3, [r7, #24]
8002ccc: 60d3 str r3, [r2, #12]
for(position = 0U; position < GPIO_NUMBER; position++)
8002cce: 69fb ldr r3, [r7, #28]
8002cd0: 3301 adds r3, #1
8002cd2: 61fb str r3, [r7, #28]
8002cd4: 69fb ldr r3, [r7, #28]
8002cd6: 2b0f cmp r3, #15
8002cd8: f67f ae84 bls.w 80029e4 <HAL_GPIO_Init+0x1c>
}
}
}
}
8002cdc: bf00 nop
8002cde: 3724 adds r7, #36 ; 0x24
8002ce0: 46bd mov sp, r7
8002ce2: f85d 7b04 ldr.w r7, [sp], #4
8002ce6: 4770 bx lr
8002ce8: 40023800 .word 0x40023800
8002cec: 40013800 .word 0x40013800
8002cf0: 40020000 .word 0x40020000
8002cf4: 40020400 .word 0x40020400
8002cf8: 40020800 .word 0x40020800
8002cfc: 40020c00 .word 0x40020c00
8002d00: 40021000 .word 0x40021000
8002d04: 40021400 .word 0x40021400
8002d08: 40021800 .word 0x40021800
8002d0c: 40021c00 .word 0x40021c00
8002d10: 40022000 .word 0x40022000
8002d14: 40022400 .word 0x40022400
8002d18: 40013c00 .word 0x40013c00
08002d1c <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
8002d1c: b480 push {r7}
8002d1e: b083 sub sp, #12
8002d20: af00 add r7, sp, #0
8002d22: 6078 str r0, [r7, #4]
8002d24: 460b mov r3, r1
8002d26: 807b strh r3, [r7, #2]
8002d28: 4613 mov r3, r2
8002d2a: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if(PinState != GPIO_PIN_RESET)
8002d2c: 787b ldrb r3, [r7, #1]
8002d2e: 2b00 cmp r3, #0
8002d30: d003 beq.n 8002d3a <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = GPIO_Pin;
8002d32: 887a ldrh r2, [r7, #2]
8002d34: 687b ldr r3, [r7, #4]
8002d36: 619a str r2, [r3, #24]
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
}
}
8002d38: e003 b.n 8002d42 <HAL_GPIO_WritePin+0x26>
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
8002d3a: 887b ldrh r3, [r7, #2]
8002d3c: 041a lsls r2, r3, #16
8002d3e: 687b ldr r3, [r7, #4]
8002d40: 619a str r2, [r3, #24]
}
8002d42: bf00 nop
8002d44: 370c adds r7, #12
8002d46: 46bd mov sp, r7
8002d48: f85d 7b04 ldr.w r7, [sp], #4
8002d4c: 4770 bx lr
...
08002d50 <HAL_GPIO_EXTI_IRQHandler>:
* @brief This function handles EXTI interrupt request.
* @param GPIO_Pin Specifies the pins connected EXTI line
* @retval None
*/
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
{
8002d50: b580 push {r7, lr}
8002d52: b082 sub sp, #8
8002d54: af00 add r7, sp, #0
8002d56: 4603 mov r3, r0
8002d58: 80fb strh r3, [r7, #6]
/* EXTI line interrupt detected */
if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
8002d5a: 4b08 ldr r3, [pc, #32] ; (8002d7c <HAL_GPIO_EXTI_IRQHandler+0x2c>)
8002d5c: 695a ldr r2, [r3, #20]
8002d5e: 88fb ldrh r3, [r7, #6]
8002d60: 4013 ands r3, r2
8002d62: 2b00 cmp r3, #0
8002d64: d006 beq.n 8002d74 <HAL_GPIO_EXTI_IRQHandler+0x24>
{
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
8002d66: 4a05 ldr r2, [pc, #20] ; (8002d7c <HAL_GPIO_EXTI_IRQHandler+0x2c>)
8002d68: 88fb ldrh r3, [r7, #6]
8002d6a: 6153 str r3, [r2, #20]
HAL_GPIO_EXTI_Callback(GPIO_Pin);
8002d6c: 88fb ldrh r3, [r7, #6]
8002d6e: 4618 mov r0, r3
8002d70: f000 f806 bl 8002d80 <HAL_GPIO_EXTI_Callback>
}
}
8002d74: bf00 nop
8002d76: 3708 adds r7, #8
8002d78: 46bd mov sp, r7
8002d7a: bd80 pop {r7, pc}
8002d7c: 40013c00 .word 0x40013c00
08002d80 <HAL_GPIO_EXTI_Callback>:
* @brief EXTI line detection callbacks.
* @param GPIO_Pin Specifies the pins connected EXTI line
* @retval None
*/
__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
{
8002d80: b480 push {r7}
8002d82: b083 sub sp, #12
8002d84: af00 add r7, sp, #0
8002d86: 4603 mov r3, r0
8002d88: 80fb strh r3, [r7, #6]
/* Prevent unused argument(s) compilation warning */
UNUSED(GPIO_Pin);
/* NOTE: This function Should not be modified, when the callback is needed,
the HAL_GPIO_EXTI_Callback could be implemented in the user file
*/
}
8002d8a: bf00 nop
8002d8c: 370c adds r7, #12
8002d8e: 46bd mov sp, r7
8002d90: f85d 7b04 ldr.w r7, [sp], #4
8002d94: 4770 bx lr
...
08002d98 <HAL_RCC_OscConfig>:
* supported by this API. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8002d98: b580 push {r7, lr}
8002d9a: b086 sub sp, #24
8002d9c: af00 add r7, sp, #0
8002d9e: 6078 str r0, [r7, #4]
uint32_t tickstart, pll_config;
/* Check Null pointer */
if(RCC_OscInitStruct == NULL)
8002da0: 687b ldr r3, [r7, #4]
8002da2: 2b00 cmp r3, #0
8002da4: d101 bne.n 8002daa <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
8002da6: 2301 movs r3, #1
8002da8: e25b b.n 8003262 <HAL_RCC_OscConfig+0x4ca>
}
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
8002daa: 687b ldr r3, [r7, #4]
8002dac: 681b ldr r3, [r3, #0]
8002dae: f003 0301 and.w r3, r3, #1
8002db2: 2b00 cmp r3, #0
8002db4: d075 beq.n 8002ea2 <HAL_RCC_OscConfig+0x10a>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
8002db6: 4ba3 ldr r3, [pc, #652] ; (8003044 <HAL_RCC_OscConfig+0x2ac>)
8002db8: 689b ldr r3, [r3, #8]
8002dba: f003 030c and.w r3, r3, #12
8002dbe: 2b04 cmp r3, #4
8002dc0: d00c beq.n 8002ddc <HAL_RCC_OscConfig+0x44>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
8002dc2: 4ba0 ldr r3, [pc, #640] ; (8003044 <HAL_RCC_OscConfig+0x2ac>)
8002dc4: 689b ldr r3, [r3, #8]
8002dc6: f003 030c and.w r3, r3, #12
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
8002dca: 2b08 cmp r3, #8
8002dcc: d112 bne.n 8002df4 <HAL_RCC_OscConfig+0x5c>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
8002dce: 4b9d ldr r3, [pc, #628] ; (8003044 <HAL_RCC_OscConfig+0x2ac>)
8002dd0: 685b ldr r3, [r3, #4]
8002dd2: f403 0380 and.w r3, r3, #4194304 ; 0x400000
8002dd6: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
8002dda: d10b bne.n 8002df4 <HAL_RCC_OscConfig+0x5c>
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8002ddc: 4b99 ldr r3, [pc, #612] ; (8003044 <HAL_RCC_OscConfig+0x2ac>)
8002dde: 681b ldr r3, [r3, #0]
8002de0: f403 3300 and.w r3, r3, #131072 ; 0x20000
8002de4: 2b00 cmp r3, #0
8002de6: d05b beq.n 8002ea0 <HAL_RCC_OscConfig+0x108>
8002de8: 687b ldr r3, [r7, #4]
8002dea: 685b ldr r3, [r3, #4]
8002dec: 2b00 cmp r3, #0
8002dee: d157 bne.n 8002ea0 <HAL_RCC_OscConfig+0x108>
{
return HAL_ERROR;
8002df0: 2301 movs r3, #1
8002df2: e236 b.n 8003262 <HAL_RCC_OscConfig+0x4ca>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8002df4: 687b ldr r3, [r7, #4]
8002df6: 685b ldr r3, [r3, #4]
8002df8: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8002dfc: d106 bne.n 8002e0c <HAL_RCC_OscConfig+0x74>
8002dfe: 4b91 ldr r3, [pc, #580] ; (8003044 <HAL_RCC_OscConfig+0x2ac>)
8002e00: 681b ldr r3, [r3, #0]
8002e02: 4a90 ldr r2, [pc, #576] ; (8003044 <HAL_RCC_OscConfig+0x2ac>)
8002e04: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8002e08: 6013 str r3, [r2, #0]
8002e0a: e01d b.n 8002e48 <HAL_RCC_OscConfig+0xb0>
8002e0c: 687b ldr r3, [r7, #4]
8002e0e: 685b ldr r3, [r3, #4]
8002e10: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
8002e14: d10c bne.n 8002e30 <HAL_RCC_OscConfig+0x98>
8002e16: 4b8b ldr r3, [pc, #556] ; (8003044 <HAL_RCC_OscConfig+0x2ac>)
8002e18: 681b ldr r3, [r3, #0]
8002e1a: 4a8a ldr r2, [pc, #552] ; (8003044 <HAL_RCC_OscConfig+0x2ac>)
8002e1c: f443 2380 orr.w r3, r3, #262144 ; 0x40000
8002e20: 6013 str r3, [r2, #0]
8002e22: 4b88 ldr r3, [pc, #544] ; (8003044 <HAL_RCC_OscConfig+0x2ac>)
8002e24: 681b ldr r3, [r3, #0]
8002e26: 4a87 ldr r2, [pc, #540] ; (8003044 <HAL_RCC_OscConfig+0x2ac>)
8002e28: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8002e2c: 6013 str r3, [r2, #0]
8002e2e: e00b b.n 8002e48 <HAL_RCC_OscConfig+0xb0>
8002e30: 4b84 ldr r3, [pc, #528] ; (8003044 <HAL_RCC_OscConfig+0x2ac>)
8002e32: 681b ldr r3, [r3, #0]
8002e34: 4a83 ldr r2, [pc, #524] ; (8003044 <HAL_RCC_OscConfig+0x2ac>)
8002e36: f423 3380 bic.w r3, r3, #65536 ; 0x10000
8002e3a: 6013 str r3, [r2, #0]
8002e3c: 4b81 ldr r3, [pc, #516] ; (8003044 <HAL_RCC_OscConfig+0x2ac>)
8002e3e: 681b ldr r3, [r3, #0]
8002e40: 4a80 ldr r2, [pc, #512] ; (8003044 <HAL_RCC_OscConfig+0x2ac>)
8002e42: f423 2380 bic.w r3, r3, #262144 ; 0x40000
8002e46: 6013 str r3, [r2, #0]
/* Check the HSE State */
if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
8002e48: 687b ldr r3, [r7, #4]
8002e4a: 685b ldr r3, [r3, #4]
8002e4c: 2b00 cmp r3, #0
8002e4e: d013 beq.n 8002e78 <HAL_RCC_OscConfig+0xe0>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8002e50: f7ff f88e bl 8001f70 <HAL_GetTick>
8002e54: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8002e56: e008 b.n 8002e6a <HAL_RCC_OscConfig+0xd2>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
8002e58: f7ff f88a bl 8001f70 <HAL_GetTick>
8002e5c: 4602 mov r2, r0
8002e5e: 693b ldr r3, [r7, #16]
8002e60: 1ad3 subs r3, r2, r3
8002e62: 2b64 cmp r3, #100 ; 0x64
8002e64: d901 bls.n 8002e6a <HAL_RCC_OscConfig+0xd2>
{
return HAL_TIMEOUT;
8002e66: 2303 movs r3, #3
8002e68: e1fb b.n 8003262 <HAL_RCC_OscConfig+0x4ca>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8002e6a: 4b76 ldr r3, [pc, #472] ; (8003044 <HAL_RCC_OscConfig+0x2ac>)
8002e6c: 681b ldr r3, [r3, #0]
8002e6e: f403 3300 and.w r3, r3, #131072 ; 0x20000
8002e72: 2b00 cmp r3, #0
8002e74: d0f0 beq.n 8002e58 <HAL_RCC_OscConfig+0xc0>
8002e76: e014 b.n 8002ea2 <HAL_RCC_OscConfig+0x10a>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8002e78: f7ff f87a bl 8001f70 <HAL_GetTick>
8002e7c: 6138 str r0, [r7, #16]
/* Wait till HSE is bypassed or disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8002e7e: e008 b.n 8002e92 <HAL_RCC_OscConfig+0xfa>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
8002e80: f7ff f876 bl 8001f70 <HAL_GetTick>
8002e84: 4602 mov r2, r0
8002e86: 693b ldr r3, [r7, #16]
8002e88: 1ad3 subs r3, r2, r3
8002e8a: 2b64 cmp r3, #100 ; 0x64
8002e8c: d901 bls.n 8002e92 <HAL_RCC_OscConfig+0xfa>
{
return HAL_TIMEOUT;
8002e8e: 2303 movs r3, #3
8002e90: e1e7 b.n 8003262 <HAL_RCC_OscConfig+0x4ca>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8002e92: 4b6c ldr r3, [pc, #432] ; (8003044 <HAL_RCC_OscConfig+0x2ac>)
8002e94: 681b ldr r3, [r3, #0]
8002e96: f403 3300 and.w r3, r3, #131072 ; 0x20000
8002e9a: 2b00 cmp r3, #0
8002e9c: d1f0 bne.n 8002e80 <HAL_RCC_OscConfig+0xe8>
8002e9e: e000 b.n 8002ea2 <HAL_RCC_OscConfig+0x10a>
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8002ea0: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
8002ea2: 687b ldr r3, [r7, #4]
8002ea4: 681b ldr r3, [r3, #0]
8002ea6: f003 0302 and.w r3, r3, #2
8002eaa: 2b00 cmp r3, #0
8002eac: d063 beq.n 8002f76 <HAL_RCC_OscConfig+0x1de>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
8002eae: 4b65 ldr r3, [pc, #404] ; (8003044 <HAL_RCC_OscConfig+0x2ac>)
8002eb0: 689b ldr r3, [r3, #8]
8002eb2: f003 030c and.w r3, r3, #12
8002eb6: 2b00 cmp r3, #0
8002eb8: d00b beq.n 8002ed2 <HAL_RCC_OscConfig+0x13a>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
8002eba: 4b62 ldr r3, [pc, #392] ; (8003044 <HAL_RCC_OscConfig+0x2ac>)
8002ebc: 689b ldr r3, [r3, #8]
8002ebe: f003 030c and.w r3, r3, #12
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
8002ec2: 2b08 cmp r3, #8
8002ec4: d11c bne.n 8002f00 <HAL_RCC_OscConfig+0x168>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
8002ec6: 4b5f ldr r3, [pc, #380] ; (8003044 <HAL_RCC_OscConfig+0x2ac>)
8002ec8: 685b ldr r3, [r3, #4]
8002eca: f403 0380 and.w r3, r3, #4194304 ; 0x400000
8002ece: 2b00 cmp r3, #0
8002ed0: d116 bne.n 8002f00 <HAL_RCC_OscConfig+0x168>
{
/* When HSI is used as system clock it will not disabled */
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8002ed2: 4b5c ldr r3, [pc, #368] ; (8003044 <HAL_RCC_OscConfig+0x2ac>)
8002ed4: 681b ldr r3, [r3, #0]
8002ed6: f003 0302 and.w r3, r3, #2
8002eda: 2b00 cmp r3, #0
8002edc: d005 beq.n 8002eea <HAL_RCC_OscConfig+0x152>
8002ede: 687b ldr r3, [r7, #4]
8002ee0: 68db ldr r3, [r3, #12]
8002ee2: 2b01 cmp r3, #1
8002ee4: d001 beq.n 8002eea <HAL_RCC_OscConfig+0x152>
{
return HAL_ERROR;
8002ee6: 2301 movs r3, #1
8002ee8: e1bb b.n 8003262 <HAL_RCC_OscConfig+0x4ca>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8002eea: 4b56 ldr r3, [pc, #344] ; (8003044 <HAL_RCC_OscConfig+0x2ac>)
8002eec: 681b ldr r3, [r3, #0]
8002eee: f023 02f8 bic.w r2, r3, #248 ; 0xf8
8002ef2: 687b ldr r3, [r7, #4]
8002ef4: 691b ldr r3, [r3, #16]
8002ef6: 00db lsls r3, r3, #3
8002ef8: 4952 ldr r1, [pc, #328] ; (8003044 <HAL_RCC_OscConfig+0x2ac>)
8002efa: 4313 orrs r3, r2
8002efc: 600b str r3, [r1, #0]
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8002efe: e03a b.n 8002f76 <HAL_RCC_OscConfig+0x1de>
}
}
else
{
/* Check the HSI State */
if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
8002f00: 687b ldr r3, [r7, #4]
8002f02: 68db ldr r3, [r3, #12]
8002f04: 2b00 cmp r3, #0
8002f06: d020 beq.n 8002f4a <HAL_RCC_OscConfig+0x1b2>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8002f08: 4b4f ldr r3, [pc, #316] ; (8003048 <HAL_RCC_OscConfig+0x2b0>)
8002f0a: 2201 movs r2, #1
8002f0c: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002f0e: f7ff f82f bl 8001f70 <HAL_GetTick>
8002f12: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8002f14: e008 b.n 8002f28 <HAL_RCC_OscConfig+0x190>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
8002f16: f7ff f82b bl 8001f70 <HAL_GetTick>
8002f1a: 4602 mov r2, r0
8002f1c: 693b ldr r3, [r7, #16]
8002f1e: 1ad3 subs r3, r2, r3
8002f20: 2b02 cmp r3, #2
8002f22: d901 bls.n 8002f28 <HAL_RCC_OscConfig+0x190>
{
return HAL_TIMEOUT;
8002f24: 2303 movs r3, #3
8002f26: e19c b.n 8003262 <HAL_RCC_OscConfig+0x4ca>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8002f28: 4b46 ldr r3, [pc, #280] ; (8003044 <HAL_RCC_OscConfig+0x2ac>)
8002f2a: 681b ldr r3, [r3, #0]
8002f2c: f003 0302 and.w r3, r3, #2
8002f30: 2b00 cmp r3, #0
8002f32: d0f0 beq.n 8002f16 <HAL_RCC_OscConfig+0x17e>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value. */
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8002f34: 4b43 ldr r3, [pc, #268] ; (8003044 <HAL_RCC_OscConfig+0x2ac>)
8002f36: 681b ldr r3, [r3, #0]
8002f38: f023 02f8 bic.w r2, r3, #248 ; 0xf8
8002f3c: 687b ldr r3, [r7, #4]
8002f3e: 691b ldr r3, [r3, #16]
8002f40: 00db lsls r3, r3, #3
8002f42: 4940 ldr r1, [pc, #256] ; (8003044 <HAL_RCC_OscConfig+0x2ac>)
8002f44: 4313 orrs r3, r2
8002f46: 600b str r3, [r1, #0]
8002f48: e015 b.n 8002f76 <HAL_RCC_OscConfig+0x1de>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
8002f4a: 4b3f ldr r3, [pc, #252] ; (8003048 <HAL_RCC_OscConfig+0x2b0>)
8002f4c: 2200 movs r2, #0
8002f4e: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002f50: f7ff f80e bl 8001f70 <HAL_GetTick>
8002f54: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8002f56: e008 b.n 8002f6a <HAL_RCC_OscConfig+0x1d2>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
8002f58: f7ff f80a bl 8001f70 <HAL_GetTick>
8002f5c: 4602 mov r2, r0
8002f5e: 693b ldr r3, [r7, #16]
8002f60: 1ad3 subs r3, r2, r3
8002f62: 2b02 cmp r3, #2
8002f64: d901 bls.n 8002f6a <HAL_RCC_OscConfig+0x1d2>
{
return HAL_TIMEOUT;
8002f66: 2303 movs r3, #3
8002f68: e17b b.n 8003262 <HAL_RCC_OscConfig+0x4ca>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8002f6a: 4b36 ldr r3, [pc, #216] ; (8003044 <HAL_RCC_OscConfig+0x2ac>)
8002f6c: 681b ldr r3, [r3, #0]
8002f6e: f003 0302 and.w r3, r3, #2
8002f72: 2b00 cmp r3, #0
8002f74: d1f0 bne.n 8002f58 <HAL_RCC_OscConfig+0x1c0>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
8002f76: 687b ldr r3, [r7, #4]
8002f78: 681b ldr r3, [r3, #0]
8002f7a: f003 0308 and.w r3, r3, #8
8002f7e: 2b00 cmp r3, #0
8002f80: d030 beq.n 8002fe4 <HAL_RCC_OscConfig+0x24c>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
8002f82: 687b ldr r3, [r7, #4]
8002f84: 695b ldr r3, [r3, #20]
8002f86: 2b00 cmp r3, #0
8002f88: d016 beq.n 8002fb8 <HAL_RCC_OscConfig+0x220>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8002f8a: 4b30 ldr r3, [pc, #192] ; (800304c <HAL_RCC_OscConfig+0x2b4>)
8002f8c: 2201 movs r2, #1
8002f8e: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002f90: f7fe ffee bl 8001f70 <HAL_GetTick>
8002f94: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8002f96: e008 b.n 8002faa <HAL_RCC_OscConfig+0x212>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
8002f98: f7fe ffea bl 8001f70 <HAL_GetTick>
8002f9c: 4602 mov r2, r0
8002f9e: 693b ldr r3, [r7, #16]
8002fa0: 1ad3 subs r3, r2, r3
8002fa2: 2b02 cmp r3, #2
8002fa4: d901 bls.n 8002faa <HAL_RCC_OscConfig+0x212>
{
return HAL_TIMEOUT;
8002fa6: 2303 movs r3, #3
8002fa8: e15b b.n 8003262 <HAL_RCC_OscConfig+0x4ca>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8002faa: 4b26 ldr r3, [pc, #152] ; (8003044 <HAL_RCC_OscConfig+0x2ac>)
8002fac: 6f5b ldr r3, [r3, #116] ; 0x74
8002fae: f003 0302 and.w r3, r3, #2
8002fb2: 2b00 cmp r3, #0
8002fb4: d0f0 beq.n 8002f98 <HAL_RCC_OscConfig+0x200>
8002fb6: e015 b.n 8002fe4 <HAL_RCC_OscConfig+0x24c>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8002fb8: 4b24 ldr r3, [pc, #144] ; (800304c <HAL_RCC_OscConfig+0x2b4>)
8002fba: 2200 movs r2, #0
8002fbc: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8002fbe: f7fe ffd7 bl 8001f70 <HAL_GetTick>
8002fc2: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8002fc4: e008 b.n 8002fd8 <HAL_RCC_OscConfig+0x240>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
8002fc6: f7fe ffd3 bl 8001f70 <HAL_GetTick>
8002fca: 4602 mov r2, r0
8002fcc: 693b ldr r3, [r7, #16]
8002fce: 1ad3 subs r3, r2, r3
8002fd0: 2b02 cmp r3, #2
8002fd2: d901 bls.n 8002fd8 <HAL_RCC_OscConfig+0x240>
{
return HAL_TIMEOUT;
8002fd4: 2303 movs r3, #3
8002fd6: e144 b.n 8003262 <HAL_RCC_OscConfig+0x4ca>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8002fd8: 4b1a ldr r3, [pc, #104] ; (8003044 <HAL_RCC_OscConfig+0x2ac>)
8002fda: 6f5b ldr r3, [r3, #116] ; 0x74
8002fdc: f003 0302 and.w r3, r3, #2
8002fe0: 2b00 cmp r3, #0
8002fe2: d1f0 bne.n 8002fc6 <HAL_RCC_OscConfig+0x22e>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8002fe4: 687b ldr r3, [r7, #4]
8002fe6: 681b ldr r3, [r3, #0]
8002fe8: f003 0304 and.w r3, r3, #4
8002fec: 2b00 cmp r3, #0
8002fee: f000 80a0 beq.w 8003132 <HAL_RCC_OscConfig+0x39a>
{
FlagStatus pwrclkchanged = RESET;
8002ff2: 2300 movs r3, #0
8002ff4: 75fb strb r3, [r7, #23]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
8002ff6: 4b13 ldr r3, [pc, #76] ; (8003044 <HAL_RCC_OscConfig+0x2ac>)
8002ff8: 6c1b ldr r3, [r3, #64] ; 0x40
8002ffa: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8002ffe: 2b00 cmp r3, #0
8003000: d10f bne.n 8003022 <HAL_RCC_OscConfig+0x28a>
{
__HAL_RCC_PWR_CLK_ENABLE();
8003002: 2300 movs r3, #0
8003004: 60bb str r3, [r7, #8]
8003006: 4b0f ldr r3, [pc, #60] ; (8003044 <HAL_RCC_OscConfig+0x2ac>)
8003008: 6c1b ldr r3, [r3, #64] ; 0x40
800300a: 4a0e ldr r2, [pc, #56] ; (8003044 <HAL_RCC_OscConfig+0x2ac>)
800300c: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8003010: 6413 str r3, [r2, #64] ; 0x40
8003012: 4b0c ldr r3, [pc, #48] ; (8003044 <HAL_RCC_OscConfig+0x2ac>)
8003014: 6c1b ldr r3, [r3, #64] ; 0x40
8003016: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
800301a: 60bb str r3, [r7, #8]
800301c: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
800301e: 2301 movs r3, #1
8003020: 75fb strb r3, [r7, #23]
}
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8003022: 4b0b ldr r3, [pc, #44] ; (8003050 <HAL_RCC_OscConfig+0x2b8>)
8003024: 681b ldr r3, [r3, #0]
8003026: f403 7380 and.w r3, r3, #256 ; 0x100
800302a: 2b00 cmp r3, #0
800302c: d121 bne.n 8003072 <HAL_RCC_OscConfig+0x2da>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
800302e: 4b08 ldr r3, [pc, #32] ; (8003050 <HAL_RCC_OscConfig+0x2b8>)
8003030: 681b ldr r3, [r3, #0]
8003032: 4a07 ldr r2, [pc, #28] ; (8003050 <HAL_RCC_OscConfig+0x2b8>)
8003034: f443 7380 orr.w r3, r3, #256 ; 0x100
8003038: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
800303a: f7fe ff99 bl 8001f70 <HAL_GetTick>
800303e: 6138 str r0, [r7, #16]
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8003040: e011 b.n 8003066 <HAL_RCC_OscConfig+0x2ce>
8003042: bf00 nop
8003044: 40023800 .word 0x40023800
8003048: 42470000 .word 0x42470000
800304c: 42470e80 .word 0x42470e80
8003050: 40007000 .word 0x40007000
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8003054: f7fe ff8c bl 8001f70 <HAL_GetTick>
8003058: 4602 mov r2, r0
800305a: 693b ldr r3, [r7, #16]
800305c: 1ad3 subs r3, r2, r3
800305e: 2b02 cmp r3, #2
8003060: d901 bls.n 8003066 <HAL_RCC_OscConfig+0x2ce>
{
return HAL_TIMEOUT;
8003062: 2303 movs r3, #3
8003064: e0fd b.n 8003262 <HAL_RCC_OscConfig+0x4ca>
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8003066: 4b81 ldr r3, [pc, #516] ; (800326c <HAL_RCC_OscConfig+0x4d4>)
8003068: 681b ldr r3, [r3, #0]
800306a: f403 7380 and.w r3, r3, #256 ; 0x100
800306e: 2b00 cmp r3, #0
8003070: d0f0 beq.n 8003054 <HAL_RCC_OscConfig+0x2bc>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8003072: 687b ldr r3, [r7, #4]
8003074: 689b ldr r3, [r3, #8]
8003076: 2b01 cmp r3, #1
8003078: d106 bne.n 8003088 <HAL_RCC_OscConfig+0x2f0>
800307a: 4b7d ldr r3, [pc, #500] ; (8003270 <HAL_RCC_OscConfig+0x4d8>)
800307c: 6f1b ldr r3, [r3, #112] ; 0x70
800307e: 4a7c ldr r2, [pc, #496] ; (8003270 <HAL_RCC_OscConfig+0x4d8>)
8003080: f043 0301 orr.w r3, r3, #1
8003084: 6713 str r3, [r2, #112] ; 0x70
8003086: e01c b.n 80030c2 <HAL_RCC_OscConfig+0x32a>
8003088: 687b ldr r3, [r7, #4]
800308a: 689b ldr r3, [r3, #8]
800308c: 2b05 cmp r3, #5
800308e: d10c bne.n 80030aa <HAL_RCC_OscConfig+0x312>
8003090: 4b77 ldr r3, [pc, #476] ; (8003270 <HAL_RCC_OscConfig+0x4d8>)
8003092: 6f1b ldr r3, [r3, #112] ; 0x70
8003094: 4a76 ldr r2, [pc, #472] ; (8003270 <HAL_RCC_OscConfig+0x4d8>)
8003096: f043 0304 orr.w r3, r3, #4
800309a: 6713 str r3, [r2, #112] ; 0x70
800309c: 4b74 ldr r3, [pc, #464] ; (8003270 <HAL_RCC_OscConfig+0x4d8>)
800309e: 6f1b ldr r3, [r3, #112] ; 0x70
80030a0: 4a73 ldr r2, [pc, #460] ; (8003270 <HAL_RCC_OscConfig+0x4d8>)
80030a2: f043 0301 orr.w r3, r3, #1
80030a6: 6713 str r3, [r2, #112] ; 0x70
80030a8: e00b b.n 80030c2 <HAL_RCC_OscConfig+0x32a>
80030aa: 4b71 ldr r3, [pc, #452] ; (8003270 <HAL_RCC_OscConfig+0x4d8>)
80030ac: 6f1b ldr r3, [r3, #112] ; 0x70
80030ae: 4a70 ldr r2, [pc, #448] ; (8003270 <HAL_RCC_OscConfig+0x4d8>)
80030b0: f023 0301 bic.w r3, r3, #1
80030b4: 6713 str r3, [r2, #112] ; 0x70
80030b6: 4b6e ldr r3, [pc, #440] ; (8003270 <HAL_RCC_OscConfig+0x4d8>)
80030b8: 6f1b ldr r3, [r3, #112] ; 0x70
80030ba: 4a6d ldr r2, [pc, #436] ; (8003270 <HAL_RCC_OscConfig+0x4d8>)
80030bc: f023 0304 bic.w r3, r3, #4
80030c0: 6713 str r3, [r2, #112] ; 0x70
/* Check the LSE State */
if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
80030c2: 687b ldr r3, [r7, #4]
80030c4: 689b ldr r3, [r3, #8]
80030c6: 2b00 cmp r3, #0
80030c8: d015 beq.n 80030f6 <HAL_RCC_OscConfig+0x35e>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
80030ca: f7fe ff51 bl 8001f70 <HAL_GetTick>
80030ce: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
80030d0: e00a b.n 80030e8 <HAL_RCC_OscConfig+0x350>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
80030d2: f7fe ff4d bl 8001f70 <HAL_GetTick>
80030d6: 4602 mov r2, r0
80030d8: 693b ldr r3, [r7, #16]
80030da: 1ad3 subs r3, r2, r3
80030dc: f241 3288 movw r2, #5000 ; 0x1388
80030e0: 4293 cmp r3, r2
80030e2: d901 bls.n 80030e8 <HAL_RCC_OscConfig+0x350>
{
return HAL_TIMEOUT;
80030e4: 2303 movs r3, #3
80030e6: e0bc b.n 8003262 <HAL_RCC_OscConfig+0x4ca>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
80030e8: 4b61 ldr r3, [pc, #388] ; (8003270 <HAL_RCC_OscConfig+0x4d8>)
80030ea: 6f1b ldr r3, [r3, #112] ; 0x70
80030ec: f003 0302 and.w r3, r3, #2
80030f0: 2b00 cmp r3, #0
80030f2: d0ee beq.n 80030d2 <HAL_RCC_OscConfig+0x33a>
80030f4: e014 b.n 8003120 <HAL_RCC_OscConfig+0x388>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
80030f6: f7fe ff3b bl 8001f70 <HAL_GetTick>
80030fa: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
80030fc: e00a b.n 8003114 <HAL_RCC_OscConfig+0x37c>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
80030fe: f7fe ff37 bl 8001f70 <HAL_GetTick>
8003102: 4602 mov r2, r0
8003104: 693b ldr r3, [r7, #16]
8003106: 1ad3 subs r3, r2, r3
8003108: f241 3288 movw r2, #5000 ; 0x1388
800310c: 4293 cmp r3, r2
800310e: d901 bls.n 8003114 <HAL_RCC_OscConfig+0x37c>
{
return HAL_TIMEOUT;
8003110: 2303 movs r3, #3
8003112: e0a6 b.n 8003262 <HAL_RCC_OscConfig+0x4ca>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8003114: 4b56 ldr r3, [pc, #344] ; (8003270 <HAL_RCC_OscConfig+0x4d8>)
8003116: 6f1b ldr r3, [r3, #112] ; 0x70
8003118: f003 0302 and.w r3, r3, #2
800311c: 2b00 cmp r3, #0
800311e: d1ee bne.n 80030fe <HAL_RCC_OscConfig+0x366>
}
}
}
/* Restore clock configuration if changed */
if(pwrclkchanged == SET)
8003120: 7dfb ldrb r3, [r7, #23]
8003122: 2b01 cmp r3, #1
8003124: d105 bne.n 8003132 <HAL_RCC_OscConfig+0x39a>
{
__HAL_RCC_PWR_CLK_DISABLE();
8003126: 4b52 ldr r3, [pc, #328] ; (8003270 <HAL_RCC_OscConfig+0x4d8>)
8003128: 6c1b ldr r3, [r3, #64] ; 0x40
800312a: 4a51 ldr r2, [pc, #324] ; (8003270 <HAL_RCC_OscConfig+0x4d8>)
800312c: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
8003130: 6413 str r3, [r2, #64] ; 0x40
}
}
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
8003132: 687b ldr r3, [r7, #4]
8003134: 699b ldr r3, [r3, #24]
8003136: 2b00 cmp r3, #0
8003138: f000 8092 beq.w 8003260 <HAL_RCC_OscConfig+0x4c8>
{
/* Check if the PLL is used as system clock or not */
if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
800313c: 4b4c ldr r3, [pc, #304] ; (8003270 <HAL_RCC_OscConfig+0x4d8>)
800313e: 689b ldr r3, [r3, #8]
8003140: f003 030c and.w r3, r3, #12
8003144: 2b08 cmp r3, #8
8003146: d05c beq.n 8003202 <HAL_RCC_OscConfig+0x46a>
{
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
8003148: 687b ldr r3, [r7, #4]
800314a: 699b ldr r3, [r3, #24]
800314c: 2b02 cmp r3, #2
800314e: d141 bne.n 80031d4 <HAL_RCC_OscConfig+0x43c>
assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8003150: 4b48 ldr r3, [pc, #288] ; (8003274 <HAL_RCC_OscConfig+0x4dc>)
8003152: 2200 movs r2, #0
8003154: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8003156: f7fe ff0b bl 8001f70 <HAL_GetTick>
800315a: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
800315c: e008 b.n 8003170 <HAL_RCC_OscConfig+0x3d8>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
800315e: f7fe ff07 bl 8001f70 <HAL_GetTick>
8003162: 4602 mov r2, r0
8003164: 693b ldr r3, [r7, #16]
8003166: 1ad3 subs r3, r2, r3
8003168: 2b02 cmp r3, #2
800316a: d901 bls.n 8003170 <HAL_RCC_OscConfig+0x3d8>
{
return HAL_TIMEOUT;
800316c: 2303 movs r3, #3
800316e: e078 b.n 8003262 <HAL_RCC_OscConfig+0x4ca>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8003170: 4b3f ldr r3, [pc, #252] ; (8003270 <HAL_RCC_OscConfig+0x4d8>)
8003172: 681b ldr r3, [r3, #0]
8003174: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8003178: 2b00 cmp r3, #0
800317a: d1f0 bne.n 800315e <HAL_RCC_OscConfig+0x3c6>
}
}
/* Configure the main PLL clock source, multiplication and division factors. */
WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \
800317c: 687b ldr r3, [r7, #4]
800317e: 69da ldr r2, [r3, #28]
8003180: 687b ldr r3, [r7, #4]
8003182: 6a1b ldr r3, [r3, #32]
8003184: 431a orrs r2, r3
8003186: 687b ldr r3, [r7, #4]
8003188: 6a5b ldr r3, [r3, #36] ; 0x24
800318a: 019b lsls r3, r3, #6
800318c: 431a orrs r2, r3
800318e: 687b ldr r3, [r7, #4]
8003190: 6a9b ldr r3, [r3, #40] ; 0x28
8003192: 085b lsrs r3, r3, #1
8003194: 3b01 subs r3, #1
8003196: 041b lsls r3, r3, #16
8003198: 431a orrs r2, r3
800319a: 687b ldr r3, [r7, #4]
800319c: 6adb ldr r3, [r3, #44] ; 0x2c
800319e: 061b lsls r3, r3, #24
80031a0: 4933 ldr r1, [pc, #204] ; (8003270 <HAL_RCC_OscConfig+0x4d8>)
80031a2: 4313 orrs r3, r2
80031a4: 604b str r3, [r1, #4]
RCC_OscInitStruct->PLL.PLLM | \
(RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \
(((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \
(RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)));
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
80031a6: 4b33 ldr r3, [pc, #204] ; (8003274 <HAL_RCC_OscConfig+0x4dc>)
80031a8: 2201 movs r2, #1
80031aa: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80031ac: f7fe fee0 bl 8001f70 <HAL_GetTick>
80031b0: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
80031b2: e008 b.n 80031c6 <HAL_RCC_OscConfig+0x42e>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
80031b4: f7fe fedc bl 8001f70 <HAL_GetTick>
80031b8: 4602 mov r2, r0
80031ba: 693b ldr r3, [r7, #16]
80031bc: 1ad3 subs r3, r2, r3
80031be: 2b02 cmp r3, #2
80031c0: d901 bls.n 80031c6 <HAL_RCC_OscConfig+0x42e>
{
return HAL_TIMEOUT;
80031c2: 2303 movs r3, #3
80031c4: e04d b.n 8003262 <HAL_RCC_OscConfig+0x4ca>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
80031c6: 4b2a ldr r3, [pc, #168] ; (8003270 <HAL_RCC_OscConfig+0x4d8>)
80031c8: 681b ldr r3, [r3, #0]
80031ca: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
80031ce: 2b00 cmp r3, #0
80031d0: d0f0 beq.n 80031b4 <HAL_RCC_OscConfig+0x41c>
80031d2: e045 b.n 8003260 <HAL_RCC_OscConfig+0x4c8>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
80031d4: 4b27 ldr r3, [pc, #156] ; (8003274 <HAL_RCC_OscConfig+0x4dc>)
80031d6: 2200 movs r2, #0
80031d8: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80031da: f7fe fec9 bl 8001f70 <HAL_GetTick>
80031de: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80031e0: e008 b.n 80031f4 <HAL_RCC_OscConfig+0x45c>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
80031e2: f7fe fec5 bl 8001f70 <HAL_GetTick>
80031e6: 4602 mov r2, r0
80031e8: 693b ldr r3, [r7, #16]
80031ea: 1ad3 subs r3, r2, r3
80031ec: 2b02 cmp r3, #2
80031ee: d901 bls.n 80031f4 <HAL_RCC_OscConfig+0x45c>
{
return HAL_TIMEOUT;
80031f0: 2303 movs r3, #3
80031f2: e036 b.n 8003262 <HAL_RCC_OscConfig+0x4ca>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80031f4: 4b1e ldr r3, [pc, #120] ; (8003270 <HAL_RCC_OscConfig+0x4d8>)
80031f6: 681b ldr r3, [r3, #0]
80031f8: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
80031fc: 2b00 cmp r3, #0
80031fe: d1f0 bne.n 80031e2 <HAL_RCC_OscConfig+0x44a>
8003200: e02e b.n 8003260 <HAL_RCC_OscConfig+0x4c8>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
8003202: 687b ldr r3, [r7, #4]
8003204: 699b ldr r3, [r3, #24]
8003206: 2b01 cmp r3, #1
8003208: d101 bne.n 800320e <HAL_RCC_OscConfig+0x476>
{
return HAL_ERROR;
800320a: 2301 movs r3, #1
800320c: e029 b.n 8003262 <HAL_RCC_OscConfig+0x4ca>
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->PLLCFGR;
800320e: 4b18 ldr r3, [pc, #96] ; (8003270 <HAL_RCC_OscConfig+0x4d8>)
8003210: 685b ldr r3, [r3, #4]
8003212: 60fb str r3, [r7, #12]
if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8003214: 68fb ldr r3, [r7, #12]
8003216: f403 0280 and.w r2, r3, #4194304 ; 0x400000
800321a: 687b ldr r3, [r7, #4]
800321c: 69db ldr r3, [r3, #28]
800321e: 429a cmp r2, r3
8003220: d11c bne.n 800325c <HAL_RCC_OscConfig+0x4c4>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
8003222: 68fb ldr r3, [r7, #12]
8003224: f003 023f and.w r2, r3, #63 ; 0x3f
8003228: 687b ldr r3, [r7, #4]
800322a: 6a1b ldr r3, [r3, #32]
if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
800322c: 429a cmp r2, r3
800322e: d115 bne.n 800325c <HAL_RCC_OscConfig+0x4c4>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != RCC_OscInitStruct->PLL.PLLN) ||
8003230: 68fa ldr r2, [r7, #12]
8003232: f647 73c0 movw r3, #32704 ; 0x7fc0
8003236: 4013 ands r3, r2
8003238: 687a ldr r2, [r7, #4]
800323a: 6a52 ldr r2, [r2, #36] ; 0x24
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
800323c: 4293 cmp r3, r2
800323e: d10d bne.n 800325c <HAL_RCC_OscConfig+0x4c4>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) ||
8003240: 68fb ldr r3, [r7, #12]
8003242: f403 3240 and.w r2, r3, #196608 ; 0x30000
8003246: 687b ldr r3, [r7, #4]
8003248: 6a9b ldr r3, [r3, #40] ; 0x28
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != RCC_OscInitStruct->PLL.PLLN) ||
800324a: 429a cmp r2, r3
800324c: d106 bne.n 800325c <HAL_RCC_OscConfig+0x4c4>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ))
800324e: 68fb ldr r3, [r7, #12]
8003250: f003 6270 and.w r2, r3, #251658240 ; 0xf000000
8003254: 687b ldr r3, [r7, #4]
8003256: 6adb ldr r3, [r3, #44] ; 0x2c
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) ||
8003258: 429a cmp r2, r3
800325a: d001 beq.n 8003260 <HAL_RCC_OscConfig+0x4c8>
{
return HAL_ERROR;
800325c: 2301 movs r3, #1
800325e: e000 b.n 8003262 <HAL_RCC_OscConfig+0x4ca>
}
}
}
}
return HAL_OK;
8003260: 2300 movs r3, #0
}
8003262: 4618 mov r0, r3
8003264: 3718 adds r7, #24
8003266: 46bd mov sp, r7
8003268: bd80 pop {r7, pc}
800326a: bf00 nop
800326c: 40007000 .word 0x40007000
8003270: 40023800 .word 0x40023800
8003274: 42470060 .word 0x42470060
08003278 <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval None
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8003278: b580 push {r7, lr}
800327a: b084 sub sp, #16
800327c: af00 add r7, sp, #0
800327e: 6078 str r0, [r7, #4]
8003280: 6039 str r1, [r7, #0]
uint32_t tickstart;
/* Check Null pointer */
if(RCC_ClkInitStruct == NULL)
8003282: 687b ldr r3, [r7, #4]
8003284: 2b00 cmp r3, #0
8003286: d101 bne.n 800328c <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
8003288: 2301 movs r3, #1
800328a: e0cc b.n 8003426 <HAL_RCC_ClockConfig+0x1ae>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if(FLatency > __HAL_FLASH_GET_LATENCY())
800328c: 4b68 ldr r3, [pc, #416] ; (8003430 <HAL_RCC_ClockConfig+0x1b8>)
800328e: 681b ldr r3, [r3, #0]
8003290: f003 030f and.w r3, r3, #15
8003294: 683a ldr r2, [r7, #0]
8003296: 429a cmp r2, r3
8003298: d90c bls.n 80032b4 <HAL_RCC_ClockConfig+0x3c>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
800329a: 4b65 ldr r3, [pc, #404] ; (8003430 <HAL_RCC_ClockConfig+0x1b8>)
800329c: 683a ldr r2, [r7, #0]
800329e: b2d2 uxtb r2, r2
80032a0: 701a strb r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
80032a2: 4b63 ldr r3, [pc, #396] ; (8003430 <HAL_RCC_ClockConfig+0x1b8>)
80032a4: 681b ldr r3, [r3, #0]
80032a6: f003 030f and.w r3, r3, #15
80032aa: 683a ldr r2, [r7, #0]
80032ac: 429a cmp r2, r3
80032ae: d001 beq.n 80032b4 <HAL_RCC_ClockConfig+0x3c>
{
return HAL_ERROR;
80032b0: 2301 movs r3, #1
80032b2: e0b8 b.n 8003426 <HAL_RCC_ClockConfig+0x1ae>
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
80032b4: 687b ldr r3, [r7, #4]
80032b6: 681b ldr r3, [r3, #0]
80032b8: f003 0302 and.w r3, r3, #2
80032bc: 2b00 cmp r3, #0
80032be: d020 beq.n 8003302 <HAL_RCC_ClockConfig+0x8a>
{
/* Set the highest APBx dividers in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
80032c0: 687b ldr r3, [r7, #4]
80032c2: 681b ldr r3, [r3, #0]
80032c4: f003 0304 and.w r3, r3, #4
80032c8: 2b00 cmp r3, #0
80032ca: d005 beq.n 80032d8 <HAL_RCC_ClockConfig+0x60>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
80032cc: 4b59 ldr r3, [pc, #356] ; (8003434 <HAL_RCC_ClockConfig+0x1bc>)
80032ce: 689b ldr r3, [r3, #8]
80032d0: 4a58 ldr r2, [pc, #352] ; (8003434 <HAL_RCC_ClockConfig+0x1bc>)
80032d2: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00
80032d6: 6093 str r3, [r2, #8]
}
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
80032d8: 687b ldr r3, [r7, #4]
80032da: 681b ldr r3, [r3, #0]
80032dc: f003 0308 and.w r3, r3, #8
80032e0: 2b00 cmp r3, #0
80032e2: d005 beq.n 80032f0 <HAL_RCC_ClockConfig+0x78>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
80032e4: 4b53 ldr r3, [pc, #332] ; (8003434 <HAL_RCC_ClockConfig+0x1bc>)
80032e6: 689b ldr r3, [r3, #8]
80032e8: 4a52 ldr r2, [pc, #328] ; (8003434 <HAL_RCC_ClockConfig+0x1bc>)
80032ea: f443 4360 orr.w r3, r3, #57344 ; 0xe000
80032ee: 6093 str r3, [r2, #8]
}
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
80032f0: 4b50 ldr r3, [pc, #320] ; (8003434 <HAL_RCC_ClockConfig+0x1bc>)
80032f2: 689b ldr r3, [r3, #8]
80032f4: f023 02f0 bic.w r2, r3, #240 ; 0xf0
80032f8: 687b ldr r3, [r7, #4]
80032fa: 689b ldr r3, [r3, #8]
80032fc: 494d ldr r1, [pc, #308] ; (8003434 <HAL_RCC_ClockConfig+0x1bc>)
80032fe: 4313 orrs r3, r2
8003300: 608b str r3, [r1, #8]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8003302: 687b ldr r3, [r7, #4]
8003304: 681b ldr r3, [r3, #0]
8003306: f003 0301 and.w r3, r3, #1
800330a: 2b00 cmp r3, #0
800330c: d044 beq.n 8003398 <HAL_RCC_ClockConfig+0x120>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
800330e: 687b ldr r3, [r7, #4]
8003310: 685b ldr r3, [r3, #4]
8003312: 2b01 cmp r3, #1
8003314: d107 bne.n 8003326 <HAL_RCC_ClockConfig+0xae>
{
/* Check the HSE ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8003316: 4b47 ldr r3, [pc, #284] ; (8003434 <HAL_RCC_ClockConfig+0x1bc>)
8003318: 681b ldr r3, [r3, #0]
800331a: f403 3300 and.w r3, r3, #131072 ; 0x20000
800331e: 2b00 cmp r3, #0
8003320: d119 bne.n 8003356 <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8003322: 2301 movs r3, #1
8003324: e07f b.n 8003426 <HAL_RCC_ClockConfig+0x1ae>
}
}
/* PLL is selected as System Clock Source */
else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
8003326: 687b ldr r3, [r7, #4]
8003328: 685b ldr r3, [r3, #4]
800332a: 2b02 cmp r3, #2
800332c: d003 beq.n 8003336 <HAL_RCC_ClockConfig+0xbe>
(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
800332e: 687b ldr r3, [r7, #4]
8003330: 685b ldr r3, [r3, #4]
else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
8003332: 2b03 cmp r3, #3
8003334: d107 bne.n 8003346 <HAL_RCC_ClockConfig+0xce>
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8003336: 4b3f ldr r3, [pc, #252] ; (8003434 <HAL_RCC_ClockConfig+0x1bc>)
8003338: 681b ldr r3, [r3, #0]
800333a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
800333e: 2b00 cmp r3, #0
8003340: d109 bne.n 8003356 <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8003342: 2301 movs r3, #1
8003344: e06f b.n 8003426 <HAL_RCC_ClockConfig+0x1ae>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8003346: 4b3b ldr r3, [pc, #236] ; (8003434 <HAL_RCC_ClockConfig+0x1bc>)
8003348: 681b ldr r3, [r3, #0]
800334a: f003 0302 and.w r3, r3, #2
800334e: 2b00 cmp r3, #0
8003350: d101 bne.n 8003356 <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8003352: 2301 movs r3, #1
8003354: e067 b.n 8003426 <HAL_RCC_ClockConfig+0x1ae>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
8003356: 4b37 ldr r3, [pc, #220] ; (8003434 <HAL_RCC_ClockConfig+0x1bc>)
8003358: 689b ldr r3, [r3, #8]
800335a: f023 0203 bic.w r2, r3, #3
800335e: 687b ldr r3, [r7, #4]
8003360: 685b ldr r3, [r3, #4]
8003362: 4934 ldr r1, [pc, #208] ; (8003434 <HAL_RCC_ClockConfig+0x1bc>)
8003364: 4313 orrs r3, r2
8003366: 608b str r3, [r1, #8]
/* Get Start Tick */
tickstart = HAL_GetTick();
8003368: f7fe fe02 bl 8001f70 <HAL_GetTick>
800336c: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
800336e: e00a b.n 8003386 <HAL_RCC_ClockConfig+0x10e>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8003370: f7fe fdfe bl 8001f70 <HAL_GetTick>
8003374: 4602 mov r2, r0
8003376: 68fb ldr r3, [r7, #12]
8003378: 1ad3 subs r3, r2, r3
800337a: f241 3288 movw r2, #5000 ; 0x1388
800337e: 4293 cmp r3, r2
8003380: d901 bls.n 8003386 <HAL_RCC_ClockConfig+0x10e>
{
return HAL_TIMEOUT;
8003382: 2303 movs r3, #3
8003384: e04f b.n 8003426 <HAL_RCC_ClockConfig+0x1ae>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8003386: 4b2b ldr r3, [pc, #172] ; (8003434 <HAL_RCC_ClockConfig+0x1bc>)
8003388: 689b ldr r3, [r3, #8]
800338a: f003 020c and.w r2, r3, #12
800338e: 687b ldr r3, [r7, #4]
8003390: 685b ldr r3, [r3, #4]
8003392: 009b lsls r3, r3, #2
8003394: 429a cmp r2, r3
8003396: d1eb bne.n 8003370 <HAL_RCC_ClockConfig+0xf8>
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLatency < __HAL_FLASH_GET_LATENCY())
8003398: 4b25 ldr r3, [pc, #148] ; (8003430 <HAL_RCC_ClockConfig+0x1b8>)
800339a: 681b ldr r3, [r3, #0]
800339c: f003 030f and.w r3, r3, #15
80033a0: 683a ldr r2, [r7, #0]
80033a2: 429a cmp r2, r3
80033a4: d20c bcs.n 80033c0 <HAL_RCC_ClockConfig+0x148>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
80033a6: 4b22 ldr r3, [pc, #136] ; (8003430 <HAL_RCC_ClockConfig+0x1b8>)
80033a8: 683a ldr r2, [r7, #0]
80033aa: b2d2 uxtb r2, r2
80033ac: 701a strb r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
80033ae: 4b20 ldr r3, [pc, #128] ; (8003430 <HAL_RCC_ClockConfig+0x1b8>)
80033b0: 681b ldr r3, [r3, #0]
80033b2: f003 030f and.w r3, r3, #15
80033b6: 683a ldr r2, [r7, #0]
80033b8: 429a cmp r2, r3
80033ba: d001 beq.n 80033c0 <HAL_RCC_ClockConfig+0x148>
{
return HAL_ERROR;
80033bc: 2301 movs r3, #1
80033be: e032 b.n 8003426 <HAL_RCC_ClockConfig+0x1ae>
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
80033c0: 687b ldr r3, [r7, #4]
80033c2: 681b ldr r3, [r3, #0]
80033c4: f003 0304 and.w r3, r3, #4
80033c8: 2b00 cmp r3, #0
80033ca: d008 beq.n 80033de <HAL_RCC_ClockConfig+0x166>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
80033cc: 4b19 ldr r3, [pc, #100] ; (8003434 <HAL_RCC_ClockConfig+0x1bc>)
80033ce: 689b ldr r3, [r3, #8]
80033d0: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00
80033d4: 687b ldr r3, [r7, #4]
80033d6: 68db ldr r3, [r3, #12]
80033d8: 4916 ldr r1, [pc, #88] ; (8003434 <HAL_RCC_ClockConfig+0x1bc>)
80033da: 4313 orrs r3, r2
80033dc: 608b str r3, [r1, #8]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
80033de: 687b ldr r3, [r7, #4]
80033e0: 681b ldr r3, [r3, #0]
80033e2: f003 0308 and.w r3, r3, #8
80033e6: 2b00 cmp r3, #0
80033e8: d009 beq.n 80033fe <HAL_RCC_ClockConfig+0x186>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
80033ea: 4b12 ldr r3, [pc, #72] ; (8003434 <HAL_RCC_ClockConfig+0x1bc>)
80033ec: 689b ldr r3, [r3, #8]
80033ee: f423 4260 bic.w r2, r3, #57344 ; 0xe000
80033f2: 687b ldr r3, [r7, #4]
80033f4: 691b ldr r3, [r3, #16]
80033f6: 00db lsls r3, r3, #3
80033f8: 490e ldr r1, [pc, #56] ; (8003434 <HAL_RCC_ClockConfig+0x1bc>)
80033fa: 4313 orrs r3, r2
80033fc: 608b str r3, [r1, #8]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
80033fe: f000 f821 bl 8003444 <HAL_RCC_GetSysClockFreq>
8003402: 4601 mov r1, r0
8003404: 4b0b ldr r3, [pc, #44] ; (8003434 <HAL_RCC_ClockConfig+0x1bc>)
8003406: 689b ldr r3, [r3, #8]
8003408: 091b lsrs r3, r3, #4
800340a: f003 030f and.w r3, r3, #15
800340e: 4a0a ldr r2, [pc, #40] ; (8003438 <HAL_RCC_ClockConfig+0x1c0>)
8003410: 5cd3 ldrb r3, [r2, r3]
8003412: fa21 f303 lsr.w r3, r1, r3
8003416: 4a09 ldr r2, [pc, #36] ; (800343c <HAL_RCC_ClockConfig+0x1c4>)
8003418: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings */
HAL_InitTick (uwTickPrio);
800341a: 4b09 ldr r3, [pc, #36] ; (8003440 <HAL_RCC_ClockConfig+0x1c8>)
800341c: 681b ldr r3, [r3, #0]
800341e: 4618 mov r0, r3
8003420: f7fe fd62 bl 8001ee8 <HAL_InitTick>
return HAL_OK;
8003424: 2300 movs r3, #0
}
8003426: 4618 mov r0, r3
8003428: 3710 adds r7, #16
800342a: 46bd mov sp, r7
800342c: bd80 pop {r7, pc}
800342e: bf00 nop
8003430: 40023c00 .word 0x40023c00
8003434: 40023800 .word 0x40023800
8003438: 08004484 .word 0x08004484
800343c: 20000004 .word 0x20000004
8003440: 20000008 .word 0x20000008
08003444 <HAL_RCC_GetSysClockFreq>:
*
*
* @retval SYSCLK frequency
*/
__weak uint32_t HAL_RCC_GetSysClockFreq(void)
{
8003444: b5f0 push {r4, r5, r6, r7, lr}
8003446: b085 sub sp, #20
8003448: af00 add r7, sp, #0
uint32_t pllm = 0U, pllvco = 0U, pllp = 0U;
800344a: 2300 movs r3, #0
800344c: 607b str r3, [r7, #4]
800344e: 2300 movs r3, #0
8003450: 60fb str r3, [r7, #12]
8003452: 2300 movs r3, #0
8003454: 603b str r3, [r7, #0]
uint32_t sysclockfreq = 0U;
8003456: 2300 movs r3, #0
8003458: 60bb str r3, [r7, #8]
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
800345a: 4b63 ldr r3, [pc, #396] ; (80035e8 <HAL_RCC_GetSysClockFreq+0x1a4>)
800345c: 689b ldr r3, [r3, #8]
800345e: f003 030c and.w r3, r3, #12
8003462: 2b04 cmp r3, #4
8003464: d007 beq.n 8003476 <HAL_RCC_GetSysClockFreq+0x32>
8003466: 2b08 cmp r3, #8
8003468: d008 beq.n 800347c <HAL_RCC_GetSysClockFreq+0x38>
800346a: 2b00 cmp r3, #0
800346c: f040 80b4 bne.w 80035d8 <HAL_RCC_GetSysClockFreq+0x194>
{
case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
{
sysclockfreq = HSI_VALUE;
8003470: 4b5e ldr r3, [pc, #376] ; (80035ec <HAL_RCC_GetSysClockFreq+0x1a8>)
8003472: 60bb str r3, [r7, #8]
break;
8003474: e0b3 b.n 80035de <HAL_RCC_GetSysClockFreq+0x19a>
}
case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
{
sysclockfreq = HSE_VALUE;
8003476: 4b5e ldr r3, [pc, #376] ; (80035f0 <HAL_RCC_GetSysClockFreq+0x1ac>)
8003478: 60bb str r3, [r7, #8]
break;
800347a: e0b0 b.n 80035de <HAL_RCC_GetSysClockFreq+0x19a>
}
case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */
{
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
SYSCLK = PLL_VCO / PLLP */
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
800347c: 4b5a ldr r3, [pc, #360] ; (80035e8 <HAL_RCC_GetSysClockFreq+0x1a4>)
800347e: 685b ldr r3, [r3, #4]
8003480: f003 033f and.w r3, r3, #63 ; 0x3f
8003484: 607b str r3, [r7, #4]
if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
8003486: 4b58 ldr r3, [pc, #352] ; (80035e8 <HAL_RCC_GetSysClockFreq+0x1a4>)
8003488: 685b ldr r3, [r3, #4]
800348a: f403 0380 and.w r3, r3, #4194304 ; 0x400000
800348e: 2b00 cmp r3, #0
8003490: d04a beq.n 8003528 <HAL_RCC_GetSysClockFreq+0xe4>
{
/* HSE used as PLL clock source */
pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
8003492: 4b55 ldr r3, [pc, #340] ; (80035e8 <HAL_RCC_GetSysClockFreq+0x1a4>)
8003494: 685b ldr r3, [r3, #4]
8003496: 099b lsrs r3, r3, #6
8003498: f04f 0400 mov.w r4, #0
800349c: f240 11ff movw r1, #511 ; 0x1ff
80034a0: f04f 0200 mov.w r2, #0
80034a4: ea03 0501 and.w r5, r3, r1
80034a8: ea04 0602 and.w r6, r4, r2
80034ac: 4629 mov r1, r5
80034ae: 4632 mov r2, r6
80034b0: f04f 0300 mov.w r3, #0
80034b4: f04f 0400 mov.w r4, #0
80034b8: 0154 lsls r4, r2, #5
80034ba: ea44 64d1 orr.w r4, r4, r1, lsr #27
80034be: 014b lsls r3, r1, #5
80034c0: 4619 mov r1, r3
80034c2: 4622 mov r2, r4
80034c4: 1b49 subs r1, r1, r5
80034c6: eb62 0206 sbc.w r2, r2, r6
80034ca: f04f 0300 mov.w r3, #0
80034ce: f04f 0400 mov.w r4, #0
80034d2: 0194 lsls r4, r2, #6
80034d4: ea44 6491 orr.w r4, r4, r1, lsr #26
80034d8: 018b lsls r3, r1, #6
80034da: 1a5b subs r3, r3, r1
80034dc: eb64 0402 sbc.w r4, r4, r2
80034e0: f04f 0100 mov.w r1, #0
80034e4: f04f 0200 mov.w r2, #0
80034e8: 00e2 lsls r2, r4, #3
80034ea: ea42 7253 orr.w r2, r2, r3, lsr #29
80034ee: 00d9 lsls r1, r3, #3
80034f0: 460b mov r3, r1
80034f2: 4614 mov r4, r2
80034f4: 195b adds r3, r3, r5
80034f6: eb44 0406 adc.w r4, r4, r6
80034fa: f04f 0100 mov.w r1, #0
80034fe: f04f 0200 mov.w r2, #0
8003502: 0262 lsls r2, r4, #9
8003504: ea42 52d3 orr.w r2, r2, r3, lsr #23
8003508: 0259 lsls r1, r3, #9
800350a: 460b mov r3, r1
800350c: 4614 mov r4, r2
800350e: 4618 mov r0, r3
8003510: 4621 mov r1, r4
8003512: 687b ldr r3, [r7, #4]
8003514: f04f 0400 mov.w r4, #0
8003518: 461a mov r2, r3
800351a: 4623 mov r3, r4
800351c: f7fc fe66 bl 80001ec <__aeabi_uldivmod>
8003520: 4603 mov r3, r0
8003522: 460c mov r4, r1
8003524: 60fb str r3, [r7, #12]
8003526: e049 b.n 80035bc <HAL_RCC_GetSysClockFreq+0x178>
}
else
{
/* HSI used as PLL clock source */
pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
8003528: 4b2f ldr r3, [pc, #188] ; (80035e8 <HAL_RCC_GetSysClockFreq+0x1a4>)
800352a: 685b ldr r3, [r3, #4]
800352c: 099b lsrs r3, r3, #6
800352e: f04f 0400 mov.w r4, #0
8003532: f240 11ff movw r1, #511 ; 0x1ff
8003536: f04f 0200 mov.w r2, #0
800353a: ea03 0501 and.w r5, r3, r1
800353e: ea04 0602 and.w r6, r4, r2
8003542: 4629 mov r1, r5
8003544: 4632 mov r2, r6
8003546: f04f 0300 mov.w r3, #0
800354a: f04f 0400 mov.w r4, #0
800354e: 0154 lsls r4, r2, #5
8003550: ea44 64d1 orr.w r4, r4, r1, lsr #27
8003554: 014b lsls r3, r1, #5
8003556: 4619 mov r1, r3
8003558: 4622 mov r2, r4
800355a: 1b49 subs r1, r1, r5
800355c: eb62 0206 sbc.w r2, r2, r6
8003560: f04f 0300 mov.w r3, #0
8003564: f04f 0400 mov.w r4, #0
8003568: 0194 lsls r4, r2, #6
800356a: ea44 6491 orr.w r4, r4, r1, lsr #26
800356e: 018b lsls r3, r1, #6
8003570: 1a5b subs r3, r3, r1
8003572: eb64 0402 sbc.w r4, r4, r2
8003576: f04f 0100 mov.w r1, #0
800357a: f04f 0200 mov.w r2, #0
800357e: 00e2 lsls r2, r4, #3
8003580: ea42 7253 orr.w r2, r2, r3, lsr #29
8003584: 00d9 lsls r1, r3, #3
8003586: 460b mov r3, r1
8003588: 4614 mov r4, r2
800358a: 195b adds r3, r3, r5
800358c: eb44 0406 adc.w r4, r4, r6
8003590: f04f 0100 mov.w r1, #0
8003594: f04f 0200 mov.w r2, #0
8003598: 02a2 lsls r2, r4, #10
800359a: ea42 5293 orr.w r2, r2, r3, lsr #22
800359e: 0299 lsls r1, r3, #10
80035a0: 460b mov r3, r1
80035a2: 4614 mov r4, r2
80035a4: 4618 mov r0, r3
80035a6: 4621 mov r1, r4
80035a8: 687b ldr r3, [r7, #4]
80035aa: f04f 0400 mov.w r4, #0
80035ae: 461a mov r2, r3
80035b0: 4623 mov r3, r4
80035b2: f7fc fe1b bl 80001ec <__aeabi_uldivmod>
80035b6: 4603 mov r3, r0
80035b8: 460c mov r4, r1
80035ba: 60fb str r3, [r7, #12]
}
pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U);
80035bc: 4b0a ldr r3, [pc, #40] ; (80035e8 <HAL_RCC_GetSysClockFreq+0x1a4>)
80035be: 685b ldr r3, [r3, #4]
80035c0: 0c1b lsrs r3, r3, #16
80035c2: f003 0303 and.w r3, r3, #3
80035c6: 3301 adds r3, #1
80035c8: 005b lsls r3, r3, #1
80035ca: 603b str r3, [r7, #0]
sysclockfreq = pllvco/pllp;
80035cc: 68fa ldr r2, [r7, #12]
80035ce: 683b ldr r3, [r7, #0]
80035d0: fbb2 f3f3 udiv r3, r2, r3
80035d4: 60bb str r3, [r7, #8]
break;
80035d6: e002 b.n 80035de <HAL_RCC_GetSysClockFreq+0x19a>
}
default:
{
sysclockfreq = HSI_VALUE;
80035d8: 4b04 ldr r3, [pc, #16] ; (80035ec <HAL_RCC_GetSysClockFreq+0x1a8>)
80035da: 60bb str r3, [r7, #8]
break;
80035dc: bf00 nop
}
}
return sysclockfreq;
80035de: 68bb ldr r3, [r7, #8]
}
80035e0: 4618 mov r0, r3
80035e2: 3714 adds r7, #20
80035e4: 46bd mov sp, r7
80035e6: bdf0 pop {r4, r5, r6, r7, pc}
80035e8: 40023800 .word 0x40023800
80035ec: 00f42400 .word 0x00f42400
80035f0: 007a1200 .word 0x007a1200
080035f4 <HAL_SPI_Init>:
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
{
80035f4: b580 push {r7, lr}
80035f6: b082 sub sp, #8
80035f8: af00 add r7, sp, #0
80035fa: 6078 str r0, [r7, #4]
/* Check the SPI handle allocation */
if (hspi == NULL)
80035fc: 687b ldr r3, [r7, #4]
80035fe: 2b00 cmp r3, #0
8003600: d101 bne.n 8003606 <HAL_SPI_Init+0x12>
{
return HAL_ERROR;
8003602: 2301 movs r3, #1
8003604: e056 b.n 80036b4 <HAL_SPI_Init+0xc0>
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
}
#else
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
8003606: 687b ldr r3, [r7, #4]
8003608: 2200 movs r2, #0
800360a: 629a str r2, [r3, #40] ; 0x28
#endif /* USE_SPI_CRC */
if (hspi->State == HAL_SPI_STATE_RESET)
800360c: 687b ldr r3, [r7, #4]
800360e: f893 3051 ldrb.w r3, [r3, #81] ; 0x51
8003612: b2db uxtb r3, r3
8003614: 2b00 cmp r3, #0
8003616: d106 bne.n 8003626 <HAL_SPI_Init+0x32>
{
/* Allocate lock resource and initialize it */
hspi->Lock = HAL_UNLOCKED;
8003618: 687b ldr r3, [r7, #4]
800361a: 2200 movs r2, #0
800361c: f883 2050 strb.w r2, [r3, #80] ; 0x50
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
hspi->MspInitCallback(hspi);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_SPI_MspInit(hspi);
8003620: 6878 ldr r0, [r7, #4]
8003622: f7fe fadb bl 8001bdc <HAL_SPI_MspInit>
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
hspi->State = HAL_SPI_STATE_BUSY;
8003626: 687b ldr r3, [r7, #4]
8003628: 2202 movs r2, #2
800362a: f883 2051 strb.w r2, [r3, #81] ; 0x51
/* Disable the selected SPI peripheral */
__HAL_SPI_DISABLE(hspi);
800362e: 687b ldr r3, [r7, #4]
8003630: 681b ldr r3, [r3, #0]
8003632: 681a ldr r2, [r3, #0]
8003634: 687b ldr r3, [r7, #4]
8003636: 681b ldr r3, [r3, #0]
8003638: f022 0240 bic.w r2, r2, #64 ; 0x40
800363c: 601a str r2, [r3, #0]
/*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
/* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
Communication speed, First bit and CRC calculation state */
WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize |
800363e: 687b ldr r3, [r7, #4]
8003640: 685a ldr r2, [r3, #4]
8003642: 687b ldr r3, [r7, #4]
8003644: 689b ldr r3, [r3, #8]
8003646: 431a orrs r2, r3
8003648: 687b ldr r3, [r7, #4]
800364a: 68db ldr r3, [r3, #12]
800364c: 431a orrs r2, r3
800364e: 687b ldr r3, [r7, #4]
8003650: 691b ldr r3, [r3, #16]
8003652: 431a orrs r2, r3
8003654: 687b ldr r3, [r7, #4]
8003656: 695b ldr r3, [r3, #20]
8003658: 431a orrs r2, r3
800365a: 687b ldr r3, [r7, #4]
800365c: 699b ldr r3, [r3, #24]
800365e: f403 7300 and.w r3, r3, #512 ; 0x200
8003662: 431a orrs r2, r3
8003664: 687b ldr r3, [r7, #4]
8003666: 69db ldr r3, [r3, #28]
8003668: 431a orrs r2, r3
800366a: 687b ldr r3, [r7, #4]
800366c: 6a1b ldr r3, [r3, #32]
800366e: ea42 0103 orr.w r1, r2, r3
8003672: 687b ldr r3, [r7, #4]
8003674: 6a9a ldr r2, [r3, #40] ; 0x28
8003676: 687b ldr r3, [r7, #4]
8003678: 681b ldr r3, [r3, #0]
800367a: 430a orrs r2, r1
800367c: 601a str r2, [r3, #0]
hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation));
/* Configure : NSS management, TI Mode */
WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode));
800367e: 687b ldr r3, [r7, #4]
8003680: 699b ldr r3, [r3, #24]
8003682: 0c1b lsrs r3, r3, #16
8003684: f003 0104 and.w r1, r3, #4
8003688: 687b ldr r3, [r7, #4]
800368a: 6a5a ldr r2, [r3, #36] ; 0x24
800368c: 687b ldr r3, [r7, #4]
800368e: 681b ldr r3, [r3, #0]
8003690: 430a orrs r2, r1
8003692: 605a str r2, [r3, #4]
}
#endif /* USE_SPI_CRC */
#if defined(SPI_I2SCFGR_I2SMOD)
/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
8003694: 687b ldr r3, [r7, #4]
8003696: 681b ldr r3, [r3, #0]
8003698: 69da ldr r2, [r3, #28]
800369a: 687b ldr r3, [r7, #4]
800369c: 681b ldr r3, [r3, #0]
800369e: f422 6200 bic.w r2, r2, #2048 ; 0x800
80036a2: 61da str r2, [r3, #28]
#endif /* SPI_I2SCFGR_I2SMOD */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
80036a4: 687b ldr r3, [r7, #4]
80036a6: 2200 movs r2, #0
80036a8: 655a str r2, [r3, #84] ; 0x54
hspi->State = HAL_SPI_STATE_READY;
80036aa: 687b ldr r3, [r7, #4]
80036ac: 2201 movs r2, #1
80036ae: f883 2051 strb.w r2, [r3, #81] ; 0x51
return HAL_OK;
80036b2: 2300 movs r3, #0
}
80036b4: 4618 mov r0, r3
80036b6: 3708 adds r7, #8
80036b8: 46bd mov sp, r7
80036ba: bd80 pop {r7, pc}
080036bc <HAL_SPI_Transmit_IT>:
* @param pData pointer to data buffer
* @param Size amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
{
80036bc: b480 push {r7}
80036be: b087 sub sp, #28
80036c0: af00 add r7, sp, #0
80036c2: 60f8 str r0, [r7, #12]
80036c4: 60b9 str r1, [r7, #8]
80036c6: 4613 mov r3, r2
80036c8: 80fb strh r3, [r7, #6]
HAL_StatusTypeDef errorcode = HAL_OK;
80036ca: 2300 movs r3, #0
80036cc: 75fb strb r3, [r7, #23]
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
/* Process Locked */
__HAL_LOCK(hspi);
80036ce: 68fb ldr r3, [r7, #12]
80036d0: f893 3050 ldrb.w r3, [r3, #80] ; 0x50
80036d4: 2b01 cmp r3, #1
80036d6: d101 bne.n 80036dc <HAL_SPI_Transmit_IT+0x20>
80036d8: 2302 movs r3, #2
80036da: e067 b.n 80037ac <HAL_SPI_Transmit_IT+0xf0>
80036dc: 68fb ldr r3, [r7, #12]
80036de: 2201 movs r2, #1
80036e0: f883 2050 strb.w r2, [r3, #80] ; 0x50
if ((pData == NULL) || (Size == 0U))
80036e4: 68bb ldr r3, [r7, #8]
80036e6: 2b00 cmp r3, #0
80036e8: d002 beq.n 80036f0 <HAL_SPI_Transmit_IT+0x34>
80036ea: 88fb ldrh r3, [r7, #6]
80036ec: 2b00 cmp r3, #0
80036ee: d102 bne.n 80036f6 <HAL_SPI_Transmit_IT+0x3a>
{
errorcode = HAL_ERROR;
80036f0: 2301 movs r3, #1
80036f2: 75fb strb r3, [r7, #23]
goto error;
80036f4: e055 b.n 80037a2 <HAL_SPI_Transmit_IT+0xe6>
}
if (hspi->State != HAL_SPI_STATE_READY)
80036f6: 68fb ldr r3, [r7, #12]
80036f8: f893 3051 ldrb.w r3, [r3, #81] ; 0x51
80036fc: b2db uxtb r3, r3
80036fe: 2b01 cmp r3, #1
8003700: d002 beq.n 8003708 <HAL_SPI_Transmit_IT+0x4c>
{
errorcode = HAL_BUSY;
8003702: 2302 movs r3, #2
8003704: 75fb strb r3, [r7, #23]
goto error;
8003706: e04c b.n 80037a2 <HAL_SPI_Transmit_IT+0xe6>
}
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_TX;
8003708: 68fb ldr r3, [r7, #12]
800370a: 2203 movs r2, #3
800370c: f883 2051 strb.w r2, [r3, #81] ; 0x51
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
8003710: 68fb ldr r3, [r7, #12]
8003712: 2200 movs r2, #0
8003714: 655a str r2, [r3, #84] ; 0x54
hspi->pTxBuffPtr = (uint8_t *)pData;
8003716: 68fb ldr r3, [r7, #12]
8003718: 68ba ldr r2, [r7, #8]
800371a: 631a str r2, [r3, #48] ; 0x30
hspi->TxXferSize = Size;
800371c: 68fb ldr r3, [r7, #12]
800371e: 88fa ldrh r2, [r7, #6]
8003720: 869a strh r2, [r3, #52] ; 0x34
hspi->TxXferCount = Size;
8003722: 68fb ldr r3, [r7, #12]
8003724: 88fa ldrh r2, [r7, #6]
8003726: 86da strh r2, [r3, #54] ; 0x36
/* Init field not used in handle to zero */
hspi->pRxBuffPtr = (uint8_t *)NULL;
8003728: 68fb ldr r3, [r7, #12]
800372a: 2200 movs r2, #0
800372c: 639a str r2, [r3, #56] ; 0x38
hspi->RxXferSize = 0U;
800372e: 68fb ldr r3, [r7, #12]
8003730: 2200 movs r2, #0
8003732: 879a strh r2, [r3, #60] ; 0x3c
hspi->RxXferCount = 0U;
8003734: 68fb ldr r3, [r7, #12]
8003736: 2200 movs r2, #0
8003738: 87da strh r2, [r3, #62] ; 0x3e
hspi->RxISR = NULL;
800373a: 68fb ldr r3, [r7, #12]
800373c: 2200 movs r2, #0
800373e: 641a str r2, [r3, #64] ; 0x40
/* Set the function for IT treatment */
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
8003740: 68fb ldr r3, [r7, #12]
8003742: 68db ldr r3, [r3, #12]
8003744: 2b00 cmp r3, #0
8003746: d003 beq.n 8003750 <HAL_SPI_Transmit_IT+0x94>
{
hspi->TxISR = SPI_TxISR_16BIT;
8003748: 68fb ldr r3, [r7, #12]
800374a: 4a1b ldr r2, [pc, #108] ; (80037b8 <HAL_SPI_Transmit_IT+0xfc>)
800374c: 645a str r2, [r3, #68] ; 0x44
800374e: e002 b.n 8003756 <HAL_SPI_Transmit_IT+0x9a>
}
else
{
hspi->TxISR = SPI_TxISR_8BIT;
8003750: 68fb ldr r3, [r7, #12]
8003752: 4a1a ldr r2, [pc, #104] ; (80037bc <HAL_SPI_Transmit_IT+0x100>)
8003754: 645a str r2, [r3, #68] ; 0x44
}
/* Configure communication direction : 1Line */
if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
8003756: 68fb ldr r3, [r7, #12]
8003758: 689b ldr r3, [r3, #8]
800375a: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
800375e: d107 bne.n 8003770 <HAL_SPI_Transmit_IT+0xb4>
{
SPI_1LINE_TX(hspi);
8003760: 68fb ldr r3, [r7, #12]
8003762: 681b ldr r3, [r3, #0]
8003764: 681a ldr r2, [r3, #0]
8003766: 68fb ldr r3, [r7, #12]
8003768: 681b ldr r3, [r3, #0]
800376a: f442 4280 orr.w r2, r2, #16384 ; 0x4000
800376e: 601a str r2, [r3, #0]
SPI_RESET_CRC(hspi);
}
#endif /* USE_SPI_CRC */
/* Enable TXE and ERR interrupt */
__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
8003770: 68fb ldr r3, [r7, #12]
8003772: 681b ldr r3, [r3, #0]
8003774: 685a ldr r2, [r3, #4]
8003776: 68fb ldr r3, [r7, #12]
8003778: 681b ldr r3, [r3, #0]
800377a: f042 02a0 orr.w r2, r2, #160 ; 0xa0
800377e: 605a str r2, [r3, #4]
/* Check if the SPI is already enabled */
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
8003780: 68fb ldr r3, [r7, #12]
8003782: 681b ldr r3, [r3, #0]
8003784: 681b ldr r3, [r3, #0]
8003786: f003 0340 and.w r3, r3, #64 ; 0x40
800378a: 2b40 cmp r3, #64 ; 0x40
800378c: d008 beq.n 80037a0 <HAL_SPI_Transmit_IT+0xe4>
{
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
800378e: 68fb ldr r3, [r7, #12]
8003790: 681b ldr r3, [r3, #0]
8003792: 681a ldr r2, [r3, #0]
8003794: 68fb ldr r3, [r7, #12]
8003796: 681b ldr r3, [r3, #0]
8003798: f042 0240 orr.w r2, r2, #64 ; 0x40
800379c: 601a str r2, [r3, #0]
800379e: e000 b.n 80037a2 <HAL_SPI_Transmit_IT+0xe6>
}
error :
80037a0: bf00 nop
__HAL_UNLOCK(hspi);
80037a2: 68fb ldr r3, [r7, #12]
80037a4: 2200 movs r2, #0
80037a6: f883 2050 strb.w r2, [r3, #80] ; 0x50
return errorcode;
80037aa: 7dfb ldrb r3, [r7, #23]
}
80037ac: 4618 mov r0, r3
80037ae: 371c adds r7, #28
80037b0: 46bd mov sp, r7
80037b2: f85d 7b04 ldr.w r7, [sp], #4
80037b6: 4770 bx lr
80037b8: 08003a57 .word 0x08003a57
80037bc: 08003a11 .word 0x08003a11
080037c0 <HAL_SPI_IRQHandler>:
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for the specified SPI module.
* @retval None
*/
void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
{
80037c0: b580 push {r7, lr}
80037c2: b088 sub sp, #32
80037c4: af00 add r7, sp, #0
80037c6: 6078 str r0, [r7, #4]
uint32_t itsource = hspi->Instance->CR2;
80037c8: 687b ldr r3, [r7, #4]
80037ca: 681b ldr r3, [r3, #0]
80037cc: 685b ldr r3, [r3, #4]
80037ce: 61fb str r3, [r7, #28]
uint32_t itflag = hspi->Instance->SR;
80037d0: 687b ldr r3, [r7, #4]
80037d2: 681b ldr r3, [r3, #0]
80037d4: 689b ldr r3, [r3, #8]
80037d6: 61bb str r3, [r7, #24]
/* SPI in mode Receiver ----------------------------------------------------*/
if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) &&
80037d8: 69bb ldr r3, [r7, #24]
80037da: 099b lsrs r3, r3, #6
80037dc: f003 0301 and.w r3, r3, #1
80037e0: 2b00 cmp r3, #0
80037e2: d10f bne.n 8003804 <HAL_SPI_IRQHandler+0x44>
(SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET))
80037e4: 69bb ldr r3, [r7, #24]
80037e6: f003 0301 and.w r3, r3, #1
if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) &&
80037ea: 2b00 cmp r3, #0
80037ec: d00a beq.n 8003804 <HAL_SPI_IRQHandler+0x44>
(SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET))
80037ee: 69fb ldr r3, [r7, #28]
80037f0: 099b lsrs r3, r3, #6
80037f2: f003 0301 and.w r3, r3, #1
80037f6: 2b00 cmp r3, #0
80037f8: d004 beq.n 8003804 <HAL_SPI_IRQHandler+0x44>
{
hspi->RxISR(hspi);
80037fa: 687b ldr r3, [r7, #4]
80037fc: 6c1b ldr r3, [r3, #64] ; 0x40
80037fe: 6878 ldr r0, [r7, #4]
8003800: 4798 blx r3
return;
8003802: e0d8 b.n 80039b6 <HAL_SPI_IRQHandler+0x1f6>
}
/* SPI in mode Transmitter -------------------------------------------------*/
if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET))
8003804: 69bb ldr r3, [r7, #24]
8003806: 085b lsrs r3, r3, #1
8003808: f003 0301 and.w r3, r3, #1
800380c: 2b00 cmp r3, #0
800380e: d00a beq.n 8003826 <HAL_SPI_IRQHandler+0x66>
8003810: 69fb ldr r3, [r7, #28]
8003812: 09db lsrs r3, r3, #7
8003814: f003 0301 and.w r3, r3, #1
8003818: 2b00 cmp r3, #0
800381a: d004 beq.n 8003826 <HAL_SPI_IRQHandler+0x66>
{
hspi->TxISR(hspi);
800381c: 687b ldr r3, [r7, #4]
800381e: 6c5b ldr r3, [r3, #68] ; 0x44
8003820: 6878 ldr r0, [r7, #4]
8003822: 4798 blx r3
return;
8003824: e0c7 b.n 80039b6 <HAL_SPI_IRQHandler+0x1f6>
}
/* SPI in Error Treatment --------------------------------------------------*/
if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
8003826: 69bb ldr r3, [r7, #24]
8003828: 095b lsrs r3, r3, #5
800382a: f003 0301 and.w r3, r3, #1
800382e: 2b00 cmp r3, #0
8003830: d10c bne.n 800384c <HAL_SPI_IRQHandler+0x8c>
8003832: 69bb ldr r3, [r7, #24]
8003834: 099b lsrs r3, r3, #6
8003836: f003 0301 and.w r3, r3, #1
800383a: 2b00 cmp r3, #0
800383c: d106 bne.n 800384c <HAL_SPI_IRQHandler+0x8c>
|| (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET))
800383e: 69bb ldr r3, [r7, #24]
8003840: 0a1b lsrs r3, r3, #8
8003842: f003 0301 and.w r3, r3, #1
8003846: 2b00 cmp r3, #0
8003848: f000 80b5 beq.w 80039b6 <HAL_SPI_IRQHandler+0x1f6>
800384c: 69fb ldr r3, [r7, #28]
800384e: 095b lsrs r3, r3, #5
8003850: f003 0301 and.w r3, r3, #1
8003854: 2b00 cmp r3, #0
8003856: f000 80ae beq.w 80039b6 <HAL_SPI_IRQHandler+0x1f6>
{
/* SPI Overrun error interrupt occurred ----------------------------------*/
if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
800385a: 69bb ldr r3, [r7, #24]
800385c: 099b lsrs r3, r3, #6
800385e: f003 0301 and.w r3, r3, #1
8003862: 2b00 cmp r3, #0
8003864: d023 beq.n 80038ae <HAL_SPI_IRQHandler+0xee>
{
if (hspi->State != HAL_SPI_STATE_BUSY_TX)
8003866: 687b ldr r3, [r7, #4]
8003868: f893 3051 ldrb.w r3, [r3, #81] ; 0x51
800386c: b2db uxtb r3, r3
800386e: 2b03 cmp r3, #3
8003870: d011 beq.n 8003896 <HAL_SPI_IRQHandler+0xd6>
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
8003872: 687b ldr r3, [r7, #4]
8003874: 6d5b ldr r3, [r3, #84] ; 0x54
8003876: f043 0204 orr.w r2, r3, #4
800387a: 687b ldr r3, [r7, #4]
800387c: 655a str r2, [r3, #84] ; 0x54
__HAL_SPI_CLEAR_OVRFLAG(hspi);
800387e: 2300 movs r3, #0
8003880: 617b str r3, [r7, #20]
8003882: 687b ldr r3, [r7, #4]
8003884: 681b ldr r3, [r3, #0]
8003886: 68db ldr r3, [r3, #12]
8003888: 617b str r3, [r7, #20]
800388a: 687b ldr r3, [r7, #4]
800388c: 681b ldr r3, [r3, #0]
800388e: 689b ldr r3, [r3, #8]
8003890: 617b str r3, [r7, #20]
8003892: 697b ldr r3, [r7, #20]
8003894: e00b b.n 80038ae <HAL_SPI_IRQHandler+0xee>
}
else
{
__HAL_SPI_CLEAR_OVRFLAG(hspi);
8003896: 2300 movs r3, #0
8003898: 613b str r3, [r7, #16]
800389a: 687b ldr r3, [r7, #4]
800389c: 681b ldr r3, [r3, #0]
800389e: 68db ldr r3, [r3, #12]
80038a0: 613b str r3, [r7, #16]
80038a2: 687b ldr r3, [r7, #4]
80038a4: 681b ldr r3, [r3, #0]
80038a6: 689b ldr r3, [r3, #8]
80038a8: 613b str r3, [r7, #16]
80038aa: 693b ldr r3, [r7, #16]
return;
80038ac: e083 b.n 80039b6 <HAL_SPI_IRQHandler+0x1f6>
}
}
/* SPI Mode Fault error interrupt occurred -------------------------------*/
if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET)
80038ae: 69bb ldr r3, [r7, #24]
80038b0: 095b lsrs r3, r3, #5
80038b2: f003 0301 and.w r3, r3, #1
80038b6: 2b00 cmp r3, #0
80038b8: d014 beq.n 80038e4 <HAL_SPI_IRQHandler+0x124>
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
80038ba: 687b ldr r3, [r7, #4]
80038bc: 6d5b ldr r3, [r3, #84] ; 0x54
80038be: f043 0201 orr.w r2, r3, #1
80038c2: 687b ldr r3, [r7, #4]
80038c4: 655a str r2, [r3, #84] ; 0x54
__HAL_SPI_CLEAR_MODFFLAG(hspi);
80038c6: 2300 movs r3, #0
80038c8: 60fb str r3, [r7, #12]
80038ca: 687b ldr r3, [r7, #4]
80038cc: 681b ldr r3, [r3, #0]
80038ce: 689b ldr r3, [r3, #8]
80038d0: 60fb str r3, [r7, #12]
80038d2: 687b ldr r3, [r7, #4]
80038d4: 681b ldr r3, [r3, #0]
80038d6: 681a ldr r2, [r3, #0]
80038d8: 687b ldr r3, [r7, #4]
80038da: 681b ldr r3, [r3, #0]
80038dc: f022 0240 bic.w r2, r2, #64 ; 0x40
80038e0: 601a str r2, [r3, #0]
80038e2: 68fb ldr r3, [r7, #12]
}
/* SPI Frame error interrupt occurred ------------------------------------*/
if (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)
80038e4: 69bb ldr r3, [r7, #24]
80038e6: 0a1b lsrs r3, r3, #8
80038e8: f003 0301 and.w r3, r3, #1
80038ec: 2b00 cmp r3, #0
80038ee: d00c beq.n 800390a <HAL_SPI_IRQHandler+0x14a>
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
80038f0: 687b ldr r3, [r7, #4]
80038f2: 6d5b ldr r3, [r3, #84] ; 0x54
80038f4: f043 0208 orr.w r2, r3, #8
80038f8: 687b ldr r3, [r7, #4]
80038fa: 655a str r2, [r3, #84] ; 0x54
__HAL_SPI_CLEAR_FREFLAG(hspi);
80038fc: 2300 movs r3, #0
80038fe: 60bb str r3, [r7, #8]
8003900: 687b ldr r3, [r7, #4]
8003902: 681b ldr r3, [r3, #0]
8003904: 689b ldr r3, [r3, #8]
8003906: 60bb str r3, [r7, #8]
8003908: 68bb ldr r3, [r7, #8]
}
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
800390a: 687b ldr r3, [r7, #4]
800390c: 6d5b ldr r3, [r3, #84] ; 0x54
800390e: 2b00 cmp r3, #0
8003910: d050 beq.n 80039b4 <HAL_SPI_IRQHandler+0x1f4>
{
/* Disable all interrupts */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
8003912: 687b ldr r3, [r7, #4]
8003914: 681b ldr r3, [r3, #0]
8003916: 685a ldr r2, [r3, #4]
8003918: 687b ldr r3, [r7, #4]
800391a: 681b ldr r3, [r3, #0]
800391c: f022 02e0 bic.w r2, r2, #224 ; 0xe0
8003920: 605a str r2, [r3, #4]
hspi->State = HAL_SPI_STATE_READY;
8003922: 687b ldr r3, [r7, #4]
8003924: 2201 movs r2, #1
8003926: f883 2051 strb.w r2, [r3, #81] ; 0x51
/* Disable the SPI DMA requests if enabled */
if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
800392a: 69fb ldr r3, [r7, #28]
800392c: f003 0302 and.w r3, r3, #2
8003930: 2b00 cmp r3, #0
8003932: d104 bne.n 800393e <HAL_SPI_IRQHandler+0x17e>
8003934: 69fb ldr r3, [r7, #28]
8003936: f003 0301 and.w r3, r3, #1
800393a: 2b00 cmp r3, #0
800393c: d034 beq.n 80039a8 <HAL_SPI_IRQHandler+0x1e8>
{
CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
800393e: 687b ldr r3, [r7, #4]
8003940: 681b ldr r3, [r3, #0]
8003942: 685a ldr r2, [r3, #4]
8003944: 687b ldr r3, [r7, #4]
8003946: 681b ldr r3, [r3, #0]
8003948: f022 0203 bic.w r2, r2, #3
800394c: 605a str r2, [r3, #4]
/* Abort the SPI DMA Rx channel */
if (hspi->hdmarx != NULL)
800394e: 687b ldr r3, [r7, #4]
8003950: 6cdb ldr r3, [r3, #76] ; 0x4c
8003952: 2b00 cmp r3, #0
8003954: d011 beq.n 800397a <HAL_SPI_IRQHandler+0x1ba>
{
/* Set the SPI DMA Abort callback :
will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
8003956: 687b ldr r3, [r7, #4]
8003958: 6cdb ldr r3, [r3, #76] ; 0x4c
800395a: 4a18 ldr r2, [pc, #96] ; (80039bc <HAL_SPI_IRQHandler+0x1fc>)
800395c: 651a str r2, [r3, #80] ; 0x50
if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx))
800395e: 687b ldr r3, [r7, #4]
8003960: 6cdb ldr r3, [r3, #76] ; 0x4c
8003962: 4618 mov r0, r3
8003964: f7ff f80d bl 8002982 <HAL_DMA_Abort_IT>
8003968: 4603 mov r3, r0
800396a: 2b00 cmp r3, #0
800396c: d005 beq.n 800397a <HAL_SPI_IRQHandler+0x1ba>
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
800396e: 687b ldr r3, [r7, #4]
8003970: 6d5b ldr r3, [r3, #84] ; 0x54
8003972: f043 0240 orr.w r2, r3, #64 ; 0x40
8003976: 687b ldr r3, [r7, #4]
8003978: 655a str r2, [r3, #84] ; 0x54
}
}
/* Abort the SPI DMA Tx channel */
if (hspi->hdmatx != NULL)
800397a: 687b ldr r3, [r7, #4]
800397c: 6c9b ldr r3, [r3, #72] ; 0x48
800397e: 2b00 cmp r3, #0
8003980: d016 beq.n 80039b0 <HAL_SPI_IRQHandler+0x1f0>
{
/* Set the SPI DMA Abort callback :
will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
8003982: 687b ldr r3, [r7, #4]
8003984: 6c9b ldr r3, [r3, #72] ; 0x48
8003986: 4a0d ldr r2, [pc, #52] ; (80039bc <HAL_SPI_IRQHandler+0x1fc>)
8003988: 651a str r2, [r3, #80] ; 0x50
if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx))
800398a: 687b ldr r3, [r7, #4]
800398c: 6c9b ldr r3, [r3, #72] ; 0x48
800398e: 4618 mov r0, r3
8003990: f7fe fff7 bl 8002982 <HAL_DMA_Abort_IT>
8003994: 4603 mov r3, r0
8003996: 2b00 cmp r3, #0
8003998: d00a beq.n 80039b0 <HAL_SPI_IRQHandler+0x1f0>
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
800399a: 687b ldr r3, [r7, #4]
800399c: 6d5b ldr r3, [r3, #84] ; 0x54
800399e: f043 0240 orr.w r2, r3, #64 ; 0x40
80039a2: 687b ldr r3, [r7, #4]
80039a4: 655a str r2, [r3, #84] ; 0x54
if (hspi->hdmatx != NULL)
80039a6: e003 b.n 80039b0 <HAL_SPI_IRQHandler+0x1f0>
{
/* Call user error callback */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
hspi->ErrorCallback(hspi);
#else
HAL_SPI_ErrorCallback(hspi);
80039a8: 6878 ldr r0, [r7, #4]
80039aa: f000 f813 bl 80039d4 <HAL_SPI_ErrorCallback>
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
}
return;
80039ae: e000 b.n 80039b2 <HAL_SPI_IRQHandler+0x1f2>
if (hspi->hdmatx != NULL)
80039b0: bf00 nop
return;
80039b2: bf00 nop
80039b4: bf00 nop
}
}
80039b6: 3720 adds r7, #32
80039b8: 46bd mov sp, r7
80039ba: bd80 pop {r7, pc}
80039bc: 080039e9 .word 0x080039e9
080039c0 <HAL_SPI_TxCpltCallback>:
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
{
80039c0: b480 push {r7}
80039c2: b083 sub sp, #12
80039c4: af00 add r7, sp, #0
80039c6: 6078 str r0, [r7, #4]
UNUSED(hspi);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SPI_TxCpltCallback should be implemented in the user file
*/
}
80039c8: bf00 nop
80039ca: 370c adds r7, #12
80039cc: 46bd mov sp, r7
80039ce: f85d 7b04 ldr.w r7, [sp], #4
80039d2: 4770 bx lr
080039d4 <HAL_SPI_ErrorCallback>:
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
{
80039d4: b480 push {r7}
80039d6: b083 sub sp, #12
80039d8: af00 add r7, sp, #0
80039da: 6078 str r0, [r7, #4]
the HAL_SPI_ErrorCallback should be implemented in the user file
*/
/* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
and user can use HAL_SPI_GetError() API to check the latest error occurred
*/
}
80039dc: bf00 nop
80039de: 370c adds r7, #12
80039e0: 46bd mov sp, r7
80039e2: f85d 7b04 ldr.w r7, [sp], #4
80039e6: 4770 bx lr
080039e8 <SPI_DMAAbortOnError>:
* (To be called at end of DMA Abort procedure following error occurrence).
* @param hdma DMA handle.
* @retval None
*/
static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
80039e8: b580 push {r7, lr}
80039ea: b084 sub sp, #16
80039ec: af00 add r7, sp, #0
80039ee: 6078 str r0, [r7, #4]
SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
80039f0: 687b ldr r3, [r7, #4]
80039f2: 6b9b ldr r3, [r3, #56] ; 0x38
80039f4: 60fb str r3, [r7, #12]
hspi->RxXferCount = 0U;
80039f6: 68fb ldr r3, [r7, #12]
80039f8: 2200 movs r2, #0
80039fa: 87da strh r2, [r3, #62] ; 0x3e
hspi->TxXferCount = 0U;
80039fc: 68fb ldr r3, [r7, #12]
80039fe: 2200 movs r2, #0
8003a00: 86da strh r2, [r3, #54] ; 0x36
/* Call user error callback */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
hspi->ErrorCallback(hspi);
#else
HAL_SPI_ErrorCallback(hspi);
8003a02: 68f8 ldr r0, [r7, #12]
8003a04: f7ff ffe6 bl 80039d4 <HAL_SPI_ErrorCallback>
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
8003a08: bf00 nop
8003a0a: 3710 adds r7, #16
8003a0c: 46bd mov sp, r7
8003a0e: bd80 pop {r7, pc}
08003a10 <SPI_TxISR_8BIT>:
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
{
8003a10: b580 push {r7, lr}
8003a12: b082 sub sp, #8
8003a14: af00 add r7, sp, #0
8003a16: 6078 str r0, [r7, #4]
*(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
8003a18: 687b ldr r3, [r7, #4]
8003a1a: 6b1a ldr r2, [r3, #48] ; 0x30
8003a1c: 687b ldr r3, [r7, #4]
8003a1e: 681b ldr r3, [r3, #0]
8003a20: 330c adds r3, #12
8003a22: 7812 ldrb r2, [r2, #0]
8003a24: 701a strb r2, [r3, #0]
hspi->pTxBuffPtr++;
8003a26: 687b ldr r3, [r7, #4]
8003a28: 6b1b ldr r3, [r3, #48] ; 0x30
8003a2a: 1c5a adds r2, r3, #1
8003a2c: 687b ldr r3, [r7, #4]
8003a2e: 631a str r2, [r3, #48] ; 0x30
hspi->TxXferCount--;
8003a30: 687b ldr r3, [r7, #4]
8003a32: 8edb ldrh r3, [r3, #54] ; 0x36
8003a34: b29b uxth r3, r3
8003a36: 3b01 subs r3, #1
8003a38: b29a uxth r2, r3
8003a3a: 687b ldr r3, [r7, #4]
8003a3c: 86da strh r2, [r3, #54] ; 0x36
if (hspi->TxXferCount == 0U)
8003a3e: 687b ldr r3, [r7, #4]
8003a40: 8edb ldrh r3, [r3, #54] ; 0x36
8003a42: b29b uxth r3, r3
8003a44: 2b00 cmp r3, #0
8003a46: d102 bne.n 8003a4e <SPI_TxISR_8BIT+0x3e>
{
/* Enable CRC Transmission */
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
#endif /* USE_SPI_CRC */
SPI_CloseTx_ISR(hspi);
8003a48: 6878 ldr r0, [r7, #4]
8003a4a: f000 f8d3 bl 8003bf4 <SPI_CloseTx_ISR>
}
}
8003a4e: bf00 nop
8003a50: 3708 adds r7, #8
8003a52: 46bd mov sp, r7
8003a54: bd80 pop {r7, pc}
08003a56 <SPI_TxISR_16BIT>:
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
{
8003a56: b580 push {r7, lr}
8003a58: b082 sub sp, #8
8003a5a: af00 add r7, sp, #0
8003a5c: 6078 str r0, [r7, #4]
/* Transmit data in 16 Bit mode */
hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
8003a5e: 687b ldr r3, [r7, #4]
8003a60: 6b1b ldr r3, [r3, #48] ; 0x30
8003a62: 881a ldrh r2, [r3, #0]
8003a64: 687b ldr r3, [r7, #4]
8003a66: 681b ldr r3, [r3, #0]
8003a68: 60da str r2, [r3, #12]
hspi->pTxBuffPtr += sizeof(uint16_t);
8003a6a: 687b ldr r3, [r7, #4]
8003a6c: 6b1b ldr r3, [r3, #48] ; 0x30
8003a6e: 1c9a adds r2, r3, #2
8003a70: 687b ldr r3, [r7, #4]
8003a72: 631a str r2, [r3, #48] ; 0x30
hspi->TxXferCount--;
8003a74: 687b ldr r3, [r7, #4]
8003a76: 8edb ldrh r3, [r3, #54] ; 0x36
8003a78: b29b uxth r3, r3
8003a7a: 3b01 subs r3, #1
8003a7c: b29a uxth r2, r3
8003a7e: 687b ldr r3, [r7, #4]
8003a80: 86da strh r2, [r3, #54] ; 0x36
if (hspi->TxXferCount == 0U)
8003a82: 687b ldr r3, [r7, #4]
8003a84: 8edb ldrh r3, [r3, #54] ; 0x36
8003a86: b29b uxth r3, r3
8003a88: 2b00 cmp r3, #0
8003a8a: d102 bne.n 8003a92 <SPI_TxISR_16BIT+0x3c>
{
/* Enable CRC Transmission */
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
#endif /* USE_SPI_CRC */
SPI_CloseTx_ISR(hspi);
8003a8c: 6878 ldr r0, [r7, #4]
8003a8e: f000 f8b1 bl 8003bf4 <SPI_CloseTx_ISR>
}
}
8003a92: bf00 nop
8003a94: 3708 adds r7, #8
8003a96: 46bd mov sp, r7
8003a98: bd80 pop {r7, pc}
08003a9a <SPI_WaitFlagStateUntilTimeout>:
* @param Tickstart tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
uint32_t Timeout, uint32_t Tickstart)
{
8003a9a: b580 push {r7, lr}
8003a9c: b084 sub sp, #16
8003a9e: af00 add r7, sp, #0
8003aa0: 60f8 str r0, [r7, #12]
8003aa2: 60b9 str r1, [r7, #8]
8003aa4: 603b str r3, [r7, #0]
8003aa6: 4613 mov r3, r2
8003aa8: 71fb strb r3, [r7, #7]
while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
8003aaa: e04c b.n 8003b46 <SPI_WaitFlagStateUntilTimeout+0xac>
{
if (Timeout != HAL_MAX_DELAY)
8003aac: 683b ldr r3, [r7, #0]
8003aae: f1b3 3fff cmp.w r3, #4294967295
8003ab2: d048 beq.n 8003b46 <SPI_WaitFlagStateUntilTimeout+0xac>
{
if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U))
8003ab4: f7fe fa5c bl 8001f70 <HAL_GetTick>
8003ab8: 4602 mov r2, r0
8003aba: 69bb ldr r3, [r7, #24]
8003abc: 1ad3 subs r3, r2, r3
8003abe: 683a ldr r2, [r7, #0]
8003ac0: 429a cmp r2, r3
8003ac2: d902 bls.n 8003aca <SPI_WaitFlagStateUntilTimeout+0x30>
8003ac4: 683b ldr r3, [r7, #0]
8003ac6: 2b00 cmp r3, #0
8003ac8: d13d bne.n 8003b46 <SPI_WaitFlagStateUntilTimeout+0xac>
/* Disable the SPI and reset the CRC: the CRC value should be cleared
on both master and slave sides in order to resynchronize the master
and slave for their respective CRC calculation */
/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
8003aca: 68fb ldr r3, [r7, #12]
8003acc: 681b ldr r3, [r3, #0]
8003ace: 685a ldr r2, [r3, #4]
8003ad0: 68fb ldr r3, [r7, #12]
8003ad2: 681b ldr r3, [r3, #0]
8003ad4: f022 02e0 bic.w r2, r2, #224 ; 0xe0
8003ad8: 605a str r2, [r3, #4]
if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
8003ada: 68fb ldr r3, [r7, #12]
8003adc: 685b ldr r3, [r3, #4]
8003ade: f5b3 7f82 cmp.w r3, #260 ; 0x104
8003ae2: d111 bne.n 8003b08 <SPI_WaitFlagStateUntilTimeout+0x6e>
8003ae4: 68fb ldr r3, [r7, #12]
8003ae6: 689b ldr r3, [r3, #8]
8003ae8: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
8003aec: d004 beq.n 8003af8 <SPI_WaitFlagStateUntilTimeout+0x5e>
|| (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
8003aee: 68fb ldr r3, [r7, #12]
8003af0: 689b ldr r3, [r3, #8]
8003af2: f5b3 6f80 cmp.w r3, #1024 ; 0x400
8003af6: d107 bne.n 8003b08 <SPI_WaitFlagStateUntilTimeout+0x6e>
{
/* Disable SPI peripheral */
__HAL_SPI_DISABLE(hspi);
8003af8: 68fb ldr r3, [r7, #12]
8003afa: 681b ldr r3, [r3, #0]
8003afc: 681a ldr r2, [r3, #0]
8003afe: 68fb ldr r3, [r7, #12]
8003b00: 681b ldr r3, [r3, #0]
8003b02: f022 0240 bic.w r2, r2, #64 ; 0x40
8003b06: 601a str r2, [r3, #0]
}
/* Reset CRC Calculation */
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
8003b08: 68fb ldr r3, [r7, #12]
8003b0a: 6a9b ldr r3, [r3, #40] ; 0x28
8003b0c: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
8003b10: d10f bne.n 8003b32 <SPI_WaitFlagStateUntilTimeout+0x98>
{
SPI_RESET_CRC(hspi);
8003b12: 68fb ldr r3, [r7, #12]
8003b14: 681b ldr r3, [r3, #0]
8003b16: 681a ldr r2, [r3, #0]
8003b18: 68fb ldr r3, [r7, #12]
8003b1a: 681b ldr r3, [r3, #0]
8003b1c: f422 5200 bic.w r2, r2, #8192 ; 0x2000
8003b20: 601a str r2, [r3, #0]
8003b22: 68fb ldr r3, [r7, #12]
8003b24: 681b ldr r3, [r3, #0]
8003b26: 681a ldr r2, [r3, #0]
8003b28: 68fb ldr r3, [r7, #12]
8003b2a: 681b ldr r3, [r3, #0]
8003b2c: f442 5200 orr.w r2, r2, #8192 ; 0x2000
8003b30: 601a str r2, [r3, #0]
}
hspi->State = HAL_SPI_STATE_READY;
8003b32: 68fb ldr r3, [r7, #12]
8003b34: 2201 movs r2, #1
8003b36: f883 2051 strb.w r2, [r3, #81] ; 0x51
/* Process Unlocked */
__HAL_UNLOCK(hspi);
8003b3a: 68fb ldr r3, [r7, #12]
8003b3c: 2200 movs r2, #0
8003b3e: f883 2050 strb.w r2, [r3, #80] ; 0x50
return HAL_TIMEOUT;
8003b42: 2303 movs r3, #3
8003b44: e00f b.n 8003b66 <SPI_WaitFlagStateUntilTimeout+0xcc>
while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
8003b46: 68fb ldr r3, [r7, #12]
8003b48: 681b ldr r3, [r3, #0]
8003b4a: 689a ldr r2, [r3, #8]
8003b4c: 68bb ldr r3, [r7, #8]
8003b4e: 4013 ands r3, r2
8003b50: 68ba ldr r2, [r7, #8]
8003b52: 429a cmp r2, r3
8003b54: bf0c ite eq
8003b56: 2301 moveq r3, #1
8003b58: 2300 movne r3, #0
8003b5a: b2db uxtb r3, r3
8003b5c: 461a mov r2, r3
8003b5e: 79fb ldrb r3, [r7, #7]
8003b60: 429a cmp r2, r3
8003b62: d1a3 bne.n 8003aac <SPI_WaitFlagStateUntilTimeout+0x12>
}
}
}
return HAL_OK;
8003b64: 2300 movs r3, #0
}
8003b66: 4618 mov r0, r3
8003b68: 3710 adds r7, #16
8003b6a: 46bd mov sp, r7
8003b6c: bd80 pop {r7, pc}
...
08003b70 <SPI_EndRxTxTransaction>:
* @param Timeout Timeout duration
* @param Tickstart tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
{
8003b70: b580 push {r7, lr}
8003b72: b088 sub sp, #32
8003b74: af02 add r7, sp, #8
8003b76: 60f8 str r0, [r7, #12]
8003b78: 60b9 str r1, [r7, #8]
8003b7a: 607a str r2, [r7, #4]
/* Timeout in µs */
__IO uint32_t count = SPI_BSY_FLAG_WORKAROUND_TIMEOUT * (SystemCoreClock / 24U / 1000000U);
8003b7c: 4b1b ldr r3, [pc, #108] ; (8003bec <SPI_EndRxTxTransaction+0x7c>)
8003b7e: 681b ldr r3, [r3, #0]
8003b80: 4a1b ldr r2, [pc, #108] ; (8003bf0 <SPI_EndRxTxTransaction+0x80>)
8003b82: fba2 2303 umull r2, r3, r2, r3
8003b86: 0d5b lsrs r3, r3, #21
8003b88: f44f 727a mov.w r2, #1000 ; 0x3e8
8003b8c: fb02 f303 mul.w r3, r2, r3
8003b90: 617b str r3, [r7, #20]
/* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */
if (hspi->Init.Mode == SPI_MODE_MASTER)
8003b92: 68fb ldr r3, [r7, #12]
8003b94: 685b ldr r3, [r3, #4]
8003b96: f5b3 7f82 cmp.w r3, #260 ; 0x104
8003b9a: d112 bne.n 8003bc2 <SPI_EndRxTxTransaction+0x52>
{
/* Control the BSY flag */
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
8003b9c: 687b ldr r3, [r7, #4]
8003b9e: 9300 str r3, [sp, #0]
8003ba0: 68bb ldr r3, [r7, #8]
8003ba2: 2200 movs r2, #0
8003ba4: 2180 movs r1, #128 ; 0x80
8003ba6: 68f8 ldr r0, [r7, #12]
8003ba8: f7ff ff77 bl 8003a9a <SPI_WaitFlagStateUntilTimeout>
8003bac: 4603 mov r3, r0
8003bae: 2b00 cmp r3, #0
8003bb0: d016 beq.n 8003be0 <SPI_EndRxTxTransaction+0x70>
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
8003bb2: 68fb ldr r3, [r7, #12]
8003bb4: 6d5b ldr r3, [r3, #84] ; 0x54
8003bb6: f043 0220 orr.w r2, r3, #32
8003bba: 68fb ldr r3, [r7, #12]
8003bbc: 655a str r2, [r3, #84] ; 0x54
return HAL_TIMEOUT;
8003bbe: 2303 movs r3, #3
8003bc0: e00f b.n 8003be2 <SPI_EndRxTxTransaction+0x72>
* User have to calculate the timeout value to fit with the time of 1 byte transfer.
* This time is directly link with the SPI clock from Master device.
*/
do
{
if (count == 0U)
8003bc2: 697b ldr r3, [r7, #20]
8003bc4: 2b00 cmp r3, #0
8003bc6: d00a beq.n 8003bde <SPI_EndRxTxTransaction+0x6e>
{
break;
}
count--;
8003bc8: 697b ldr r3, [r7, #20]
8003bca: 3b01 subs r3, #1
8003bcc: 617b str r3, [r7, #20]
} while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_BSY) != RESET);
8003bce: 68fb ldr r3, [r7, #12]
8003bd0: 681b ldr r3, [r3, #0]
8003bd2: 689b ldr r3, [r3, #8]
8003bd4: f003 0380 and.w r3, r3, #128 ; 0x80
8003bd8: 2b80 cmp r3, #128 ; 0x80
8003bda: d0f2 beq.n 8003bc2 <SPI_EndRxTxTransaction+0x52>
8003bdc: e000 b.n 8003be0 <SPI_EndRxTxTransaction+0x70>
break;
8003bde: bf00 nop
}
return HAL_OK;
8003be0: 2300 movs r3, #0
}
8003be2: 4618 mov r0, r3
8003be4: 3718 adds r7, #24
8003be6: 46bd mov sp, r7
8003be8: bd80 pop {r7, pc}
8003bea: bf00 nop
8003bec: 20000004 .word 0x20000004
8003bf0: 165e9f81 .word 0x165e9f81
08003bf4 <SPI_CloseTx_ISR>:
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
{
8003bf4: b580 push {r7, lr}
8003bf6: b086 sub sp, #24
8003bf8: af00 add r7, sp, #0
8003bfa: 6078 str r0, [r7, #4]
uint32_t tickstart;
__IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
8003bfc: 4b2c ldr r3, [pc, #176] ; (8003cb0 <SPI_CloseTx_ISR+0xbc>)
8003bfe: 681b ldr r3, [r3, #0]
8003c00: 4a2c ldr r2, [pc, #176] ; (8003cb4 <SPI_CloseTx_ISR+0xc0>)
8003c02: fba2 2303 umull r2, r3, r2, r3
8003c06: 0a5b lsrs r3, r3, #9
8003c08: 2264 movs r2, #100 ; 0x64
8003c0a: fb02 f303 mul.w r3, r2, r3
8003c0e: 613b str r3, [r7, #16]
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
8003c10: f7fe f9ae bl 8001f70 <HAL_GetTick>
8003c14: 6178 str r0, [r7, #20]
/* Wait until TXE flag is set */
do
{
if (count == 0U)
8003c16: 693b ldr r3, [r7, #16]
8003c18: 2b00 cmp r3, #0
8003c1a: d106 bne.n 8003c2a <SPI_CloseTx_ISR+0x36>
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
8003c1c: 687b ldr r3, [r7, #4]
8003c1e: 6d5b ldr r3, [r3, #84] ; 0x54
8003c20: f043 0220 orr.w r2, r3, #32
8003c24: 687b ldr r3, [r7, #4]
8003c26: 655a str r2, [r3, #84] ; 0x54
break;
8003c28: e009 b.n 8003c3e <SPI_CloseTx_ISR+0x4a>
}
count--;
8003c2a: 693b ldr r3, [r7, #16]
8003c2c: 3b01 subs r3, #1
8003c2e: 613b str r3, [r7, #16]
} while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
8003c30: 687b ldr r3, [r7, #4]
8003c32: 681b ldr r3, [r3, #0]
8003c34: 689b ldr r3, [r3, #8]
8003c36: f003 0302 and.w r3, r3, #2
8003c3a: 2b00 cmp r3, #0
8003c3c: d0eb beq.n 8003c16 <SPI_CloseTx_ISR+0x22>
/* Disable TXE and ERR interrupt */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
8003c3e: 687b ldr r3, [r7, #4]
8003c40: 681b ldr r3, [r3, #0]
8003c42: 685a ldr r2, [r3, #4]
8003c44: 687b ldr r3, [r7, #4]
8003c46: 681b ldr r3, [r3, #0]
8003c48: f022 02a0 bic.w r2, r2, #160 ; 0xa0
8003c4c: 605a str r2, [r3, #4]
/* Check the end of the transaction */
if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
8003c4e: 697a ldr r2, [r7, #20]
8003c50: 2164 movs r1, #100 ; 0x64
8003c52: 6878 ldr r0, [r7, #4]
8003c54: f7ff ff8c bl 8003b70 <SPI_EndRxTxTransaction>
8003c58: 4603 mov r3, r0
8003c5a: 2b00 cmp r3, #0
8003c5c: d005 beq.n 8003c6a <SPI_CloseTx_ISR+0x76>
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
8003c5e: 687b ldr r3, [r7, #4]
8003c60: 6d5b ldr r3, [r3, #84] ; 0x54
8003c62: f043 0220 orr.w r2, r3, #32
8003c66: 687b ldr r3, [r7, #4]
8003c68: 655a str r2, [r3, #84] ; 0x54
}
/* Clear overrun flag in 2 Lines communication mode because received is not read */
if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
8003c6a: 687b ldr r3, [r7, #4]
8003c6c: 689b ldr r3, [r3, #8]
8003c6e: 2b00 cmp r3, #0
8003c70: d10a bne.n 8003c88 <SPI_CloseTx_ISR+0x94>
{
__HAL_SPI_CLEAR_OVRFLAG(hspi);
8003c72: 2300 movs r3, #0
8003c74: 60fb str r3, [r7, #12]
8003c76: 687b ldr r3, [r7, #4]
8003c78: 681b ldr r3, [r3, #0]
8003c7a: 68db ldr r3, [r3, #12]
8003c7c: 60fb str r3, [r7, #12]
8003c7e: 687b ldr r3, [r7, #4]
8003c80: 681b ldr r3, [r3, #0]
8003c82: 689b ldr r3, [r3, #8]
8003c84: 60fb str r3, [r7, #12]
8003c86: 68fb ldr r3, [r7, #12]
}
hspi->State = HAL_SPI_STATE_READY;
8003c88: 687b ldr r3, [r7, #4]
8003c8a: 2201 movs r2, #1
8003c8c: f883 2051 strb.w r2, [r3, #81] ; 0x51
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
8003c90: 687b ldr r3, [r7, #4]
8003c92: 6d5b ldr r3, [r3, #84] ; 0x54
8003c94: 2b00 cmp r3, #0
8003c96: d003 beq.n 8003ca0 <SPI_CloseTx_ISR+0xac>
{
/* Call user error callback */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
hspi->ErrorCallback(hspi);
#else
HAL_SPI_ErrorCallback(hspi);
8003c98: 6878 ldr r0, [r7, #4]
8003c9a: f7ff fe9b bl 80039d4 <HAL_SPI_ErrorCallback>
hspi->TxCpltCallback(hspi);
#else
HAL_SPI_TxCpltCallback(hspi);
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
}
8003c9e: e002 b.n 8003ca6 <SPI_CloseTx_ISR+0xb2>
HAL_SPI_TxCpltCallback(hspi);
8003ca0: 6878 ldr r0, [r7, #4]
8003ca2: f7ff fe8d bl 80039c0 <HAL_SPI_TxCpltCallback>
}
8003ca6: bf00 nop
8003ca8: 3718 adds r7, #24
8003caa: 46bd mov sp, r7
8003cac: bd80 pop {r7, pc}
8003cae: bf00 nop
8003cb0: 20000004 .word 0x20000004
8003cb4: 057619f1 .word 0x057619f1
08003cb8 <HAL_TIM_Base_Init>:
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
8003cb8: b580 push {r7, lr}
8003cba: b082 sub sp, #8
8003cbc: af00 add r7, sp, #0
8003cbe: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8003cc0: 687b ldr r3, [r7, #4]
8003cc2: 2b00 cmp r3, #0
8003cc4: d101 bne.n 8003cca <HAL_TIM_Base_Init+0x12>
{
return HAL_ERROR;
8003cc6: 2301 movs r3, #1
8003cc8: e01d b.n 8003d06 <HAL_TIM_Base_Init+0x4e>
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8003cca: 687b ldr r3, [r7, #4]
8003ccc: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
8003cd0: b2db uxtb r3, r3
8003cd2: 2b00 cmp r3, #0
8003cd4: d106 bne.n 8003ce4 <HAL_TIM_Base_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8003cd6: 687b ldr r3, [r7, #4]
8003cd8: 2200 movs r2, #0
8003cda: f883 203c strb.w r2, [r3, #60] ; 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->Base_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
8003cde: 6878 ldr r0, [r7, #4]
8003ce0: f7fd ffcc bl 8001c7c <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8003ce4: 687b ldr r3, [r7, #4]
8003ce6: 2202 movs r2, #2
8003ce8: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8003cec: 687b ldr r3, [r7, #4]
8003cee: 681a ldr r2, [r3, #0]
8003cf0: 687b ldr r3, [r7, #4]
8003cf2: 3304 adds r3, #4
8003cf4: 4619 mov r1, r3
8003cf6: 4610 mov r0, r2
8003cf8: f000 f9ae bl 8004058 <TIM_Base_SetConfig>
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8003cfc: 687b ldr r3, [r7, #4]
8003cfe: 2201 movs r2, #1
8003d00: f883 203d strb.w r2, [r3, #61] ; 0x3d
return HAL_OK;
8003d04: 2300 movs r3, #0
}
8003d06: 4618 mov r0, r3
8003d08: 3708 adds r7, #8
8003d0a: 46bd mov sp, r7
8003d0c: bd80 pop {r7, pc}
08003d0e <HAL_TIM_Base_Start_IT>:
* @brief Starts the TIM Base generation in interrupt mode.
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
{
8003d0e: b480 push {r7}
8003d10: b085 sub sp, #20
8003d12: af00 add r7, sp, #0
8003d14: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
/* Enable the TIM Update interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
8003d16: 687b ldr r3, [r7, #4]
8003d18: 681b ldr r3, [r3, #0]
8003d1a: 68da ldr r2, [r3, #12]
8003d1c: 687b ldr r3, [r7, #4]
8003d1e: 681b ldr r3, [r3, #0]
8003d20: f042 0201 orr.w r2, r2, #1
8003d24: 60da str r2, [r3, #12]
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
8003d26: 687b ldr r3, [r7, #4]
8003d28: 681b ldr r3, [r3, #0]
8003d2a: 689b ldr r3, [r3, #8]
8003d2c: f003 0307 and.w r3, r3, #7
8003d30: 60fb str r3, [r7, #12]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8003d32: 68fb ldr r3, [r7, #12]
8003d34: 2b06 cmp r3, #6
8003d36: d007 beq.n 8003d48 <HAL_TIM_Base_Start_IT+0x3a>
{
__HAL_TIM_ENABLE(htim);
8003d38: 687b ldr r3, [r7, #4]
8003d3a: 681b ldr r3, [r3, #0]
8003d3c: 681a ldr r2, [r3, #0]
8003d3e: 687b ldr r3, [r7, #4]
8003d40: 681b ldr r3, [r3, #0]
8003d42: f042 0201 orr.w r2, r2, #1
8003d46: 601a str r2, [r3, #0]
}
/* Return function status */
return HAL_OK;
8003d48: 2300 movs r3, #0
}
8003d4a: 4618 mov r0, r3
8003d4c: 3714 adds r7, #20
8003d4e: 46bd mov sp, r7
8003d50: f85d 7b04 ldr.w r7, [sp], #4
8003d54: 4770 bx lr
08003d56 <HAL_TIM_OnePulse_Init>:
* @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
* @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
{
8003d56: b580 push {r7, lr}
8003d58: b082 sub sp, #8
8003d5a: af00 add r7, sp, #0
8003d5c: 6078 str r0, [r7, #4]
8003d5e: 6039 str r1, [r7, #0]
/* Check the TIM handle allocation */
if (htim == NULL)
8003d60: 687b ldr r3, [r7, #4]
8003d62: 2b00 cmp r3, #0
8003d64: d101 bne.n 8003d6a <HAL_TIM_OnePulse_Init+0x14>
{
return HAL_ERROR;
8003d66: 2301 movs r3, #1
8003d68: e02d b.n 8003dc6 <HAL_TIM_OnePulse_Init+0x70>
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_OPM_MODE(OnePulseMode));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8003d6a: 687b ldr r3, [r7, #4]
8003d6c: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
8003d70: b2db uxtb r3, r3
8003d72: 2b00 cmp r3, #0
8003d74: d106 bne.n 8003d84 <HAL_TIM_OnePulse_Init+0x2e>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8003d76: 687b ldr r3, [r7, #4]
8003d78: 2200 movs r2, #0
8003d7a: f883 203c strb.w r2, [r3, #60] ; 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->OnePulse_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_OnePulse_MspInit(htim);
8003d7e: 6878 ldr r0, [r7, #4]
8003d80: f000 f825 bl 8003dce <HAL_TIM_OnePulse_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8003d84: 687b ldr r3, [r7, #4]
8003d86: 2202 movs r2, #2
8003d88: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Configure the Time base in the One Pulse Mode */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8003d8c: 687b ldr r3, [r7, #4]
8003d8e: 681a ldr r2, [r3, #0]
8003d90: 687b ldr r3, [r7, #4]
8003d92: 3304 adds r3, #4
8003d94: 4619 mov r1, r3
8003d96: 4610 mov r0, r2
8003d98: f000 f95e bl 8004058 <TIM_Base_SetConfig>
/* Reset the OPM Bit */
htim->Instance->CR1 &= ~TIM_CR1_OPM;
8003d9c: 687b ldr r3, [r7, #4]
8003d9e: 681b ldr r3, [r3, #0]
8003da0: 681a ldr r2, [r3, #0]
8003da2: 687b ldr r3, [r7, #4]
8003da4: 681b ldr r3, [r3, #0]
8003da6: f022 0208 bic.w r2, r2, #8
8003daa: 601a str r2, [r3, #0]
/* Configure the OPM Mode */
htim->Instance->CR1 |= OnePulseMode;
8003dac: 687b ldr r3, [r7, #4]
8003dae: 681b ldr r3, [r3, #0]
8003db0: 6819 ldr r1, [r3, #0]
8003db2: 687b ldr r3, [r7, #4]
8003db4: 681b ldr r3, [r3, #0]
8003db6: 683a ldr r2, [r7, #0]
8003db8: 430a orrs r2, r1
8003dba: 601a str r2, [r3, #0]
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8003dbc: 687b ldr r3, [r7, #4]
8003dbe: 2201 movs r2, #1
8003dc0: f883 203d strb.w r2, [r3, #61] ; 0x3d
return HAL_OK;
8003dc4: 2300 movs r3, #0
}
8003dc6: 4618 mov r0, r3
8003dc8: 3708 adds r7, #8
8003dca: 46bd mov sp, r7
8003dcc: bd80 pop {r7, pc}
08003dce <HAL_TIM_OnePulse_MspInit>:
* @brief Initializes the TIM One Pulse MSP.
* @param htim TIM One Pulse handle
* @retval None
*/
__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
{
8003dce: b480 push {r7}
8003dd0: b083 sub sp, #12
8003dd2: af00 add r7, sp, #0
8003dd4: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_OnePulse_MspInit could be implemented in the user file
*/
}
8003dd6: bf00 nop
8003dd8: 370c adds r7, #12
8003dda: 46bd mov sp, r7
8003ddc: f85d 7b04 ldr.w r7, [sp], #4
8003de0: 4770 bx lr
08003de2 <HAL_TIM_IRQHandler>:
* @brief This function handles TIM interrupts requests.
* @param htim TIM handle
* @retval None
*/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
8003de2: b580 push {r7, lr}
8003de4: b082 sub sp, #8
8003de6: af00 add r7, sp, #0
8003de8: 6078 str r0, [r7, #4]
/* Capture compare 1 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
8003dea: 687b ldr r3, [r7, #4]
8003dec: 681b ldr r3, [r3, #0]
8003dee: 691b ldr r3, [r3, #16]
8003df0: f003 0302 and.w r3, r3, #2
8003df4: 2b02 cmp r3, #2
8003df6: d122 bne.n 8003e3e <HAL_TIM_IRQHandler+0x5c>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
8003df8: 687b ldr r3, [r7, #4]
8003dfa: 681b ldr r3, [r3, #0]
8003dfc: 68db ldr r3, [r3, #12]
8003dfe: f003 0302 and.w r3, r3, #2
8003e02: 2b02 cmp r3, #2
8003e04: d11b bne.n 8003e3e <HAL_TIM_IRQHandler+0x5c>
{
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
8003e06: 687b ldr r3, [r7, #4]
8003e08: 681b ldr r3, [r3, #0]
8003e0a: f06f 0202 mvn.w r2, #2
8003e0e: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
8003e10: 687b ldr r3, [r7, #4]
8003e12: 2201 movs r2, #1
8003e14: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
8003e16: 687b ldr r3, [r7, #4]
8003e18: 681b ldr r3, [r3, #0]
8003e1a: 699b ldr r3, [r3, #24]
8003e1c: f003 0303 and.w r3, r3, #3
8003e20: 2b00 cmp r3, #0
8003e22: d003 beq.n 8003e2c <HAL_TIM_IRQHandler+0x4a>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8003e24: 6878 ldr r0, [r7, #4]
8003e26: f000 f8f8 bl 800401a <HAL_TIM_IC_CaptureCallback>
8003e2a: e005 b.n 8003e38 <HAL_TIM_IRQHandler+0x56>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8003e2c: 6878 ldr r0, [r7, #4]
8003e2e: f000 f8ea bl 8004006 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8003e32: 6878 ldr r0, [r7, #4]
8003e34: f000 f8fb bl 800402e <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8003e38: 687b ldr r3, [r7, #4]
8003e3a: 2200 movs r2, #0
8003e3c: 771a strb r2, [r3, #28]
}
}
}
/* Capture compare 2 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
8003e3e: 687b ldr r3, [r7, #4]
8003e40: 681b ldr r3, [r3, #0]
8003e42: 691b ldr r3, [r3, #16]
8003e44: f003 0304 and.w r3, r3, #4
8003e48: 2b04 cmp r3, #4
8003e4a: d122 bne.n 8003e92 <HAL_TIM_IRQHandler+0xb0>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
8003e4c: 687b ldr r3, [r7, #4]
8003e4e: 681b ldr r3, [r3, #0]
8003e50: 68db ldr r3, [r3, #12]
8003e52: f003 0304 and.w r3, r3, #4
8003e56: 2b04 cmp r3, #4
8003e58: d11b bne.n 8003e92 <HAL_TIM_IRQHandler+0xb0>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
8003e5a: 687b ldr r3, [r7, #4]
8003e5c: 681b ldr r3, [r3, #0]
8003e5e: f06f 0204 mvn.w r2, #4
8003e62: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
8003e64: 687b ldr r3, [r7, #4]
8003e66: 2202 movs r2, #2
8003e68: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
8003e6a: 687b ldr r3, [r7, #4]
8003e6c: 681b ldr r3, [r3, #0]
8003e6e: 699b ldr r3, [r3, #24]
8003e70: f403 7340 and.w r3, r3, #768 ; 0x300
8003e74: 2b00 cmp r3, #0
8003e76: d003 beq.n 8003e80 <HAL_TIM_IRQHandler+0x9e>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8003e78: 6878 ldr r0, [r7, #4]
8003e7a: f000 f8ce bl 800401a <HAL_TIM_IC_CaptureCallback>
8003e7e: e005 b.n 8003e8c <HAL_TIM_IRQHandler+0xaa>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8003e80: 6878 ldr r0, [r7, #4]
8003e82: f000 f8c0 bl 8004006 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8003e86: 6878 ldr r0, [r7, #4]
8003e88: f000 f8d1 bl 800402e <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8003e8c: 687b ldr r3, [r7, #4]
8003e8e: 2200 movs r2, #0
8003e90: 771a strb r2, [r3, #28]
}
}
/* Capture compare 3 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
8003e92: 687b ldr r3, [r7, #4]
8003e94: 681b ldr r3, [r3, #0]
8003e96: 691b ldr r3, [r3, #16]
8003e98: f003 0308 and.w r3, r3, #8
8003e9c: 2b08 cmp r3, #8
8003e9e: d122 bne.n 8003ee6 <HAL_TIM_IRQHandler+0x104>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
8003ea0: 687b ldr r3, [r7, #4]
8003ea2: 681b ldr r3, [r3, #0]
8003ea4: 68db ldr r3, [r3, #12]
8003ea6: f003 0308 and.w r3, r3, #8
8003eaa: 2b08 cmp r3, #8
8003eac: d11b bne.n 8003ee6 <HAL_TIM_IRQHandler+0x104>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
8003eae: 687b ldr r3, [r7, #4]
8003eb0: 681b ldr r3, [r3, #0]
8003eb2: f06f 0208 mvn.w r2, #8
8003eb6: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
8003eb8: 687b ldr r3, [r7, #4]
8003eba: 2204 movs r2, #4
8003ebc: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
8003ebe: 687b ldr r3, [r7, #4]
8003ec0: 681b ldr r3, [r3, #0]
8003ec2: 69db ldr r3, [r3, #28]
8003ec4: f003 0303 and.w r3, r3, #3
8003ec8: 2b00 cmp r3, #0
8003eca: d003 beq.n 8003ed4 <HAL_TIM_IRQHandler+0xf2>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8003ecc: 6878 ldr r0, [r7, #4]
8003ece: f000 f8a4 bl 800401a <HAL_TIM_IC_CaptureCallback>
8003ed2: e005 b.n 8003ee0 <HAL_TIM_IRQHandler+0xfe>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8003ed4: 6878 ldr r0, [r7, #4]
8003ed6: f000 f896 bl 8004006 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8003eda: 6878 ldr r0, [r7, #4]
8003edc: f000 f8a7 bl 800402e <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8003ee0: 687b ldr r3, [r7, #4]
8003ee2: 2200 movs r2, #0
8003ee4: 771a strb r2, [r3, #28]
}
}
/* Capture compare 4 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
8003ee6: 687b ldr r3, [r7, #4]
8003ee8: 681b ldr r3, [r3, #0]
8003eea: 691b ldr r3, [r3, #16]
8003eec: f003 0310 and.w r3, r3, #16
8003ef0: 2b10 cmp r3, #16
8003ef2: d122 bne.n 8003f3a <HAL_TIM_IRQHandler+0x158>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
8003ef4: 687b ldr r3, [r7, #4]
8003ef6: 681b ldr r3, [r3, #0]
8003ef8: 68db ldr r3, [r3, #12]
8003efa: f003 0310 and.w r3, r3, #16
8003efe: 2b10 cmp r3, #16
8003f00: d11b bne.n 8003f3a <HAL_TIM_IRQHandler+0x158>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
8003f02: 687b ldr r3, [r7, #4]
8003f04: 681b ldr r3, [r3, #0]
8003f06: f06f 0210 mvn.w r2, #16
8003f0a: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
8003f0c: 687b ldr r3, [r7, #4]
8003f0e: 2208 movs r2, #8
8003f10: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
8003f12: 687b ldr r3, [r7, #4]
8003f14: 681b ldr r3, [r3, #0]
8003f16: 69db ldr r3, [r3, #28]
8003f18: f403 7340 and.w r3, r3, #768 ; 0x300
8003f1c: 2b00 cmp r3, #0
8003f1e: d003 beq.n 8003f28 <HAL_TIM_IRQHandler+0x146>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8003f20: 6878 ldr r0, [r7, #4]
8003f22: f000 f87a bl 800401a <HAL_TIM_IC_CaptureCallback>
8003f26: e005 b.n 8003f34 <HAL_TIM_IRQHandler+0x152>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8003f28: 6878 ldr r0, [r7, #4]
8003f2a: f000 f86c bl 8004006 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8003f2e: 6878 ldr r0, [r7, #4]
8003f30: f000 f87d bl 800402e <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8003f34: 687b ldr r3, [r7, #4]
8003f36: 2200 movs r2, #0
8003f38: 771a strb r2, [r3, #28]
}
}
/* TIM Update event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
8003f3a: 687b ldr r3, [r7, #4]
8003f3c: 681b ldr r3, [r3, #0]
8003f3e: 691b ldr r3, [r3, #16]
8003f40: f003 0301 and.w r3, r3, #1
8003f44: 2b01 cmp r3, #1
8003f46: d10e bne.n 8003f66 <HAL_TIM_IRQHandler+0x184>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
8003f48: 687b ldr r3, [r7, #4]
8003f4a: 681b ldr r3, [r3, #0]
8003f4c: 68db ldr r3, [r3, #12]
8003f4e: f003 0301 and.w r3, r3, #1
8003f52: 2b01 cmp r3, #1
8003f54: d107 bne.n 8003f66 <HAL_TIM_IRQHandler+0x184>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
8003f56: 687b ldr r3, [r7, #4]
8003f58: 681b ldr r3, [r3, #0]
8003f5a: f06f 0201 mvn.w r2, #1
8003f5e: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PeriodElapsedCallback(htim);
#else
HAL_TIM_PeriodElapsedCallback(htim);
8003f60: 6878 ldr r0, [r7, #4]
8003f62: f000 f846 bl 8003ff2 <HAL_TIM_PeriodElapsedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break input event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
8003f66: 687b ldr r3, [r7, #4]
8003f68: 681b ldr r3, [r3, #0]
8003f6a: 691b ldr r3, [r3, #16]
8003f6c: f003 0380 and.w r3, r3, #128 ; 0x80
8003f70: 2b80 cmp r3, #128 ; 0x80
8003f72: d10e bne.n 8003f92 <HAL_TIM_IRQHandler+0x1b0>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
8003f74: 687b ldr r3, [r7, #4]
8003f76: 681b ldr r3, [r3, #0]
8003f78: 68db ldr r3, [r3, #12]
8003f7a: f003 0380 and.w r3, r3, #128 ; 0x80
8003f7e: 2b80 cmp r3, #128 ; 0x80
8003f80: d107 bne.n 8003f92 <HAL_TIM_IRQHandler+0x1b0>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
8003f82: 687b ldr r3, [r7, #4]
8003f84: 681b ldr r3, [r3, #0]
8003f86: f06f 0280 mvn.w r2, #128 ; 0x80
8003f8a: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->BreakCallback(htim);
#else
HAL_TIMEx_BreakCallback(htim);
8003f8c: 6878 ldr r0, [r7, #4]
8003f8e: f000 f989 bl 80042a4 <HAL_TIMEx_BreakCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Trigger detection event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
8003f92: 687b ldr r3, [r7, #4]
8003f94: 681b ldr r3, [r3, #0]
8003f96: 691b ldr r3, [r3, #16]
8003f98: f003 0340 and.w r3, r3, #64 ; 0x40
8003f9c: 2b40 cmp r3, #64 ; 0x40
8003f9e: d10e bne.n 8003fbe <HAL_TIM_IRQHandler+0x1dc>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
8003fa0: 687b ldr r3, [r7, #4]
8003fa2: 681b ldr r3, [r3, #0]
8003fa4: 68db ldr r3, [r3, #12]
8003fa6: f003 0340 and.w r3, r3, #64 ; 0x40
8003faa: 2b40 cmp r3, #64 ; 0x40
8003fac: d107 bne.n 8003fbe <HAL_TIM_IRQHandler+0x1dc>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
8003fae: 687b ldr r3, [r7, #4]
8003fb0: 681b ldr r3, [r3, #0]
8003fb2: f06f 0240 mvn.w r2, #64 ; 0x40
8003fb6: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TriggerCallback(htim);
#else
HAL_TIM_TriggerCallback(htim);
8003fb8: 6878 ldr r0, [r7, #4]
8003fba: f000 f842 bl 8004042 <HAL_TIM_TriggerCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM commutation event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
8003fbe: 687b ldr r3, [r7, #4]
8003fc0: 681b ldr r3, [r3, #0]
8003fc2: 691b ldr r3, [r3, #16]
8003fc4: f003 0320 and.w r3, r3, #32
8003fc8: 2b20 cmp r3, #32
8003fca: d10e bne.n 8003fea <HAL_TIM_IRQHandler+0x208>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
8003fcc: 687b ldr r3, [r7, #4]
8003fce: 681b ldr r3, [r3, #0]
8003fd0: 68db ldr r3, [r3, #12]
8003fd2: f003 0320 and.w r3, r3, #32
8003fd6: 2b20 cmp r3, #32
8003fd8: d107 bne.n 8003fea <HAL_TIM_IRQHandler+0x208>
{
__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
8003fda: 687b ldr r3, [r7, #4]
8003fdc: 681b ldr r3, [r3, #0]
8003fde: f06f 0220 mvn.w r2, #32
8003fe2: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->CommutationCallback(htim);
#else
HAL_TIMEx_CommutCallback(htim);
8003fe4: 6878 ldr r0, [r7, #4]
8003fe6: f000 f953 bl 8004290 <HAL_TIMEx_CommutCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
}
8003fea: bf00 nop
8003fec: 3708 adds r7, #8
8003fee: 46bd mov sp, r7
8003ff0: bd80 pop {r7, pc}
08003ff2 <HAL_TIM_PeriodElapsedCallback>:
* @brief Period elapsed callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
8003ff2: b480 push {r7}
8003ff4: b083 sub sp, #12
8003ff6: af00 add r7, sp, #0
8003ff8: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
*/
}
8003ffa: bf00 nop
8003ffc: 370c adds r7, #12
8003ffe: 46bd mov sp, r7
8004000: f85d 7b04 ldr.w r7, [sp], #4
8004004: 4770 bx lr
08004006 <HAL_TIM_OC_DelayElapsedCallback>:
* @brief Output Compare callback in non-blocking mode
* @param htim TIM OC handle
* @retval None
*/
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
{
8004006: b480 push {r7}
8004008: b083 sub sp, #12
800400a: af00 add r7, sp, #0
800400c: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
*/
}
800400e: bf00 nop
8004010: 370c adds r7, #12
8004012: 46bd mov sp, r7
8004014: f85d 7b04 ldr.w r7, [sp], #4
8004018: 4770 bx lr
0800401a <HAL_TIM_IC_CaptureCallback>:
* @brief Input Capture callback in non-blocking mode
* @param htim TIM IC handle
* @retval None
*/
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
{
800401a: b480 push {r7}
800401c: b083 sub sp, #12
800401e: af00 add r7, sp, #0
8004020: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_IC_CaptureCallback could be implemented in the user file
*/
}
8004022: bf00 nop
8004024: 370c adds r7, #12
8004026: 46bd mov sp, r7
8004028: f85d 7b04 ldr.w r7, [sp], #4
800402c: 4770 bx lr
0800402e <HAL_TIM_PWM_PulseFinishedCallback>:
* @brief PWM Pulse finished callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
{
800402e: b480 push {r7}
8004030: b083 sub sp, #12
8004032: af00 add r7, sp, #0
8004034: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
*/
}
8004036: bf00 nop
8004038: 370c adds r7, #12
800403a: 46bd mov sp, r7
800403c: f85d 7b04 ldr.w r7, [sp], #4
8004040: 4770 bx lr
08004042 <HAL_TIM_TriggerCallback>:
* @brief Hall Trigger detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
{
8004042: b480 push {r7}
8004044: b083 sub sp, #12
8004046: af00 add r7, sp, #0
8004048: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_TriggerCallback could be implemented in the user file
*/
}
800404a: bf00 nop
800404c: 370c adds r7, #12
800404e: 46bd mov sp, r7
8004050: f85d 7b04 ldr.w r7, [sp], #4
8004054: 4770 bx lr
...
08004058 <TIM_Base_SetConfig>:
* @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
{
8004058: b480 push {r7}
800405a: b085 sub sp, #20
800405c: af00 add r7, sp, #0
800405e: 6078 str r0, [r7, #4]
8004060: 6039 str r1, [r7, #0]
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
8004062: 687b ldr r3, [r7, #4]
8004064: 681b ldr r3, [r3, #0]
8004066: 60fb str r3, [r7, #12]
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
8004068: 687b ldr r3, [r7, #4]
800406a: 4a40 ldr r2, [pc, #256] ; (800416c <TIM_Base_SetConfig+0x114>)
800406c: 4293 cmp r3, r2
800406e: d013 beq.n 8004098 <TIM_Base_SetConfig+0x40>
8004070: 687b ldr r3, [r7, #4]
8004072: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8004076: d00f beq.n 8004098 <TIM_Base_SetConfig+0x40>
8004078: 687b ldr r3, [r7, #4]
800407a: 4a3d ldr r2, [pc, #244] ; (8004170 <TIM_Base_SetConfig+0x118>)
800407c: 4293 cmp r3, r2
800407e: d00b beq.n 8004098 <TIM_Base_SetConfig+0x40>
8004080: 687b ldr r3, [r7, #4]
8004082: 4a3c ldr r2, [pc, #240] ; (8004174 <TIM_Base_SetConfig+0x11c>)
8004084: 4293 cmp r3, r2
8004086: d007 beq.n 8004098 <TIM_Base_SetConfig+0x40>
8004088: 687b ldr r3, [r7, #4]
800408a: 4a3b ldr r2, [pc, #236] ; (8004178 <TIM_Base_SetConfig+0x120>)
800408c: 4293 cmp r3, r2
800408e: d003 beq.n 8004098 <TIM_Base_SetConfig+0x40>
8004090: 687b ldr r3, [r7, #4]
8004092: 4a3a ldr r2, [pc, #232] ; (800417c <TIM_Base_SetConfig+0x124>)
8004094: 4293 cmp r3, r2
8004096: d108 bne.n 80040aa <TIM_Base_SetConfig+0x52>
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
8004098: 68fb ldr r3, [r7, #12]
800409a: f023 0370 bic.w r3, r3, #112 ; 0x70
800409e: 60fb str r3, [r7, #12]
tmpcr1 |= Structure->CounterMode;
80040a0: 683b ldr r3, [r7, #0]
80040a2: 685b ldr r3, [r3, #4]
80040a4: 68fa ldr r2, [r7, #12]
80040a6: 4313 orrs r3, r2
80040a8: 60fb str r3, [r7, #12]
}
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
80040aa: 687b ldr r3, [r7, #4]
80040ac: 4a2f ldr r2, [pc, #188] ; (800416c <TIM_Base_SetConfig+0x114>)
80040ae: 4293 cmp r3, r2
80040b0: d02b beq.n 800410a <TIM_Base_SetConfig+0xb2>
80040b2: 687b ldr r3, [r7, #4]
80040b4: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
80040b8: d027 beq.n 800410a <TIM_Base_SetConfig+0xb2>
80040ba: 687b ldr r3, [r7, #4]
80040bc: 4a2c ldr r2, [pc, #176] ; (8004170 <TIM_Base_SetConfig+0x118>)
80040be: 4293 cmp r3, r2
80040c0: d023 beq.n 800410a <TIM_Base_SetConfig+0xb2>
80040c2: 687b ldr r3, [r7, #4]
80040c4: 4a2b ldr r2, [pc, #172] ; (8004174 <TIM_Base_SetConfig+0x11c>)
80040c6: 4293 cmp r3, r2
80040c8: d01f beq.n 800410a <TIM_Base_SetConfig+0xb2>
80040ca: 687b ldr r3, [r7, #4]
80040cc: 4a2a ldr r2, [pc, #168] ; (8004178 <TIM_Base_SetConfig+0x120>)
80040ce: 4293 cmp r3, r2
80040d0: d01b beq.n 800410a <TIM_Base_SetConfig+0xb2>
80040d2: 687b ldr r3, [r7, #4]
80040d4: 4a29 ldr r2, [pc, #164] ; (800417c <TIM_Base_SetConfig+0x124>)
80040d6: 4293 cmp r3, r2
80040d8: d017 beq.n 800410a <TIM_Base_SetConfig+0xb2>
80040da: 687b ldr r3, [r7, #4]
80040dc: 4a28 ldr r2, [pc, #160] ; (8004180 <TIM_Base_SetConfig+0x128>)
80040de: 4293 cmp r3, r2
80040e0: d013 beq.n 800410a <TIM_Base_SetConfig+0xb2>
80040e2: 687b ldr r3, [r7, #4]
80040e4: 4a27 ldr r2, [pc, #156] ; (8004184 <TIM_Base_SetConfig+0x12c>)
80040e6: 4293 cmp r3, r2
80040e8: d00f beq.n 800410a <TIM_Base_SetConfig+0xb2>
80040ea: 687b ldr r3, [r7, #4]
80040ec: 4a26 ldr r2, [pc, #152] ; (8004188 <TIM_Base_SetConfig+0x130>)
80040ee: 4293 cmp r3, r2
80040f0: d00b beq.n 800410a <TIM_Base_SetConfig+0xb2>
80040f2: 687b ldr r3, [r7, #4]
80040f4: 4a25 ldr r2, [pc, #148] ; (800418c <TIM_Base_SetConfig+0x134>)
80040f6: 4293 cmp r3, r2
80040f8: d007 beq.n 800410a <TIM_Base_SetConfig+0xb2>
80040fa: 687b ldr r3, [r7, #4]
80040fc: 4a24 ldr r2, [pc, #144] ; (8004190 <TIM_Base_SetConfig+0x138>)
80040fe: 4293 cmp r3, r2
8004100: d003 beq.n 800410a <TIM_Base_SetConfig+0xb2>
8004102: 687b ldr r3, [r7, #4]
8004104: 4a23 ldr r2, [pc, #140] ; (8004194 <TIM_Base_SetConfig+0x13c>)
8004106: 4293 cmp r3, r2
8004108: d108 bne.n 800411c <TIM_Base_SetConfig+0xc4>
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
800410a: 68fb ldr r3, [r7, #12]
800410c: f423 7340 bic.w r3, r3, #768 ; 0x300
8004110: 60fb str r3, [r7, #12]
tmpcr1 |= (uint32_t)Structure->ClockDivision;
8004112: 683b ldr r3, [r7, #0]
8004114: 68db ldr r3, [r3, #12]
8004116: 68fa ldr r2, [r7, #12]
8004118: 4313 orrs r3, r2
800411a: 60fb str r3, [r7, #12]
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
800411c: 68fb ldr r3, [r7, #12]
800411e: f023 0280 bic.w r2, r3, #128 ; 0x80
8004122: 683b ldr r3, [r7, #0]
8004124: 695b ldr r3, [r3, #20]
8004126: 4313 orrs r3, r2
8004128: 60fb str r3, [r7, #12]
TIMx->CR1 = tmpcr1;
800412a: 687b ldr r3, [r7, #4]
800412c: 68fa ldr r2, [r7, #12]
800412e: 601a str r2, [r3, #0]
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
8004130: 683b ldr r3, [r7, #0]
8004132: 689a ldr r2, [r3, #8]
8004134: 687b ldr r3, [r7, #4]
8004136: 62da str r2, [r3, #44] ; 0x2c
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
8004138: 683b ldr r3, [r7, #0]
800413a: 681a ldr r2, [r3, #0]
800413c: 687b ldr r3, [r7, #4]
800413e: 629a str r2, [r3, #40] ; 0x28
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
8004140: 687b ldr r3, [r7, #4]
8004142: 4a0a ldr r2, [pc, #40] ; (800416c <TIM_Base_SetConfig+0x114>)
8004144: 4293 cmp r3, r2
8004146: d003 beq.n 8004150 <TIM_Base_SetConfig+0xf8>
8004148: 687b ldr r3, [r7, #4]
800414a: 4a0c ldr r2, [pc, #48] ; (800417c <TIM_Base_SetConfig+0x124>)
800414c: 4293 cmp r3, r2
800414e: d103 bne.n 8004158 <TIM_Base_SetConfig+0x100>
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
8004150: 683b ldr r3, [r7, #0]
8004152: 691a ldr r2, [r3, #16]
8004154: 687b ldr r3, [r7, #4]
8004156: 631a str r2, [r3, #48] ; 0x30
}
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
8004158: 687b ldr r3, [r7, #4]
800415a: 2201 movs r2, #1
800415c: 615a str r2, [r3, #20]
}
800415e: bf00 nop
8004160: 3714 adds r7, #20
8004162: 46bd mov sp, r7
8004164: f85d 7b04 ldr.w r7, [sp], #4
8004168: 4770 bx lr
800416a: bf00 nop
800416c: 40010000 .word 0x40010000
8004170: 40000400 .word 0x40000400
8004174: 40000800 .word 0x40000800
8004178: 40000c00 .word 0x40000c00
800417c: 40010400 .word 0x40010400
8004180: 40014000 .word 0x40014000
8004184: 40014400 .word 0x40014400
8004188: 40014800 .word 0x40014800
800418c: 40001800 .word 0x40001800
8004190: 40001c00 .word 0x40001c00
8004194: 40002000 .word 0x40002000
08004198 <HAL_TIMEx_MasterConfigSynchronization>:
* mode.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
TIM_MasterConfigTypeDef *sMasterConfig)
{
8004198: b480 push {r7}
800419a: b085 sub sp, #20
800419c: af00 add r7, sp, #0
800419e: 6078 str r0, [r7, #4]
80041a0: 6039 str r1, [r7, #0]
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
/* Check input state */
__HAL_LOCK(htim);
80041a2: 687b ldr r3, [r7, #4]
80041a4: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
80041a8: 2b01 cmp r3, #1
80041aa: d101 bne.n 80041b0 <HAL_TIMEx_MasterConfigSynchronization+0x18>
80041ac: 2302 movs r3, #2
80041ae: e05a b.n 8004266 <HAL_TIMEx_MasterConfigSynchronization+0xce>
80041b0: 687b ldr r3, [r7, #4]
80041b2: 2201 movs r2, #1
80041b4: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Change the handler state */
htim->State = HAL_TIM_STATE_BUSY;
80041b8: 687b ldr r3, [r7, #4]
80041ba: 2202 movs r2, #2
80041bc: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Get the TIMx CR2 register value */
tmpcr2 = htim->Instance->CR2;
80041c0: 687b ldr r3, [r7, #4]
80041c2: 681b ldr r3, [r3, #0]
80041c4: 685b ldr r3, [r3, #4]
80041c6: 60fb str r3, [r7, #12]
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
80041c8: 687b ldr r3, [r7, #4]
80041ca: 681b ldr r3, [r3, #0]
80041cc: 689b ldr r3, [r3, #8]
80041ce: 60bb str r3, [r7, #8]
/* Reset the MMS Bits */
tmpcr2 &= ~TIM_CR2_MMS;
80041d0: 68fb ldr r3, [r7, #12]
80041d2: f023 0370 bic.w r3, r3, #112 ; 0x70
80041d6: 60fb str r3, [r7, #12]
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
80041d8: 683b ldr r3, [r7, #0]
80041da: 681b ldr r3, [r3, #0]
80041dc: 68fa ldr r2, [r7, #12]
80041de: 4313 orrs r3, r2
80041e0: 60fb str r3, [r7, #12]
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
80041e2: 687b ldr r3, [r7, #4]
80041e4: 681b ldr r3, [r3, #0]
80041e6: 68fa ldr r2, [r7, #12]
80041e8: 605a str r2, [r3, #4]
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
80041ea: 687b ldr r3, [r7, #4]
80041ec: 681b ldr r3, [r3, #0]
80041ee: 4a21 ldr r2, [pc, #132] ; (8004274 <HAL_TIMEx_MasterConfigSynchronization+0xdc>)
80041f0: 4293 cmp r3, r2
80041f2: d022 beq.n 800423a <HAL_TIMEx_MasterConfigSynchronization+0xa2>
80041f4: 687b ldr r3, [r7, #4]
80041f6: 681b ldr r3, [r3, #0]
80041f8: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
80041fc: d01d beq.n 800423a <HAL_TIMEx_MasterConfigSynchronization+0xa2>
80041fe: 687b ldr r3, [r7, #4]
8004200: 681b ldr r3, [r3, #0]
8004202: 4a1d ldr r2, [pc, #116] ; (8004278 <HAL_TIMEx_MasterConfigSynchronization+0xe0>)
8004204: 4293 cmp r3, r2
8004206: d018 beq.n 800423a <HAL_TIMEx_MasterConfigSynchronization+0xa2>
8004208: 687b ldr r3, [r7, #4]
800420a: 681b ldr r3, [r3, #0]
800420c: 4a1b ldr r2, [pc, #108] ; (800427c <HAL_TIMEx_MasterConfigSynchronization+0xe4>)
800420e: 4293 cmp r3, r2
8004210: d013 beq.n 800423a <HAL_TIMEx_MasterConfigSynchronization+0xa2>
8004212: 687b ldr r3, [r7, #4]
8004214: 681b ldr r3, [r3, #0]
8004216: 4a1a ldr r2, [pc, #104] ; (8004280 <HAL_TIMEx_MasterConfigSynchronization+0xe8>)
8004218: 4293 cmp r3, r2
800421a: d00e beq.n 800423a <HAL_TIMEx_MasterConfigSynchronization+0xa2>
800421c: 687b ldr r3, [r7, #4]
800421e: 681b ldr r3, [r3, #0]
8004220: 4a18 ldr r2, [pc, #96] ; (8004284 <HAL_TIMEx_MasterConfigSynchronization+0xec>)
8004222: 4293 cmp r3, r2
8004224: d009 beq.n 800423a <HAL_TIMEx_MasterConfigSynchronization+0xa2>
8004226: 687b ldr r3, [r7, #4]
8004228: 681b ldr r3, [r3, #0]
800422a: 4a17 ldr r2, [pc, #92] ; (8004288 <HAL_TIMEx_MasterConfigSynchronization+0xf0>)
800422c: 4293 cmp r3, r2
800422e: d004 beq.n 800423a <HAL_TIMEx_MasterConfigSynchronization+0xa2>
8004230: 687b ldr r3, [r7, #4]
8004232: 681b ldr r3, [r3, #0]
8004234: 4a15 ldr r2, [pc, #84] ; (800428c <HAL_TIMEx_MasterConfigSynchronization+0xf4>)
8004236: 4293 cmp r3, r2
8004238: d10c bne.n 8004254 <HAL_TIMEx_MasterConfigSynchronization+0xbc>
{
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
800423a: 68bb ldr r3, [r7, #8]
800423c: f023 0380 bic.w r3, r3, #128 ; 0x80
8004240: 60bb str r3, [r7, #8]
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
8004242: 683b ldr r3, [r7, #0]
8004244: 685b ldr r3, [r3, #4]
8004246: 68ba ldr r2, [r7, #8]
8004248: 4313 orrs r3, r2
800424a: 60bb str r3, [r7, #8]
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
800424c: 687b ldr r3, [r7, #4]
800424e: 681b ldr r3, [r3, #0]
8004250: 68ba ldr r2, [r7, #8]
8004252: 609a str r2, [r3, #8]
}
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
8004254: 687b ldr r3, [r7, #4]
8004256: 2201 movs r2, #1
8004258: f883 203d strb.w r2, [r3, #61] ; 0x3d
__HAL_UNLOCK(htim);
800425c: 687b ldr r3, [r7, #4]
800425e: 2200 movs r2, #0
8004260: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_OK;
8004264: 2300 movs r3, #0
}
8004266: 4618 mov r0, r3
8004268: 3714 adds r7, #20
800426a: 46bd mov sp, r7
800426c: f85d 7b04 ldr.w r7, [sp], #4
8004270: 4770 bx lr
8004272: bf00 nop
8004274: 40010000 .word 0x40010000
8004278: 40000400 .word 0x40000400
800427c: 40000800 .word 0x40000800
8004280: 40000c00 .word 0x40000c00
8004284: 40010400 .word 0x40010400
8004288: 40014000 .word 0x40014000
800428c: 40001800 .word 0x40001800
08004290 <HAL_TIMEx_CommutCallback>:
* @brief Hall commutation changed callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
{
8004290: b480 push {r7}
8004292: b083 sub sp, #12
8004294: af00 add r7, sp, #0
8004296: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_CommutCallback could be implemented in the user file
*/
}
8004298: bf00 nop
800429a: 370c adds r7, #12
800429c: 46bd mov sp, r7
800429e: f85d 7b04 ldr.w r7, [sp], #4
80042a2: 4770 bx lr
080042a4 <HAL_TIMEx_BreakCallback>:
* @brief Hall Break detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
{
80042a4: b480 push {r7}
80042a6: b083 sub sp, #12
80042a8: af00 add r7, sp, #0
80042aa: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_BreakCallback could be implemented in the user file
*/
}
80042ac: bf00 nop
80042ae: 370c adds r7, #12
80042b0: 46bd mov sp, r7
80042b2: f85d 7b04 ldr.w r7, [sp], #4
80042b6: 4770 bx lr
080042b8 <__errno>:
80042b8: 4b01 ldr r3, [pc, #4] ; (80042c0 <__errno+0x8>)
80042ba: 6818 ldr r0, [r3, #0]
80042bc: 4770 bx lr
80042be: bf00 nop
80042c0: 20000010 .word 0x20000010
080042c4 <__libc_init_array>:
80042c4: b570 push {r4, r5, r6, lr}
80042c6: 4e0d ldr r6, [pc, #52] ; (80042fc <__libc_init_array+0x38>)
80042c8: 4c0d ldr r4, [pc, #52] ; (8004300 <__libc_init_array+0x3c>)
80042ca: 1ba4 subs r4, r4, r6
80042cc: 10a4 asrs r4, r4, #2
80042ce: 2500 movs r5, #0
80042d0: 42a5 cmp r5, r4
80042d2: d109 bne.n 80042e8 <__libc_init_array+0x24>
80042d4: 4e0b ldr r6, [pc, #44] ; (8004304 <__libc_init_array+0x40>)
80042d6: 4c0c ldr r4, [pc, #48] ; (8004308 <__libc_init_array+0x44>)
80042d8: f000 f8c8 bl 800446c <_init>
80042dc: 1ba4 subs r4, r4, r6
80042de: 10a4 asrs r4, r4, #2
80042e0: 2500 movs r5, #0
80042e2: 42a5 cmp r5, r4
80042e4: d105 bne.n 80042f2 <__libc_init_array+0x2e>
80042e6: bd70 pop {r4, r5, r6, pc}
80042e8: f856 3025 ldr.w r3, [r6, r5, lsl #2]
80042ec: 4798 blx r3
80042ee: 3501 adds r5, #1
80042f0: e7ee b.n 80042d0 <__libc_init_array+0xc>
80042f2: f856 3025 ldr.w r3, [r6, r5, lsl #2]
80042f6: 4798 blx r3
80042f8: 3501 adds r5, #1
80042fa: e7f2 b.n 80042e2 <__libc_init_array+0x1e>
80042fc: 0800449c .word 0x0800449c
8004300: 0800449c .word 0x0800449c
8004304: 0800449c .word 0x0800449c
8004308: 080044a0 .word 0x080044a0
0800430c <memset>:
800430c: 4402 add r2, r0
800430e: 4603 mov r3, r0
8004310: 4293 cmp r3, r2
8004312: d100 bne.n 8004316 <memset+0xa>
8004314: 4770 bx lr
8004316: f803 1b01 strb.w r1, [r3], #1
800431a: e7f9 b.n 8004310 <memset+0x4>
0800431c <rand>:
800431c: b538 push {r3, r4, r5, lr}
800431e: 4b13 ldr r3, [pc, #76] ; (800436c <rand+0x50>)
8004320: 681c ldr r4, [r3, #0]
8004322: 6ba3 ldr r3, [r4, #56] ; 0x38
8004324: b97b cbnz r3, 8004346 <rand+0x2a>
8004326: 2018 movs r0, #24
8004328: f000 f82c bl 8004384 <malloc>
800432c: 4a10 ldr r2, [pc, #64] ; (8004370 <rand+0x54>)
800432e: 4b11 ldr r3, [pc, #68] ; (8004374 <rand+0x58>)
8004330: 63a0 str r0, [r4, #56] ; 0x38
8004332: e9c0 2300 strd r2, r3, [r0]
8004336: 4b10 ldr r3, [pc, #64] ; (8004378 <rand+0x5c>)
8004338: 6083 str r3, [r0, #8]
800433a: 230b movs r3, #11
800433c: 8183 strh r3, [r0, #12]
800433e: 2201 movs r2, #1
8004340: 2300 movs r3, #0
8004342: e9c0 2304 strd r2, r3, [r0, #16]
8004346: 6ba1 ldr r1, [r4, #56] ; 0x38
8004348: 480c ldr r0, [pc, #48] ; (800437c <rand+0x60>)
800434a: 690a ldr r2, [r1, #16]
800434c: 694b ldr r3, [r1, #20]
800434e: 4c0c ldr r4, [pc, #48] ; (8004380 <rand+0x64>)
8004350: 4350 muls r0, r2
8004352: fb04 0003 mla r0, r4, r3, r0
8004356: fba2 2304 umull r2, r3, r2, r4
800435a: 4403 add r3, r0
800435c: 1c54 adds r4, r2, #1
800435e: f143 0500 adc.w r5, r3, #0
8004362: e9c1 4504 strd r4, r5, [r1, #16]
8004366: f025 4000 bic.w r0, r5, #2147483648 ; 0x80000000
800436a: bd38 pop {r3, r4, r5, pc}
800436c: 20000010 .word 0x20000010
8004370: abcd330e .word 0xabcd330e
8004374: e66d1234 .word 0xe66d1234
8004378: 0005deec .word 0x0005deec
800437c: 5851f42d .word 0x5851f42d
8004380: 4c957f2d .word 0x4c957f2d
08004384 <malloc>:
8004384: 4b02 ldr r3, [pc, #8] ; (8004390 <malloc+0xc>)
8004386: 4601 mov r1, r0
8004388: 6818 ldr r0, [r3, #0]
800438a: f000 b803 b.w 8004394 <_malloc_r>
800438e: bf00 nop
8004390: 20000010 .word 0x20000010
08004394 <_malloc_r>:
8004394: b570 push {r4, r5, r6, lr}
8004396: 1ccd adds r5, r1, #3
8004398: f025 0503 bic.w r5, r5, #3
800439c: 3508 adds r5, #8
800439e: 2d0c cmp r5, #12
80043a0: bf38 it cc
80043a2: 250c movcc r5, #12
80043a4: 2d00 cmp r5, #0
80043a6: 4606 mov r6, r0
80043a8: db01 blt.n 80043ae <_malloc_r+0x1a>
80043aa: 42a9 cmp r1, r5
80043ac: d903 bls.n 80043b6 <_malloc_r+0x22>
80043ae: 230c movs r3, #12
80043b0: 6033 str r3, [r6, #0]
80043b2: 2000 movs r0, #0
80043b4: bd70 pop {r4, r5, r6, pc}
80043b6: f000 f857 bl 8004468 <__malloc_lock>
80043ba: 4a21 ldr r2, [pc, #132] ; (8004440 <_malloc_r+0xac>)
80043bc: 6814 ldr r4, [r2, #0]
80043be: 4621 mov r1, r4
80043c0: b991 cbnz r1, 80043e8 <_malloc_r+0x54>
80043c2: 4c20 ldr r4, [pc, #128] ; (8004444 <_malloc_r+0xb0>)
80043c4: 6823 ldr r3, [r4, #0]
80043c6: b91b cbnz r3, 80043d0 <_malloc_r+0x3c>
80043c8: 4630 mov r0, r6
80043ca: f000 f83d bl 8004448 <_sbrk_r>
80043ce: 6020 str r0, [r4, #0]
80043d0: 4629 mov r1, r5
80043d2: 4630 mov r0, r6
80043d4: f000 f838 bl 8004448 <_sbrk_r>
80043d8: 1c43 adds r3, r0, #1
80043da: d124 bne.n 8004426 <_malloc_r+0x92>
80043dc: 230c movs r3, #12
80043de: 6033 str r3, [r6, #0]
80043e0: 4630 mov r0, r6
80043e2: f000 f842 bl 800446a <__malloc_unlock>
80043e6: e7e4 b.n 80043b2 <_malloc_r+0x1e>
80043e8: 680b ldr r3, [r1, #0]
80043ea: 1b5b subs r3, r3, r5
80043ec: d418 bmi.n 8004420 <_malloc_r+0x8c>
80043ee: 2b0b cmp r3, #11
80043f0: d90f bls.n 8004412 <_malloc_r+0x7e>
80043f2: 600b str r3, [r1, #0]
80043f4: 50cd str r5, [r1, r3]
80043f6: 18cc adds r4, r1, r3
80043f8: 4630 mov r0, r6
80043fa: f000 f836 bl 800446a <__malloc_unlock>
80043fe: f104 000b add.w r0, r4, #11
8004402: 1d23 adds r3, r4, #4
8004404: f020 0007 bic.w r0, r0, #7
8004408: 1ac3 subs r3, r0, r3
800440a: d0d3 beq.n 80043b4 <_malloc_r+0x20>
800440c: 425a negs r2, r3
800440e: 50e2 str r2, [r4, r3]
8004410: e7d0 b.n 80043b4 <_malloc_r+0x20>
8004412: 428c cmp r4, r1
8004414: 684b ldr r3, [r1, #4]
8004416: bf16 itet ne
8004418: 6063 strne r3, [r4, #4]
800441a: 6013 streq r3, [r2, #0]
800441c: 460c movne r4, r1
800441e: e7eb b.n 80043f8 <_malloc_r+0x64>
8004420: 460c mov r4, r1
8004422: 6849 ldr r1, [r1, #4]
8004424: e7cc b.n 80043c0 <_malloc_r+0x2c>
8004426: 1cc4 adds r4, r0, #3
8004428: f024 0403 bic.w r4, r4, #3
800442c: 42a0 cmp r0, r4
800442e: d005 beq.n 800443c <_malloc_r+0xa8>
8004430: 1a21 subs r1, r4, r0
8004432: 4630 mov r0, r6
8004434: f000 f808 bl 8004448 <_sbrk_r>
8004438: 3001 adds r0, #1
800443a: d0cf beq.n 80043dc <_malloc_r+0x48>
800443c: 6025 str r5, [r4, #0]
800443e: e7db b.n 80043f8 <_malloc_r+0x64>
8004440: 200003b0 .word 0x200003b0
8004444: 200003b4 .word 0x200003b4
08004448 <_sbrk_r>:
8004448: b538 push {r3, r4, r5, lr}
800444a: 4c06 ldr r4, [pc, #24] ; (8004464 <_sbrk_r+0x1c>)
800444c: 2300 movs r3, #0
800444e: 4605 mov r5, r0
8004450: 4608 mov r0, r1
8004452: 6023 str r3, [r4, #0]
8004454: f7fd fcb0 bl 8001db8 <_sbrk>
8004458: 1c43 adds r3, r0, #1
800445a: d102 bne.n 8004462 <_sbrk_r+0x1a>
800445c: 6823 ldr r3, [r4, #0]
800445e: b103 cbz r3, 8004462 <_sbrk_r+0x1a>
8004460: 602b str r3, [r5, #0]
8004462: bd38 pop {r3, r4, r5, pc}
8004464: 200004a0 .word 0x200004a0
08004468 <__malloc_lock>:
8004468: 4770 bx lr
0800446a <__malloc_unlock>:
800446a: 4770 bx lr
0800446c <_init>:
800446c: b5f8 push {r3, r4, r5, r6, r7, lr}
800446e: bf00 nop
8004470: bcf8 pop {r3, r4, r5, r6, r7}
8004472: bc08 pop {r3}
8004474: 469e mov lr, r3
8004476: 4770 bx lr
08004478 <_fini>:
8004478: b5f8 push {r3, r4, r5, r6, r7, lr}
800447a: bf00 nop
800447c: bcf8 pop {r3, r4, r5, r6, r7}
800447e: bc08 pop {r3}
8004480: 469e mov lr, r3
8004482: 4770 bx lr
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