William/LED-Face-Mask
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c2f788aa3e0974ef08eeab3b12718aa079574d30
LED-Face-Mask/Debug/STM32F429I-DISC1_LEDFaceMask.list
William Miceli c2f788aa3e Initial Commit 
Blank working project
2020-08-05 17:53:34 -04:00

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469 KiB
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STM32F429I-DISC1_LEDFaceMask.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 000001ac 08000000 08000000 00010000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00004a18 080001ac 080001ac 000101ac 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000018 08004bc4 08004bc4 00014bc4 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08004bdc 08004bdc 0002000c 2**0
CONTENTS
4 .ARM 00000008 08004bdc 08004bdc 00014bdc 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .preinit_array 00000000 08004be4 08004be4 0002000c 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08004be4 08004be4 00014be4 2**2
CONTENTS, ALLOC, LOAD, DATA
7 .fini_array 00000004 08004be8 08004be8 00014be8 2**2
CONTENTS, ALLOC, LOAD, DATA
8 .data 0000000c 20000000 08004bec 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 0000031c 2000000c 08004bf8 0002000c 2**2
ALLOC
10 ._user_heap_stack 00000600 20000328 08004bf8 00020328 2**0
ALLOC
11 .ARM.attributes 00000030 00000000 00000000 0002000c 2**0
CONTENTS, READONLY
12 .debug_info 00015f6c 00000000 00000000 0002003c 2**0
CONTENTS, READONLY, DEBUGGING
13 .debug_abbrev 00002aef 00000000 00000000 00035fa8 2**0
CONTENTS, READONLY, DEBUGGING
14 .debug_aranges 00001600 00000000 00000000 00038a98 2**3
CONTENTS, READONLY, DEBUGGING
15 .debug_ranges 000014b8 00000000 00000000 0003a098 2**3
CONTENTS, READONLY, DEBUGGING
16 .debug_macro 00025759 00000000 00000000 0003b550 2**0
CONTENTS, READONLY, DEBUGGING
17 .debug_line 00011cc1 00000000 00000000 00060ca9 2**0
CONTENTS, READONLY, DEBUGGING
18 .debug_str 000e0efd 00000000 00000000 0007296a 2**0
CONTENTS, READONLY, DEBUGGING
19 .comment 0000007b 00000000 00000000 00153867 2**0
CONTENTS, READONLY
20 .debug_frame 00005e70 00000000 00000000 001538e4 2**2
CONTENTS, READONLY, DEBUGGING
Disassembly of section .text:
080001ac <__do_global_dtors_aux>:
80001ac: b510 push {r4, lr}
80001ae: 4c05 ldr r4, [pc, #20] ; (80001c4 <__do_global_dtors_aux+0x18>)
80001b0: 7823 ldrb r3, [r4, #0]
80001b2: b933 cbnz r3, 80001c2 <__do_global_dtors_aux+0x16>
80001b4: 4b04 ldr r3, [pc, #16] ; (80001c8 <__do_global_dtors_aux+0x1c>)
80001b6: b113 cbz r3, 80001be <__do_global_dtors_aux+0x12>
80001b8: 4804 ldr r0, [pc, #16] ; (80001cc <__do_global_dtors_aux+0x20>)
80001ba: f3af 8000 nop.w
80001be: 2301 movs r3, #1
80001c0: 7023 strb r3, [r4, #0]
80001c2: bd10 pop {r4, pc}
80001c4: 2000000c .word 0x2000000c
80001c8: 00000000 .word 0x00000000
80001cc: 08004bac .word 0x08004bac
080001d0 <frame_dummy>:
80001d0: b508 push {r3, lr}
80001d2: 4b03 ldr r3, [pc, #12] ; (80001e0 <frame_dummy+0x10>)
80001d4: b11b cbz r3, 80001de <frame_dummy+0xe>
80001d6: 4903 ldr r1, [pc, #12] ; (80001e4 <frame_dummy+0x14>)
80001d8: 4803 ldr r0, [pc, #12] ; (80001e8 <frame_dummy+0x18>)
80001da: f3af 8000 nop.w
80001de: bd08 pop {r3, pc}
80001e0: 00000000 .word 0x00000000
80001e4: 20000010 .word 0x20000010
80001e8: 08004bac .word 0x08004bac
080001ec <__aeabi_uldivmod>:
80001ec: b953 cbnz r3, 8000204 <__aeabi_uldivmod+0x18>
80001ee: b94a cbnz r2, 8000204 <__aeabi_uldivmod+0x18>
80001f0: 2900 cmp r1, #0
80001f2: bf08 it eq
80001f4: 2800 cmpeq r0, #0
80001f6: bf1c itt ne
80001f8: f04f 31ff movne.w r1, #4294967295
80001fc: f04f 30ff movne.w r0, #4294967295
8000200: f000 b972 b.w 80004e8 <__aeabi_idiv0>
8000204: f1ad 0c08 sub.w ip, sp, #8
8000208: e96d ce04 strd ip, lr, [sp, #-16]!
800020c: f000 f806 bl 800021c <__udivmoddi4>
8000210: f8dd e004 ldr.w lr, [sp, #4]
8000214: e9dd 2302 ldrd r2, r3, [sp, #8]
8000218: b004 add sp, #16
800021a: 4770 bx lr
0800021c <__udivmoddi4>:
800021c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
8000220: 9e08 ldr r6, [sp, #32]
8000222: 4604 mov r4, r0
8000224: 4688 mov r8, r1
8000226: 2b00 cmp r3, #0
8000228: d14b bne.n 80002c2 <__udivmoddi4+0xa6>
800022a: 428a cmp r2, r1
800022c: 4615 mov r5, r2
800022e: d967 bls.n 8000300 <__udivmoddi4+0xe4>
8000230: fab2 f282 clz r2, r2
8000234: b14a cbz r2, 800024a <__udivmoddi4+0x2e>
8000236: f1c2 0720 rsb r7, r2, #32
800023a: fa01 f302 lsl.w r3, r1, r2
800023e: fa20 f707 lsr.w r7, r0, r7
8000242: 4095 lsls r5, r2
8000244: ea47 0803 orr.w r8, r7, r3
8000248: 4094 lsls r4, r2
800024a: ea4f 4e15 mov.w lr, r5, lsr #16
800024e: 0c23 lsrs r3, r4, #16
8000250: fbb8 f7fe udiv r7, r8, lr
8000254: fa1f fc85 uxth.w ip, r5
8000258: fb0e 8817 mls r8, lr, r7, r8
800025c: ea43 4308 orr.w r3, r3, r8, lsl #16
8000260: fb07 f10c mul.w r1, r7, ip
8000264: 4299 cmp r1, r3
8000266: d909 bls.n 800027c <__udivmoddi4+0x60>
8000268: 18eb adds r3, r5, r3
800026a: f107 30ff add.w r0, r7, #4294967295
800026e: f080 811b bcs.w 80004a8 <__udivmoddi4+0x28c>
8000272: 4299 cmp r1, r3
8000274: f240 8118 bls.w 80004a8 <__udivmoddi4+0x28c>
8000278: 3f02 subs r7, #2
800027a: 442b add r3, r5
800027c: 1a5b subs r3, r3, r1
800027e: b2a4 uxth r4, r4
8000280: fbb3 f0fe udiv r0, r3, lr
8000284: fb0e 3310 mls r3, lr, r0, r3
8000288: ea44 4403 orr.w r4, r4, r3, lsl #16
800028c: fb00 fc0c mul.w ip, r0, ip
8000290: 45a4 cmp ip, r4
8000292: d909 bls.n 80002a8 <__udivmoddi4+0x8c>
8000294: 192c adds r4, r5, r4
8000296: f100 33ff add.w r3, r0, #4294967295
800029a: f080 8107 bcs.w 80004ac <__udivmoddi4+0x290>
800029e: 45a4 cmp ip, r4
80002a0: f240 8104 bls.w 80004ac <__udivmoddi4+0x290>
80002a4: 3802 subs r0, #2
80002a6: 442c add r4, r5
80002a8: ea40 4007 orr.w r0, r0, r7, lsl #16
80002ac: eba4 040c sub.w r4, r4, ip
80002b0: 2700 movs r7, #0
80002b2: b11e cbz r6, 80002bc <__udivmoddi4+0xa0>
80002b4: 40d4 lsrs r4, r2
80002b6: 2300 movs r3, #0
80002b8: e9c6 4300 strd r4, r3, [r6]
80002bc: 4639 mov r1, r7
80002be: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
80002c2: 428b cmp r3, r1
80002c4: d909 bls.n 80002da <__udivmoddi4+0xbe>
80002c6: 2e00 cmp r6, #0
80002c8: f000 80eb beq.w 80004a2 <__udivmoddi4+0x286>
80002cc: 2700 movs r7, #0
80002ce: e9c6 0100 strd r0, r1, [r6]
80002d2: 4638 mov r0, r7
80002d4: 4639 mov r1, r7
80002d6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
80002da: fab3 f783 clz r7, r3
80002de: 2f00 cmp r7, #0
80002e0: d147 bne.n 8000372 <__udivmoddi4+0x156>
80002e2: 428b cmp r3, r1
80002e4: d302 bcc.n 80002ec <__udivmoddi4+0xd0>
80002e6: 4282 cmp r2, r0
80002e8: f200 80fa bhi.w 80004e0 <__udivmoddi4+0x2c4>
80002ec: 1a84 subs r4, r0, r2
80002ee: eb61 0303 sbc.w r3, r1, r3
80002f2: 2001 movs r0, #1
80002f4: 4698 mov r8, r3
80002f6: 2e00 cmp r6, #0
80002f8: d0e0 beq.n 80002bc <__udivmoddi4+0xa0>
80002fa: e9c6 4800 strd r4, r8, [r6]
80002fe: e7dd b.n 80002bc <__udivmoddi4+0xa0>
8000300: b902 cbnz r2, 8000304 <__udivmoddi4+0xe8>
8000302: deff udf #255 ; 0xff
8000304: fab2 f282 clz r2, r2
8000308: 2a00 cmp r2, #0
800030a: f040 808f bne.w 800042c <__udivmoddi4+0x210>
800030e: 1b49 subs r1, r1, r5
8000310: ea4f 4e15 mov.w lr, r5, lsr #16
8000314: fa1f f885 uxth.w r8, r5
8000318: 2701 movs r7, #1
800031a: fbb1 fcfe udiv ip, r1, lr
800031e: 0c23 lsrs r3, r4, #16
8000320: fb0e 111c mls r1, lr, ip, r1
8000324: ea43 4301 orr.w r3, r3, r1, lsl #16
8000328: fb08 f10c mul.w r1, r8, ip
800032c: 4299 cmp r1, r3
800032e: d907 bls.n 8000340 <__udivmoddi4+0x124>
8000330: 18eb adds r3, r5, r3
8000332: f10c 30ff add.w r0, ip, #4294967295
8000336: d202 bcs.n 800033e <__udivmoddi4+0x122>
8000338: 4299 cmp r1, r3
800033a: f200 80cd bhi.w 80004d8 <__udivmoddi4+0x2bc>
800033e: 4684 mov ip, r0
8000340: 1a59 subs r1, r3, r1
8000342: b2a3 uxth r3, r4
8000344: fbb1 f0fe udiv r0, r1, lr
8000348: fb0e 1410 mls r4, lr, r0, r1
800034c: ea43 4404 orr.w r4, r3, r4, lsl #16
8000350: fb08 f800 mul.w r8, r8, r0
8000354: 45a0 cmp r8, r4
8000356: d907 bls.n 8000368 <__udivmoddi4+0x14c>
8000358: 192c adds r4, r5, r4
800035a: f100 33ff add.w r3, r0, #4294967295
800035e: d202 bcs.n 8000366 <__udivmoddi4+0x14a>
8000360: 45a0 cmp r8, r4
8000362: f200 80b6 bhi.w 80004d2 <__udivmoddi4+0x2b6>
8000366: 4618 mov r0, r3
8000368: eba4 0408 sub.w r4, r4, r8
800036c: ea40 400c orr.w r0, r0, ip, lsl #16
8000370: e79f b.n 80002b2 <__udivmoddi4+0x96>
8000372: f1c7 0c20 rsb ip, r7, #32
8000376: 40bb lsls r3, r7
8000378: fa22 fe0c lsr.w lr, r2, ip
800037c: ea4e 0e03 orr.w lr, lr, r3
8000380: fa01 f407 lsl.w r4, r1, r7
8000384: fa20 f50c lsr.w r5, r0, ip
8000388: fa21 f30c lsr.w r3, r1, ip
800038c: ea4f 481e mov.w r8, lr, lsr #16
8000390: 4325 orrs r5, r4
8000392: fbb3 f9f8 udiv r9, r3, r8
8000396: 0c2c lsrs r4, r5, #16
8000398: fb08 3319 mls r3, r8, r9, r3
800039c: fa1f fa8e uxth.w sl, lr
80003a0: ea44 4303 orr.w r3, r4, r3, lsl #16
80003a4: fb09 f40a mul.w r4, r9, sl
80003a8: 429c cmp r4, r3
80003aa: fa02 f207 lsl.w r2, r2, r7
80003ae: fa00 f107 lsl.w r1, r0, r7
80003b2: d90b bls.n 80003cc <__udivmoddi4+0x1b0>
80003b4: eb1e 0303 adds.w r3, lr, r3
80003b8: f109 30ff add.w r0, r9, #4294967295
80003bc: f080 8087 bcs.w 80004ce <__udivmoddi4+0x2b2>
80003c0: 429c cmp r4, r3
80003c2: f240 8084 bls.w 80004ce <__udivmoddi4+0x2b2>
80003c6: f1a9 0902 sub.w r9, r9, #2
80003ca: 4473 add r3, lr
80003cc: 1b1b subs r3, r3, r4
80003ce: b2ad uxth r5, r5
80003d0: fbb3 f0f8 udiv r0, r3, r8
80003d4: fb08 3310 mls r3, r8, r0, r3
80003d8: ea45 4403 orr.w r4, r5, r3, lsl #16
80003dc: fb00 fa0a mul.w sl, r0, sl
80003e0: 45a2 cmp sl, r4
80003e2: d908 bls.n 80003f6 <__udivmoddi4+0x1da>
80003e4: eb1e 0404 adds.w r4, lr, r4
80003e8: f100 33ff add.w r3, r0, #4294967295
80003ec: d26b bcs.n 80004c6 <__udivmoddi4+0x2aa>
80003ee: 45a2 cmp sl, r4
80003f0: d969 bls.n 80004c6 <__udivmoddi4+0x2aa>
80003f2: 3802 subs r0, #2
80003f4: 4474 add r4, lr
80003f6: ea40 4009 orr.w r0, r0, r9, lsl #16
80003fa: fba0 8902 umull r8, r9, r0, r2
80003fe: eba4 040a sub.w r4, r4, sl
8000402: 454c cmp r4, r9
8000404: 46c2 mov sl, r8
8000406: 464b mov r3, r9
8000408: d354 bcc.n 80004b4 <__udivmoddi4+0x298>
800040a: d051 beq.n 80004b0 <__udivmoddi4+0x294>
800040c: 2e00 cmp r6, #0
800040e: d069 beq.n 80004e4 <__udivmoddi4+0x2c8>
8000410: ebb1 050a subs.w r5, r1, sl
8000414: eb64 0403 sbc.w r4, r4, r3
8000418: fa04 fc0c lsl.w ip, r4, ip
800041c: 40fd lsrs r5, r7
800041e: 40fc lsrs r4, r7
8000420: ea4c 0505 orr.w r5, ip, r5
8000424: e9c6 5400 strd r5, r4, [r6]
8000428: 2700 movs r7, #0
800042a: e747 b.n 80002bc <__udivmoddi4+0xa0>
800042c: f1c2 0320 rsb r3, r2, #32
8000430: fa20 f703 lsr.w r7, r0, r3
8000434: 4095 lsls r5, r2
8000436: fa01 f002 lsl.w r0, r1, r2
800043a: fa21 f303 lsr.w r3, r1, r3
800043e: ea4f 4e15 mov.w lr, r5, lsr #16
8000442: 4338 orrs r0, r7
8000444: 0c01 lsrs r1, r0, #16
8000446: fbb3 f7fe udiv r7, r3, lr
800044a: fa1f f885 uxth.w r8, r5
800044e: fb0e 3317 mls r3, lr, r7, r3
8000452: ea41 4103 orr.w r1, r1, r3, lsl #16
8000456: fb07 f308 mul.w r3, r7, r8
800045a: 428b cmp r3, r1
800045c: fa04 f402 lsl.w r4, r4, r2
8000460: d907 bls.n 8000472 <__udivmoddi4+0x256>
8000462: 1869 adds r1, r5, r1
8000464: f107 3cff add.w ip, r7, #4294967295
8000468: d22f bcs.n 80004ca <__udivmoddi4+0x2ae>
800046a: 428b cmp r3, r1
800046c: d92d bls.n 80004ca <__udivmoddi4+0x2ae>
800046e: 3f02 subs r7, #2
8000470: 4429 add r1, r5
8000472: 1acb subs r3, r1, r3
8000474: b281 uxth r1, r0
8000476: fbb3 f0fe udiv r0, r3, lr
800047a: fb0e 3310 mls r3, lr, r0, r3
800047e: ea41 4103 orr.w r1, r1, r3, lsl #16
8000482: fb00 f308 mul.w r3, r0, r8
8000486: 428b cmp r3, r1
8000488: d907 bls.n 800049a <__udivmoddi4+0x27e>
800048a: 1869 adds r1, r5, r1
800048c: f100 3cff add.w ip, r0, #4294967295
8000490: d217 bcs.n 80004c2 <__udivmoddi4+0x2a6>
8000492: 428b cmp r3, r1
8000494: d915 bls.n 80004c2 <__udivmoddi4+0x2a6>
8000496: 3802 subs r0, #2
8000498: 4429 add r1, r5
800049a: 1ac9 subs r1, r1, r3
800049c: ea40 4707 orr.w r7, r0, r7, lsl #16
80004a0: e73b b.n 800031a <__udivmoddi4+0xfe>
80004a2: 4637 mov r7, r6
80004a4: 4630 mov r0, r6
80004a6: e709 b.n 80002bc <__udivmoddi4+0xa0>
80004a8: 4607 mov r7, r0
80004aa: e6e7 b.n 800027c <__udivmoddi4+0x60>
80004ac: 4618 mov r0, r3
80004ae: e6fb b.n 80002a8 <__udivmoddi4+0x8c>
80004b0: 4541 cmp r1, r8
80004b2: d2ab bcs.n 800040c <__udivmoddi4+0x1f0>
80004b4: ebb8 0a02 subs.w sl, r8, r2
80004b8: eb69 020e sbc.w r2, r9, lr
80004bc: 3801 subs r0, #1
80004be: 4613 mov r3, r2
80004c0: e7a4 b.n 800040c <__udivmoddi4+0x1f0>
80004c2: 4660 mov r0, ip
80004c4: e7e9 b.n 800049a <__udivmoddi4+0x27e>
80004c6: 4618 mov r0, r3
80004c8: e795 b.n 80003f6 <__udivmoddi4+0x1da>
80004ca: 4667 mov r7, ip
80004cc: e7d1 b.n 8000472 <__udivmoddi4+0x256>
80004ce: 4681 mov r9, r0
80004d0: e77c b.n 80003cc <__udivmoddi4+0x1b0>
80004d2: 3802 subs r0, #2
80004d4: 442c add r4, r5
80004d6: e747 b.n 8000368 <__udivmoddi4+0x14c>
80004d8: f1ac 0c02 sub.w ip, ip, #2
80004dc: 442b add r3, r5
80004de: e72f b.n 8000340 <__udivmoddi4+0x124>
80004e0: 4638 mov r0, r7
80004e2: e708 b.n 80002f6 <__udivmoddi4+0xda>
80004e4: 4637 mov r7, r6
80004e6: e6e9 b.n 80002bc <__udivmoddi4+0xa0>
080004e8 <__aeabi_idiv0>:
80004e8: 4770 bx lr
80004ea: bf00 nop
080004ec <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
80004ec: b580 push {r7, lr}
80004ee: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
80004f0: f001 f8e8 bl 80016c4 <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
80004f4: f000 f824 bl 8000540 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
80004f8: f000 faf4 bl 8000ae4 <MX_GPIO_Init>
MX_CRC_Init();
80004fc: f000 f8a2 bl 8000644 <MX_CRC_Init>
MX_DMA2D_Init();
8000500: f000 f8b4 bl 800066c <MX_DMA2D_Init>
MX_FMC_Init();
8000504: f000 fa9e bl 8000a44 <MX_FMC_Init>
MX_I2C3_Init();
8000508: f000 f8e2 bl 80006d0 <MX_I2C3_Init>
MX_LTDC_Init();
800050c: f000 f920 bl 8000750 <MX_LTDC_Init>
MX_SPI5_Init();
8000510: f000 f9e8 bl 80008e4 <MX_SPI5_Init>
MX_TIM1_Init();
8000514: f000 fa1c bl 8000950 <MX_TIM1_Init>
MX_USART1_UART_Init();
8000518: f000 fa6a bl 80009f0 <MX_USART1_UART_Init>
MX_RNG_Init();
800051c: f000 f998 bl 8000850 <MX_RNG_Init>
MX_SPI4_Init();
8000520: f000 f9aa bl 8000878 <MX_SPI4_Init>
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
{
HAL_GPIO_WritePin(GPIOF, GPIO_PIN_6, GPIO_PIN_SET);
8000524: 2201 movs r2, #1
8000526: 2140 movs r1, #64 ; 0x40
8000528: 4804 ldr r0, [pc, #16] ; (800053c <main+0x50>)
800052a: f001 fda1 bl 8002070 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(GPIOF, GPIO_PIN_6, GPIO_PIN_RESET);
800052e: 2200 movs r2, #0
8000530: 2140 movs r1, #64 ; 0x40
8000532: 4802 ldr r0, [pc, #8] ; (800053c <main+0x50>)
8000534: f001 fd9c bl 8002070 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(GPIOF, GPIO_PIN_6, GPIO_PIN_SET);
8000538: e7f4 b.n 8000524 <main+0x38>
800053a: bf00 nop
800053c: 40021400 .word 0x40021400
08000540 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
8000540: b580 push {r7, lr}
8000542: b0a0 sub sp, #128 ; 0x80
8000544: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
8000546: f107 0350 add.w r3, r7, #80 ; 0x50
800054a: 2230 movs r2, #48 ; 0x30
800054c: 2100 movs r1, #0
800054e: 4618 mov r0, r3
8000550: f004 fb24 bl 8004b9c <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
8000554: f107 033c add.w r3, r7, #60 ; 0x3c
8000558: 2200 movs r2, #0
800055a: 601a str r2, [r3, #0]
800055c: 605a str r2, [r3, #4]
800055e: 609a str r2, [r3, #8]
8000560: 60da str r2, [r3, #12]
8000562: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
8000564: f107 030c add.w r3, r7, #12
8000568: 2230 movs r2, #48 ; 0x30
800056a: 2100 movs r1, #0
800056c: 4618 mov r0, r3
800056e: f004 fb15 bl 8004b9c <memset>
/** Configure the main internal regulator output voltage
*/
__HAL_RCC_PWR_CLK_ENABLE();
8000572: 2300 movs r3, #0
8000574: 60bb str r3, [r7, #8]
8000576: 4b31 ldr r3, [pc, #196] ; (800063c <SystemClock_Config+0xfc>)
8000578: 6c1b ldr r3, [r3, #64] ; 0x40
800057a: 4a30 ldr r2, [pc, #192] ; (800063c <SystemClock_Config+0xfc>)
800057c: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8000580: 6413 str r3, [r2, #64] ; 0x40
8000582: 4b2e ldr r3, [pc, #184] ; (800063c <SystemClock_Config+0xfc>)
8000584: 6c1b ldr r3, [r3, #64] ; 0x40
8000586: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
800058a: 60bb str r3, [r7, #8]
800058c: 68bb ldr r3, [r7, #8]
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
800058e: 2300 movs r3, #0
8000590: 607b str r3, [r7, #4]
8000592: 4b2b ldr r3, [pc, #172] ; (8000640 <SystemClock_Config+0x100>)
8000594: 681b ldr r3, [r3, #0]
8000596: 4a2a ldr r2, [pc, #168] ; (8000640 <SystemClock_Config+0x100>)
8000598: f443 4340 orr.w r3, r3, #49152 ; 0xc000
800059c: 6013 str r3, [r2, #0]
800059e: 4b28 ldr r3, [pc, #160] ; (8000640 <SystemClock_Config+0x100>)
80005a0: 681b ldr r3, [r3, #0]
80005a2: f403 4340 and.w r3, r3, #49152 ; 0xc000
80005a6: 607b str r3, [r7, #4]
80005a8: 687b ldr r3, [r7, #4]
/** Initializes the CPU, AHB and APB busses clocks
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
80005aa: 2301 movs r3, #1
80005ac: 653b str r3, [r7, #80] ; 0x50
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
80005ae: f44f 3380 mov.w r3, #65536 ; 0x10000
80005b2: 657b str r3, [r7, #84] ; 0x54
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
80005b4: 2302 movs r3, #2
80005b6: 66bb str r3, [r7, #104] ; 0x68
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
80005b8: f44f 0380 mov.w r3, #4194304 ; 0x400000
80005bc: 66fb str r3, [r7, #108] ; 0x6c
RCC_OscInitStruct.PLL.PLLM = 4;
80005be: 2304 movs r3, #4
80005c0: 673b str r3, [r7, #112] ; 0x70
RCC_OscInitStruct.PLL.PLLN = 144;
80005c2: 2390 movs r3, #144 ; 0x90
80005c4: 677b str r3, [r7, #116] ; 0x74
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
80005c6: 2302 movs r3, #2
80005c8: 67bb str r3, [r7, #120] ; 0x78
RCC_OscInitStruct.PLL.PLLQ = 6;
80005ca: 2306 movs r3, #6
80005cc: 67fb str r3, [r7, #124] ; 0x7c
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
80005ce: f107 0350 add.w r3, r7, #80 ; 0x50
80005d2: 4618 mov r0, r3
80005d4: f002 fa82 bl 8002adc <HAL_RCC_OscConfig>
80005d8: 4603 mov r3, r0
80005da: 2b00 cmp r3, #0
80005dc: d001 beq.n 80005e2 <SystemClock_Config+0xa2>
{
Error_Handler();
80005de: f000 fbd5 bl 8000d8c <Error_Handler>
}
/** Initializes the CPU, AHB and APB busses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
80005e2: 230f movs r3, #15
80005e4: 63fb str r3, [r7, #60] ; 0x3c
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
80005e6: 2302 movs r3, #2
80005e8: 643b str r3, [r7, #64] ; 0x40
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
80005ea: 2300 movs r3, #0
80005ec: 647b str r3, [r7, #68] ; 0x44
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
80005ee: f44f 53a0 mov.w r3, #5120 ; 0x1400
80005f2: 64bb str r3, [r7, #72] ; 0x48
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
80005f4: f44f 5380 mov.w r3, #4096 ; 0x1000
80005f8: 64fb str r3, [r7, #76] ; 0x4c
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
80005fa: f107 033c add.w r3, r7, #60 ; 0x3c
80005fe: 2104 movs r1, #4
8000600: 4618 mov r0, r3
8000602: f002 fcdb bl 8002fbc <HAL_RCC_ClockConfig>
8000606: 4603 mov r3, r0
8000608: 2b00 cmp r3, #0
800060a: d001 beq.n 8000610 <SystemClock_Config+0xd0>
{
Error_Handler();
800060c: f000 fbbe bl 8000d8c <Error_Handler>
}
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LTDC;
8000610: 2308 movs r3, #8
8000612: 60fb str r3, [r7, #12]
PeriphClkInitStruct.PLLSAI.PLLSAIN = 50;
8000614: 2332 movs r3, #50 ; 0x32
8000616: 61fb str r3, [r7, #28]
PeriphClkInitStruct.PLLSAI.PLLSAIR = 2;
8000618: 2302 movs r3, #2
800061a: 627b str r3, [r7, #36] ; 0x24
PeriphClkInitStruct.PLLSAIDivR = RCC_PLLSAIDIVR_2;
800061c: 2300 movs r3, #0
800061e: 633b str r3, [r7, #48] ; 0x30
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
8000620: f107 030c add.w r3, r7, #12
8000624: 4618 mov r0, r3
8000626: f002 feed bl 8003404 <HAL_RCCEx_PeriphCLKConfig>
800062a: 4603 mov r3, r0
800062c: 2b00 cmp r3, #0
800062e: d001 beq.n 8000634 <SystemClock_Config+0xf4>
{
Error_Handler();
8000630: f000 fbac bl 8000d8c <Error_Handler>
}
}
8000634: bf00 nop
8000636: 3780 adds r7, #128 ; 0x80
8000638: 46bd mov sp, r7
800063a: bd80 pop {r7, pc}
800063c: 40023800 .word 0x40023800
8000640: 40007000 .word 0x40007000
08000644 <MX_CRC_Init>:
* @brief CRC Initialization Function
* @param None
* @retval None
*/
static void MX_CRC_Init(void)
{
8000644: b580 push {r7, lr}
8000646: af00 add r7, sp, #0
/* USER CODE END CRC_Init 0 */
/* USER CODE BEGIN CRC_Init 1 */
/* USER CODE END CRC_Init 1 */
hcrc.Instance = CRC;
8000648: 4b06 ldr r3, [pc, #24] ; (8000664 <MX_CRC_Init+0x20>)
800064a: 4a07 ldr r2, [pc, #28] ; (8000668 <MX_CRC_Init+0x24>)
800064c: 601a str r2, [r3, #0]
if (HAL_CRC_Init(&hcrc) != HAL_OK)
800064e: 4805 ldr r0, [pc, #20] ; (8000664 <MX_CRC_Init+0x20>)
8000650: f001 f95c bl 800190c <HAL_CRC_Init>
8000654: 4603 mov r3, r0
8000656: 2b00 cmp r3, #0
8000658: d001 beq.n 800065e <MX_CRC_Init+0x1a>
{
Error_Handler();
800065a: f000 fb97 bl 8000d8c <Error_Handler>
}
/* USER CODE BEGIN CRC_Init 2 */
/* USER CODE END CRC_Init 2 */
}
800065e: bf00 nop
8000660: bd80 pop {r7, pc}
8000662: bf00 nop
8000664: 200000d8 .word 0x200000d8
8000668: 40023000 .word 0x40023000
0800066c <MX_DMA2D_Init>:
* @brief DMA2D Initialization Function
* @param None
* @retval None
*/
static void MX_DMA2D_Init(void)
{
800066c: b580 push {r7, lr}
800066e: af00 add r7, sp, #0
/* USER CODE END DMA2D_Init 0 */
/* USER CODE BEGIN DMA2D_Init 1 */
/* USER CODE END DMA2D_Init 1 */
hdma2d.Instance = DMA2D;
8000670: 4b15 ldr r3, [pc, #84] ; (80006c8 <MX_DMA2D_Init+0x5c>)
8000672: 4a16 ldr r2, [pc, #88] ; (80006cc <MX_DMA2D_Init+0x60>)
8000674: 601a str r2, [r3, #0]
hdma2d.Init.Mode = DMA2D_M2M;
8000676: 4b14 ldr r3, [pc, #80] ; (80006c8 <MX_DMA2D_Init+0x5c>)
8000678: 2200 movs r2, #0
800067a: 605a str r2, [r3, #4]
hdma2d.Init.ColorMode = DMA2D_OUTPUT_ARGB8888;
800067c: 4b12 ldr r3, [pc, #72] ; (80006c8 <MX_DMA2D_Init+0x5c>)
800067e: 2200 movs r2, #0
8000680: 609a str r2, [r3, #8]
hdma2d.Init.OutputOffset = 0;
8000682: 4b11 ldr r3, [pc, #68] ; (80006c8 <MX_DMA2D_Init+0x5c>)
8000684: 2200 movs r2, #0
8000686: 60da str r2, [r3, #12]
hdma2d.LayerCfg[1].InputOffset = 0;
8000688: 4b0f ldr r3, [pc, #60] ; (80006c8 <MX_DMA2D_Init+0x5c>)
800068a: 2200 movs r2, #0
800068c: 629a str r2, [r3, #40] ; 0x28
hdma2d.LayerCfg[1].InputColorMode = DMA2D_INPUT_ARGB8888;
800068e: 4b0e ldr r3, [pc, #56] ; (80006c8 <MX_DMA2D_Init+0x5c>)
8000690: 2200 movs r2, #0
8000692: 62da str r2, [r3, #44] ; 0x2c
hdma2d.LayerCfg[1].AlphaMode = DMA2D_NO_MODIF_ALPHA;
8000694: 4b0c ldr r3, [pc, #48] ; (80006c8 <MX_DMA2D_Init+0x5c>)
8000696: 2200 movs r2, #0
8000698: 631a str r2, [r3, #48] ; 0x30
hdma2d.LayerCfg[1].InputAlpha = 0;
800069a: 4b0b ldr r3, [pc, #44] ; (80006c8 <MX_DMA2D_Init+0x5c>)
800069c: 2200 movs r2, #0
800069e: 635a str r2, [r3, #52] ; 0x34
if (HAL_DMA2D_Init(&hdma2d) != HAL_OK)
80006a0: 4809 ldr r0, [pc, #36] ; (80006c8 <MX_DMA2D_Init+0x5c>)
80006a2: f001 f94f bl 8001944 <HAL_DMA2D_Init>
80006a6: 4603 mov r3, r0
80006a8: 2b00 cmp r3, #0
80006aa: d001 beq.n 80006b0 <MX_DMA2D_Init+0x44>
{
Error_Handler();
80006ac: f000 fb6e bl 8000d8c <Error_Handler>
}
if (HAL_DMA2D_ConfigLayer(&hdma2d, 1) != HAL_OK)
80006b0: 2101 movs r1, #1
80006b2: 4805 ldr r0, [pc, #20] ; (80006c8 <MX_DMA2D_Init+0x5c>)
80006b4: f001 faa0 bl 8001bf8 <HAL_DMA2D_ConfigLayer>
80006b8: 4603 mov r3, r0
80006ba: 2b00 cmp r3, #0
80006bc: d001 beq.n 80006c2 <MX_DMA2D_Init+0x56>
{
Error_Handler();
80006be: f000 fb65 bl 8000d8c <Error_Handler>
}
/* USER CODE BEGIN DMA2D_Init 2 */
/* USER CODE END DMA2D_Init 2 */
}
80006c2: bf00 nop
80006c4: bd80 pop {r7, pc}
80006c6: bf00 nop
80006c8: 20000270 .word 0x20000270
80006cc: 4002b000 .word 0x4002b000
080006d0 <MX_I2C3_Init>:
* @brief I2C3 Initialization Function
* @param None
* @retval None
*/
static void MX_I2C3_Init(void)
{
80006d0: b580 push {r7, lr}
80006d2: af00 add r7, sp, #0
/* USER CODE END I2C3_Init 0 */
/* USER CODE BEGIN I2C3_Init 1 */
/* USER CODE END I2C3_Init 1 */
hi2c3.Instance = I2C3;
80006d4: 4b1b ldr r3, [pc, #108] ; (8000744 <MX_I2C3_Init+0x74>)
80006d6: 4a1c ldr r2, [pc, #112] ; (8000748 <MX_I2C3_Init+0x78>)
80006d8: 601a str r2, [r3, #0]
hi2c3.Init.ClockSpeed = 100000;
80006da: 4b1a ldr r3, [pc, #104] ; (8000744 <MX_I2C3_Init+0x74>)
80006dc: 4a1b ldr r2, [pc, #108] ; (800074c <MX_I2C3_Init+0x7c>)
80006de: 605a str r2, [r3, #4]
hi2c3.Init.DutyCycle = I2C_DUTYCYCLE_2;
80006e0: 4b18 ldr r3, [pc, #96] ; (8000744 <MX_I2C3_Init+0x74>)
80006e2: 2200 movs r2, #0
80006e4: 609a str r2, [r3, #8]
hi2c3.Init.OwnAddress1 = 0;
80006e6: 4b17 ldr r3, [pc, #92] ; (8000744 <MX_I2C3_Init+0x74>)
80006e8: 2200 movs r2, #0
80006ea: 60da str r2, [r3, #12]
hi2c3.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
80006ec: 4b15 ldr r3, [pc, #84] ; (8000744 <MX_I2C3_Init+0x74>)
80006ee: f44f 4280 mov.w r2, #16384 ; 0x4000
80006f2: 611a str r2, [r3, #16]
hi2c3.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
80006f4: 4b13 ldr r3, [pc, #76] ; (8000744 <MX_I2C3_Init+0x74>)
80006f6: 2200 movs r2, #0
80006f8: 615a str r2, [r3, #20]
hi2c3.Init.OwnAddress2 = 0;
80006fa: 4b12 ldr r3, [pc, #72] ; (8000744 <MX_I2C3_Init+0x74>)
80006fc: 2200 movs r2, #0
80006fe: 619a str r2, [r3, #24]
hi2c3.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
8000700: 4b10 ldr r3, [pc, #64] ; (8000744 <MX_I2C3_Init+0x74>)
8000702: 2200 movs r2, #0
8000704: 61da str r2, [r3, #28]
hi2c3.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
8000706: 4b0f ldr r3, [pc, #60] ; (8000744 <MX_I2C3_Init+0x74>)
8000708: 2200 movs r2, #0
800070a: 621a str r2, [r3, #32]
if (HAL_I2C_Init(&hi2c3) != HAL_OK)
800070c: 480d ldr r0, [pc, #52] ; (8000744 <MX_I2C3_Init+0x74>)
800070e: f001 fcc9 bl 80020a4 <HAL_I2C_Init>
8000712: 4603 mov r3, r0
8000714: 2b00 cmp r3, #0
8000716: d001 beq.n 800071c <MX_I2C3_Init+0x4c>
{
Error_Handler();
8000718: f000 fb38 bl 8000d8c <Error_Handler>
}
/** Configure Analogue filter
*/
if (HAL_I2CEx_ConfigAnalogFilter(&hi2c3, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
800071c: 2100 movs r1, #0
800071e: 4809 ldr r0, [pc, #36] ; (8000744 <MX_I2C3_Init+0x74>)
8000720: f001 fdf8 bl 8002314 <HAL_I2CEx_ConfigAnalogFilter>
8000724: 4603 mov r3, r0
8000726: 2b00 cmp r3, #0
8000728: d001 beq.n 800072e <MX_I2C3_Init+0x5e>
{
Error_Handler();
800072a: f000 fb2f bl 8000d8c <Error_Handler>
}
/** Configure Digital filter
*/
if (HAL_I2CEx_ConfigDigitalFilter(&hi2c3, 0) != HAL_OK)
800072e: 2100 movs r1, #0
8000730: 4804 ldr r0, [pc, #16] ; (8000744 <MX_I2C3_Init+0x74>)
8000732: f001 fe2b bl 800238c <HAL_I2CEx_ConfigDigitalFilter>
8000736: 4603 mov r3, r0
8000738: 2b00 cmp r3, #0
800073a: d001 beq.n 8000740 <MX_I2C3_Init+0x70>
{
Error_Handler();
800073c: f000 fb26 bl 8000d8c <Error_Handler>
}
/* USER CODE BEGIN I2C3_Init 2 */
/* USER CODE END I2C3_Init 2 */
}
8000740: bf00 nop
8000742: bd80 pop {r7, pc}
8000744: 2000002c .word 0x2000002c
8000748: 40005c00 .word 0x40005c00
800074c: 000186a0 .word 0x000186a0
08000750 <MX_LTDC_Init>:
* @brief LTDC Initialization Function
* @param None
* @retval None
*/
static void MX_LTDC_Init(void)
{
8000750: b580 push {r7, lr}
8000752: b08e sub sp, #56 ; 0x38
8000754: af00 add r7, sp, #0
/* USER CODE BEGIN LTDC_Init 0 */
/* USER CODE END LTDC_Init 0 */
LTDC_LayerCfgTypeDef pLayerCfg = {0};
8000756: 1d3b adds r3, r7, #4
8000758: 2234 movs r2, #52 ; 0x34
800075a: 2100 movs r1, #0
800075c: 4618 mov r0, r3
800075e: f004 fa1d bl 8004b9c <memset>
/* USER CODE BEGIN LTDC_Init 1 */
/* USER CODE END LTDC_Init 1 */
hltdc.Instance = LTDC;
8000762: 4b39 ldr r3, [pc, #228] ; (8000848 <MX_LTDC_Init+0xf8>)
8000764: 4a39 ldr r2, [pc, #228] ; (800084c <MX_LTDC_Init+0xfc>)
8000766: 601a str r2, [r3, #0]
hltdc.Init.HSPolarity = LTDC_HSPOLARITY_AL;
8000768: 4b37 ldr r3, [pc, #220] ; (8000848 <MX_LTDC_Init+0xf8>)
800076a: 2200 movs r2, #0
800076c: 605a str r2, [r3, #4]
hltdc.Init.VSPolarity = LTDC_VSPOLARITY_AL;
800076e: 4b36 ldr r3, [pc, #216] ; (8000848 <MX_LTDC_Init+0xf8>)
8000770: 2200 movs r2, #0
8000772: 609a str r2, [r3, #8]
hltdc.Init.DEPolarity = LTDC_DEPOLARITY_AL;
8000774: 4b34 ldr r3, [pc, #208] ; (8000848 <MX_LTDC_Init+0xf8>)
8000776: 2200 movs r2, #0
8000778: 60da str r2, [r3, #12]
hltdc.Init.PCPolarity = LTDC_PCPOLARITY_IPC;
800077a: 4b33 ldr r3, [pc, #204] ; (8000848 <MX_LTDC_Init+0xf8>)
800077c: 2200 movs r2, #0
800077e: 611a str r2, [r3, #16]
hltdc.Init.HorizontalSync = 9;
8000780: 4b31 ldr r3, [pc, #196] ; (8000848 <MX_LTDC_Init+0xf8>)
8000782: 2209 movs r2, #9
8000784: 615a str r2, [r3, #20]
hltdc.Init.VerticalSync = 1;
8000786: 4b30 ldr r3, [pc, #192] ; (8000848 <MX_LTDC_Init+0xf8>)
8000788: 2201 movs r2, #1
800078a: 619a str r2, [r3, #24]
hltdc.Init.AccumulatedHBP = 29;
800078c: 4b2e ldr r3, [pc, #184] ; (8000848 <MX_LTDC_Init+0xf8>)
800078e: 221d movs r2, #29
8000790: 61da str r2, [r3, #28]
hltdc.Init.AccumulatedVBP = 3;
8000792: 4b2d ldr r3, [pc, #180] ; (8000848 <MX_LTDC_Init+0xf8>)
8000794: 2203 movs r2, #3
8000796: 621a str r2, [r3, #32]
hltdc.Init.AccumulatedActiveW = 269;
8000798: 4b2b ldr r3, [pc, #172] ; (8000848 <MX_LTDC_Init+0xf8>)
800079a: f240 120d movw r2, #269 ; 0x10d
800079e: 625a str r2, [r3, #36] ; 0x24
hltdc.Init.AccumulatedActiveH = 323;
80007a0: 4b29 ldr r3, [pc, #164] ; (8000848 <MX_LTDC_Init+0xf8>)
80007a2: f240 1243 movw r2, #323 ; 0x143
80007a6: 629a str r2, [r3, #40] ; 0x28
hltdc.Init.TotalWidth = 279;
80007a8: 4b27 ldr r3, [pc, #156] ; (8000848 <MX_LTDC_Init+0xf8>)
80007aa: f240 1217 movw r2, #279 ; 0x117
80007ae: 62da str r2, [r3, #44] ; 0x2c
hltdc.Init.TotalHeigh = 327;
80007b0: 4b25 ldr r3, [pc, #148] ; (8000848 <MX_LTDC_Init+0xf8>)
80007b2: f240 1247 movw r2, #327 ; 0x147
80007b6: 631a str r2, [r3, #48] ; 0x30
hltdc.Init.Backcolor.Blue = 0;
80007b8: 4b23 ldr r3, [pc, #140] ; (8000848 <MX_LTDC_Init+0xf8>)
80007ba: 2200 movs r2, #0
80007bc: f883 2034 strb.w r2, [r3, #52] ; 0x34
hltdc.Init.Backcolor.Green = 0;
80007c0: 4b21 ldr r3, [pc, #132] ; (8000848 <MX_LTDC_Init+0xf8>)
80007c2: 2200 movs r2, #0
80007c4: f883 2035 strb.w r2, [r3, #53] ; 0x35
hltdc.Init.Backcolor.Red = 0;
80007c8: 4b1f ldr r3, [pc, #124] ; (8000848 <MX_LTDC_Init+0xf8>)
80007ca: 2200 movs r2, #0
80007cc: f883 2036 strb.w r2, [r3, #54] ; 0x36
if (HAL_LTDC_Init(&hltdc) != HAL_OK)
80007d0: 481d ldr r0, [pc, #116] ; (8000848 <MX_LTDC_Init+0xf8>)
80007d2: f001 fe1b bl 800240c <HAL_LTDC_Init>
80007d6: 4603 mov r3, r0
80007d8: 2b00 cmp r3, #0
80007da: d001 beq.n 80007e0 <MX_LTDC_Init+0x90>
{
Error_Handler();
80007dc: f000 fad6 bl 8000d8c <Error_Handler>
}
pLayerCfg.WindowX0 = 0;
80007e0: 2300 movs r3, #0
80007e2: 607b str r3, [r7, #4]
pLayerCfg.WindowX1 = 240;
80007e4: 23f0 movs r3, #240 ; 0xf0
80007e6: 60bb str r3, [r7, #8]
pLayerCfg.WindowY0 = 0;
80007e8: 2300 movs r3, #0
80007ea: 60fb str r3, [r7, #12]
pLayerCfg.WindowY1 = 320;
80007ec: f44f 73a0 mov.w r3, #320 ; 0x140
80007f0: 613b str r3, [r7, #16]
pLayerCfg.PixelFormat = LTDC_PIXEL_FORMAT_RGB888;
80007f2: 2301 movs r3, #1
80007f4: 617b str r3, [r7, #20]
pLayerCfg.Alpha = 255;
80007f6: 23ff movs r3, #255 ; 0xff
80007f8: 61bb str r3, [r7, #24]
pLayerCfg.Alpha0 = 0;
80007fa: 2300 movs r3, #0
80007fc: 61fb str r3, [r7, #28]
pLayerCfg.BlendingFactor1 = LTDC_BLENDING_FACTOR1_PAxCA;
80007fe: f44f 63c0 mov.w r3, #1536 ; 0x600
8000802: 623b str r3, [r7, #32]
pLayerCfg.BlendingFactor2 = LTDC_BLENDING_FACTOR2_PAxCA;
8000804: 2307 movs r3, #7
8000806: 627b str r3, [r7, #36] ; 0x24
pLayerCfg.FBStartAdress = 0xD0000000;
8000808: f04f 4350 mov.w r3, #3489660928 ; 0xd0000000
800080c: 62bb str r3, [r7, #40] ; 0x28
pLayerCfg.ImageWidth = 240;
800080e: 23f0 movs r3, #240 ; 0xf0
8000810: 62fb str r3, [r7, #44] ; 0x2c
pLayerCfg.ImageHeight = 320;
8000812: f44f 73a0 mov.w r3, #320 ; 0x140
8000816: 633b str r3, [r7, #48] ; 0x30
pLayerCfg.Backcolor.Blue = 0;
8000818: 2300 movs r3, #0
800081a: f887 3034 strb.w r3, [r7, #52] ; 0x34
pLayerCfg.Backcolor.Green = 0;
800081e: 2300 movs r3, #0
8000820: f887 3035 strb.w r3, [r7, #53] ; 0x35
pLayerCfg.Backcolor.Red = 0;
8000824: 2300 movs r3, #0
8000826: f887 3036 strb.w r3, [r7, #54] ; 0x36
if (HAL_LTDC_ConfigLayer(&hltdc, &pLayerCfg, 0) != HAL_OK)
800082a: 1d3b adds r3, r7, #4
800082c: 2200 movs r2, #0
800082e: 4619 mov r1, r3
8000830: 4805 ldr r0, [pc, #20] ; (8000848 <MX_LTDC_Init+0xf8>)
8000832: f001 ff7d bl 8002730 <HAL_LTDC_ConfigLayer>
8000836: 4603 mov r3, r0
8000838: 2b00 cmp r3, #0
800083a: d001 beq.n 8000840 <MX_LTDC_Init+0xf0>
{
Error_Handler();
800083c: f000 faa6 bl 8000d8c <Error_Handler>
}
/* USER CODE BEGIN LTDC_Init 2 */
/* USER CODE END LTDC_Init 2 */
}
8000840: bf00 nop
8000842: 3738 adds r7, #56 ; 0x38
8000844: 46bd mov sp, r7
8000846: bd80 pop {r7, pc}
8000848: 200000e0 .word 0x200000e0
800084c: 40016800 .word 0x40016800
08000850 <MX_RNG_Init>:
* @brief RNG Initialization Function
* @param None
* @retval None
*/
static void MX_RNG_Init(void)
{
8000850: b580 push {r7, lr}
8000852: af00 add r7, sp, #0
/* USER CODE END RNG_Init 0 */
/* USER CODE BEGIN RNG_Init 1 */
/* USER CODE END RNG_Init 1 */
hrng.Instance = RNG;
8000854: 4b06 ldr r3, [pc, #24] ; (8000870 <MX_RNG_Init+0x20>)
8000856: 4a07 ldr r2, [pc, #28] ; (8000874 <MX_RNG_Init+0x24>)
8000858: 601a str r2, [r3, #0]
if (HAL_RNG_Init(&hrng) != HAL_OK)
800085a: 4805 ldr r0, [pc, #20] ; (8000870 <MX_RNG_Init+0x20>)
800085c: f002 ff90 bl 8003780 <HAL_RNG_Init>
8000860: 4603 mov r3, r0
8000862: 2b00 cmp r3, #0
8000864: d001 beq.n 800086a <MX_RNG_Init+0x1a>
{
Error_Handler();
8000866: f000 fa91 bl 8000d8c <Error_Handler>
}
/* USER CODE BEGIN RNG_Init 2 */
/* USER CODE END RNG_Init 2 */
}
800086a: bf00 nop
800086c: bd80 pop {r7, pc}
800086e: bf00 nop
8000870: 20000260 .word 0x20000260
8000874: 50060800 .word 0x50060800
08000878 <MX_SPI4_Init>:
* @brief SPI4 Initialization Function
* @param None
* @retval None
*/
static void MX_SPI4_Init(void)
{
8000878: b580 push {r7, lr}
800087a: af00 add r7, sp, #0
/* USER CODE BEGIN SPI4_Init 1 */
/* USER CODE END SPI4_Init 1 */
/* SPI4 parameter configuration*/
hspi4.Instance = SPI4;
800087c: 4b17 ldr r3, [pc, #92] ; (80008dc <MX_SPI4_Init+0x64>)
800087e: 4a18 ldr r2, [pc, #96] ; (80008e0 <MX_SPI4_Init+0x68>)
8000880: 601a str r2, [r3, #0]
hspi4.Init.Mode = SPI_MODE_MASTER;
8000882: 4b16 ldr r3, [pc, #88] ; (80008dc <MX_SPI4_Init+0x64>)
8000884: f44f 7282 mov.w r2, #260 ; 0x104
8000888: 605a str r2, [r3, #4]
hspi4.Init.Direction = SPI_DIRECTION_2LINES;
800088a: 4b14 ldr r3, [pc, #80] ; (80008dc <MX_SPI4_Init+0x64>)
800088c: 2200 movs r2, #0
800088e: 609a str r2, [r3, #8]
hspi4.Init.DataSize = SPI_DATASIZE_8BIT;
8000890: 4b12 ldr r3, [pc, #72] ; (80008dc <MX_SPI4_Init+0x64>)
8000892: 2200 movs r2, #0
8000894: 60da str r2, [r3, #12]
hspi4.Init.CLKPolarity = SPI_POLARITY_LOW;
8000896: 4b11 ldr r3, [pc, #68] ; (80008dc <MX_SPI4_Init+0x64>)
8000898: 2200 movs r2, #0
800089a: 611a str r2, [r3, #16]
hspi4.Init.CLKPhase = SPI_PHASE_1EDGE;
800089c: 4b0f ldr r3, [pc, #60] ; (80008dc <MX_SPI4_Init+0x64>)
800089e: 2200 movs r2, #0
80008a0: 615a str r2, [r3, #20]
hspi4.Init.NSS = SPI_NSS_SOFT;
80008a2: 4b0e ldr r3, [pc, #56] ; (80008dc <MX_SPI4_Init+0x64>)
80008a4: f44f 7200 mov.w r2, #512 ; 0x200
80008a8: 619a str r2, [r3, #24]
hspi4.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
80008aa: 4b0c ldr r3, [pc, #48] ; (80008dc <MX_SPI4_Init+0x64>)
80008ac: 2200 movs r2, #0
80008ae: 61da str r2, [r3, #28]
hspi4.Init.FirstBit = SPI_FIRSTBIT_MSB;
80008b0: 4b0a ldr r3, [pc, #40] ; (80008dc <MX_SPI4_Init+0x64>)
80008b2: 2200 movs r2, #0
80008b4: 621a str r2, [r3, #32]
hspi4.Init.TIMode = SPI_TIMODE_DISABLE;
80008b6: 4b09 ldr r3, [pc, #36] ; (80008dc <MX_SPI4_Init+0x64>)
80008b8: 2200 movs r2, #0
80008ba: 625a str r2, [r3, #36] ; 0x24
hspi4.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
80008bc: 4b07 ldr r3, [pc, #28] ; (80008dc <MX_SPI4_Init+0x64>)
80008be: 2200 movs r2, #0
80008c0: 629a str r2, [r3, #40] ; 0x28
hspi4.Init.CRCPolynomial = 10;
80008c2: 4b06 ldr r3, [pc, #24] ; (80008dc <MX_SPI4_Init+0x64>)
80008c4: 220a movs r2, #10
80008c6: 62da str r2, [r3, #44] ; 0x2c
if (HAL_SPI_Init(&hspi4) != HAL_OK)
80008c8: 4804 ldr r0, [pc, #16] ; (80008dc <MX_SPI4_Init+0x64>)
80008ca: f003 f822 bl 8003912 <HAL_SPI_Init>
80008ce: 4603 mov r3, r0
80008d0: 2b00 cmp r3, #0
80008d2: d001 beq.n 80008d8 <MX_SPI4_Init+0x60>
{
Error_Handler();
80008d4: f000 fa5a bl 8000d8c <Error_Handler>
}
/* USER CODE BEGIN SPI4_Init 2 */
/* USER CODE END SPI4_Init 2 */
}
80008d8: bf00 nop
80008da: bd80 pop {r7, pc}
80008dc: 200001c8 .word 0x200001c8
80008e0: 40013400 .word 0x40013400
080008e4 <MX_SPI5_Init>:
* @brief SPI5 Initialization Function
* @param None
* @retval None
*/
static void MX_SPI5_Init(void)
{
80008e4: b580 push {r7, lr}
80008e6: af00 add r7, sp, #0
/* USER CODE BEGIN SPI5_Init 1 */
/* USER CODE END SPI5_Init 1 */
/* SPI5 parameter configuration*/
hspi5.Instance = SPI5;
80008e8: 4b17 ldr r3, [pc, #92] ; (8000948 <MX_SPI5_Init+0x64>)
80008ea: 4a18 ldr r2, [pc, #96] ; (800094c <MX_SPI5_Init+0x68>)
80008ec: 601a str r2, [r3, #0]
hspi5.Init.Mode = SPI_MODE_MASTER;
80008ee: 4b16 ldr r3, [pc, #88] ; (8000948 <MX_SPI5_Init+0x64>)
80008f0: f44f 7282 mov.w r2, #260 ; 0x104
80008f4: 605a str r2, [r3, #4]
hspi5.Init.Direction = SPI_DIRECTION_2LINES;
80008f6: 4b14 ldr r3, [pc, #80] ; (8000948 <MX_SPI5_Init+0x64>)
80008f8: 2200 movs r2, #0
80008fa: 609a str r2, [r3, #8]
hspi5.Init.DataSize = SPI_DATASIZE_8BIT;
80008fc: 4b12 ldr r3, [pc, #72] ; (8000948 <MX_SPI5_Init+0x64>)
80008fe: 2200 movs r2, #0
8000900: 60da str r2, [r3, #12]
hspi5.Init.CLKPolarity = SPI_POLARITY_LOW;
8000902: 4b11 ldr r3, [pc, #68] ; (8000948 <MX_SPI5_Init+0x64>)
8000904: 2200 movs r2, #0
8000906: 611a str r2, [r3, #16]
hspi5.Init.CLKPhase = SPI_PHASE_1EDGE;
8000908: 4b0f ldr r3, [pc, #60] ; (8000948 <MX_SPI5_Init+0x64>)
800090a: 2200 movs r2, #0
800090c: 615a str r2, [r3, #20]
hspi5.Init.NSS = SPI_NSS_SOFT;
800090e: 4b0e ldr r3, [pc, #56] ; (8000948 <MX_SPI5_Init+0x64>)
8000910: f44f 7200 mov.w r2, #512 ; 0x200
8000914: 619a str r2, [r3, #24]
hspi5.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16;
8000916: 4b0c ldr r3, [pc, #48] ; (8000948 <MX_SPI5_Init+0x64>)
8000918: 2218 movs r2, #24
800091a: 61da str r2, [r3, #28]
hspi5.Init.FirstBit = SPI_FIRSTBIT_MSB;
800091c: 4b0a ldr r3, [pc, #40] ; (8000948 <MX_SPI5_Init+0x64>)
800091e: 2200 movs r2, #0
8000920: 621a str r2, [r3, #32]
hspi5.Init.TIMode = SPI_TIMODE_DISABLE;
8000922: 4b09 ldr r3, [pc, #36] ; (8000948 <MX_SPI5_Init+0x64>)
8000924: 2200 movs r2, #0
8000926: 625a str r2, [r3, #36] ; 0x24
hspi5.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
8000928: 4b07 ldr r3, [pc, #28] ; (8000948 <MX_SPI5_Init+0x64>)
800092a: 2200 movs r2, #0
800092c: 629a str r2, [r3, #40] ; 0x28
hspi5.Init.CRCPolynomial = 10;
800092e: 4b06 ldr r3, [pc, #24] ; (8000948 <MX_SPI5_Init+0x64>)
8000930: 220a movs r2, #10
8000932: 62da str r2, [r3, #44] ; 0x2c
if (HAL_SPI_Init(&hspi5) != HAL_OK)
8000934: 4804 ldr r0, [pc, #16] ; (8000948 <MX_SPI5_Init+0x64>)
8000936: f002 ffec bl 8003912 <HAL_SPI_Init>
800093a: 4603 mov r3, r0
800093c: 2b00 cmp r3, #0
800093e: d001 beq.n 8000944 <MX_SPI5_Init+0x60>
{
Error_Handler();
8000940: f000 fa24 bl 8000d8c <Error_Handler>
}
/* USER CODE BEGIN SPI5_Init 2 */
/* USER CODE END SPI5_Init 2 */
}
8000944: bf00 nop
8000946: bd80 pop {r7, pc}
8000948: 20000080 .word 0x20000080
800094c: 40015000 .word 0x40015000
08000950 <MX_TIM1_Init>:
* @brief TIM1 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM1_Init(void)
{
8000950: b580 push {r7, lr}
8000952: b086 sub sp, #24
8000954: af00 add r7, sp, #0
/* USER CODE BEGIN TIM1_Init 0 */
/* USER CODE END TIM1_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
8000956: f107 0308 add.w r3, r7, #8
800095a: 2200 movs r2, #0
800095c: 601a str r2, [r3, #0]
800095e: 605a str r2, [r3, #4]
8000960: 609a str r2, [r3, #8]
8000962: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
8000964: 463b mov r3, r7
8000966: 2200 movs r2, #0
8000968: 601a str r2, [r3, #0]
800096a: 605a str r2, [r3, #4]
/* USER CODE BEGIN TIM1_Init 1 */
/* USER CODE END TIM1_Init 1 */
htim1.Instance = TIM1;
800096c: 4b1e ldr r3, [pc, #120] ; (80009e8 <MX_TIM1_Init+0x98>)
800096e: 4a1f ldr r2, [pc, #124] ; (80009ec <MX_TIM1_Init+0x9c>)
8000970: 601a str r2, [r3, #0]
htim1.Init.Prescaler = 0;
8000972: 4b1d ldr r3, [pc, #116] ; (80009e8 <MX_TIM1_Init+0x98>)
8000974: 2200 movs r2, #0
8000976: 605a str r2, [r3, #4]
htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
8000978: 4b1b ldr r3, [pc, #108] ; (80009e8 <MX_TIM1_Init+0x98>)
800097a: 2200 movs r2, #0
800097c: 609a str r2, [r3, #8]
htim1.Init.Period = 0;
800097e: 4b1a ldr r3, [pc, #104] ; (80009e8 <MX_TIM1_Init+0x98>)
8000980: 2200 movs r2, #0
8000982: 60da str r2, [r3, #12]
htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8000984: 4b18 ldr r3, [pc, #96] ; (80009e8 <MX_TIM1_Init+0x98>)
8000986: 2200 movs r2, #0
8000988: 611a str r2, [r3, #16]
htim1.Init.RepetitionCounter = 0;
800098a: 4b17 ldr r3, [pc, #92] ; (80009e8 <MX_TIM1_Init+0x98>)
800098c: 2200 movs r2, #0
800098e: 615a str r2, [r3, #20]
htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
8000990: 4b15 ldr r3, [pc, #84] ; (80009e8 <MX_TIM1_Init+0x98>)
8000992: 2200 movs r2, #0
8000994: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim1) != HAL_OK)
8000996: 4814 ldr r0, [pc, #80] ; (80009e8 <MX_TIM1_Init+0x98>)
8000998: f003 f81f bl 80039da <HAL_TIM_Base_Init>
800099c: 4603 mov r3, r0
800099e: 2b00 cmp r3, #0
80009a0: d001 beq.n 80009a6 <MX_TIM1_Init+0x56>
{
Error_Handler();
80009a2: f000 f9f3 bl 8000d8c <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
80009a6: f44f 5380 mov.w r3, #4096 ; 0x1000
80009aa: 60bb str r3, [r7, #8]
if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK)
80009ac: f107 0308 add.w r3, r7, #8
80009b0: 4619 mov r1, r3
80009b2: 480d ldr r0, [pc, #52] ; (80009e8 <MX_TIM1_Init+0x98>)
80009b4: f003 f968 bl 8003c88 <HAL_TIM_ConfigClockSource>
80009b8: 4603 mov r3, r0
80009ba: 2b00 cmp r3, #0
80009bc: d001 beq.n 80009c2 <MX_TIM1_Init+0x72>
{
Error_Handler();
80009be: f000 f9e5 bl 8000d8c <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
80009c2: 2300 movs r3, #0
80009c4: 603b str r3, [r7, #0]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
80009c6: 2300 movs r3, #0
80009c8: 607b str r3, [r7, #4]
if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK)
80009ca: 463b mov r3, r7
80009cc: 4619 mov r1, r3
80009ce: 4806 ldr r0, [pc, #24] ; (80009e8 <MX_TIM1_Init+0x98>)
80009d0: f003 fb74 bl 80040bc <HAL_TIMEx_MasterConfigSynchronization>
80009d4: 4603 mov r3, r0
80009d6: 2b00 cmp r3, #0
80009d8: d001 beq.n 80009de <MX_TIM1_Init+0x8e>
{
Error_Handler();
80009da: f000 f9d7 bl 8000d8c <Error_Handler>
}
/* USER CODE BEGIN TIM1_Init 2 */
/* USER CODE END TIM1_Init 2 */
}
80009de: bf00 nop
80009e0: 3718 adds r7, #24
80009e2: 46bd mov sp, r7
80009e4: bd80 pop {r7, pc}
80009e6: bf00 nop
80009e8: 20000220 .word 0x20000220
80009ec: 40010000 .word 0x40010000
080009f0 <MX_USART1_UART_Init>:
* @brief USART1 Initialization Function
* @param None
* @retval None
*/
static void MX_USART1_UART_Init(void)
{
80009f0: b580 push {r7, lr}
80009f2: af00 add r7, sp, #0
/* USER CODE END USART1_Init 0 */
/* USER CODE BEGIN USART1_Init 1 */
/* USER CODE END USART1_Init 1 */
huart1.Instance = USART1;
80009f4: 4b11 ldr r3, [pc, #68] ; (8000a3c <MX_USART1_UART_Init+0x4c>)
80009f6: 4a12 ldr r2, [pc, #72] ; (8000a40 <MX_USART1_UART_Init+0x50>)
80009f8: 601a str r2, [r3, #0]
huart1.Init.BaudRate = 115200;
80009fa: 4b10 ldr r3, [pc, #64] ; (8000a3c <MX_USART1_UART_Init+0x4c>)
80009fc: f44f 32e1 mov.w r2, #115200 ; 0x1c200
8000a00: 605a str r2, [r3, #4]
huart1.Init.WordLength = UART_WORDLENGTH_8B;
8000a02: 4b0e ldr r3, [pc, #56] ; (8000a3c <MX_USART1_UART_Init+0x4c>)
8000a04: 2200 movs r2, #0
8000a06: 609a str r2, [r3, #8]
huart1.Init.StopBits = UART_STOPBITS_1;
8000a08: 4b0c ldr r3, [pc, #48] ; (8000a3c <MX_USART1_UART_Init+0x4c>)
8000a0a: 2200 movs r2, #0
8000a0c: 60da str r2, [r3, #12]
huart1.Init.Parity = UART_PARITY_NONE;
8000a0e: 4b0b ldr r3, [pc, #44] ; (8000a3c <MX_USART1_UART_Init+0x4c>)
8000a10: 2200 movs r2, #0
8000a12: 611a str r2, [r3, #16]
huart1.Init.Mode = UART_MODE_TX_RX;
8000a14: 4b09 ldr r3, [pc, #36] ; (8000a3c <MX_USART1_UART_Init+0x4c>)
8000a16: 220c movs r2, #12
8000a18: 615a str r2, [r3, #20]
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
8000a1a: 4b08 ldr r3, [pc, #32] ; (8000a3c <MX_USART1_UART_Init+0x4c>)
8000a1c: 2200 movs r2, #0
8000a1e: 619a str r2, [r3, #24]
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
8000a20: 4b06 ldr r3, [pc, #24] ; (8000a3c <MX_USART1_UART_Init+0x4c>)
8000a22: 2200 movs r2, #0
8000a24: 61da str r2, [r3, #28]
if (HAL_UART_Init(&huart1) != HAL_OK)
8000a26: 4805 ldr r0, [pc, #20] ; (8000a3c <MX_USART1_UART_Init+0x4c>)
8000a28: f003 fbd8 bl 80041dc <HAL_UART_Init>
8000a2c: 4603 mov r3, r0
8000a2e: 2b00 cmp r3, #0
8000a30: d001 beq.n 8000a36 <MX_USART1_UART_Init+0x46>
{
Error_Handler();
8000a32: f000 f9ab bl 8000d8c <Error_Handler>
}
/* USER CODE BEGIN USART1_Init 2 */
/* USER CODE END USART1_Init 2 */
}
8000a36: bf00 nop
8000a38: bd80 pop {r7, pc}
8000a3a: bf00 nop
8000a3c: 20000188 .word 0x20000188
8000a40: 40011000 .word 0x40011000
08000a44 <MX_FMC_Init>:
/* FMC initialization function */
static void MX_FMC_Init(void)
{
8000a44: b580 push {r7, lr}
8000a46: b088 sub sp, #32
8000a48: af00 add r7, sp, #0
/* USER CODE BEGIN FMC_Init 0 */
/* USER CODE END FMC_Init 0 */
FMC_SDRAM_TimingTypeDef SdramTiming = {0};
8000a4a: 1d3b adds r3, r7, #4
8000a4c: 2200 movs r2, #0
8000a4e: 601a str r2, [r3, #0]
8000a50: 605a str r2, [r3, #4]
8000a52: 609a str r2, [r3, #8]
8000a54: 60da str r2, [r3, #12]
8000a56: 611a str r2, [r3, #16]
8000a58: 615a str r2, [r3, #20]
8000a5a: 619a str r2, [r3, #24]
/* USER CODE END FMC_Init 1 */
/** Perform the SDRAM1 memory initialization sequence
*/
hsdram1.Instance = FMC_SDRAM_DEVICE;
8000a5c: 4b1f ldr r3, [pc, #124] ; (8000adc <MX_FMC_Init+0x98>)
8000a5e: 4a20 ldr r2, [pc, #128] ; (8000ae0 <MX_FMC_Init+0x9c>)
8000a60: 601a str r2, [r3, #0]
/* hsdram1.Init */
hsdram1.Init.SDBank = FMC_SDRAM_BANK2;
8000a62: 4b1e ldr r3, [pc, #120] ; (8000adc <MX_FMC_Init+0x98>)
8000a64: 2201 movs r2, #1
8000a66: 605a str r2, [r3, #4]
hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8;
8000a68: 4b1c ldr r3, [pc, #112] ; (8000adc <MX_FMC_Init+0x98>)
8000a6a: 2200 movs r2, #0
8000a6c: 609a str r2, [r3, #8]
hsdram1.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12;
8000a6e: 4b1b ldr r3, [pc, #108] ; (8000adc <MX_FMC_Init+0x98>)
8000a70: 2204 movs r2, #4
8000a72: 60da str r2, [r3, #12]
hsdram1.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_16;
8000a74: 4b19 ldr r3, [pc, #100] ; (8000adc <MX_FMC_Init+0x98>)
8000a76: 2210 movs r2, #16
8000a78: 611a str r2, [r3, #16]
hsdram1.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
8000a7a: 4b18 ldr r3, [pc, #96] ; (8000adc <MX_FMC_Init+0x98>)
8000a7c: 2240 movs r2, #64 ; 0x40
8000a7e: 615a str r2, [r3, #20]
hsdram1.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_3;
8000a80: 4b16 ldr r3, [pc, #88] ; (8000adc <MX_FMC_Init+0x98>)
8000a82: f44f 72c0 mov.w r2, #384 ; 0x180
8000a86: 619a str r2, [r3, #24]
hsdram1.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
8000a88: 4b14 ldr r3, [pc, #80] ; (8000adc <MX_FMC_Init+0x98>)
8000a8a: 2200 movs r2, #0
8000a8c: 61da str r2, [r3, #28]
hsdram1.Init.SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2;
8000a8e: 4b13 ldr r3, [pc, #76] ; (8000adc <MX_FMC_Init+0x98>)
8000a90: f44f 6200 mov.w r2, #2048 ; 0x800
8000a94: 621a str r2, [r3, #32]
hsdram1.Init.ReadBurst = FMC_SDRAM_RBURST_DISABLE;
8000a96: 4b11 ldr r3, [pc, #68] ; (8000adc <MX_FMC_Init+0x98>)
8000a98: 2200 movs r2, #0
8000a9a: 625a str r2, [r3, #36] ; 0x24
hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_1;
8000a9c: 4b0f ldr r3, [pc, #60] ; (8000adc <MX_FMC_Init+0x98>)
8000a9e: f44f 5200 mov.w r2, #8192 ; 0x2000
8000aa2: 629a str r2, [r3, #40] ; 0x28
/* SdramTiming */
SdramTiming.LoadToActiveDelay = 2;
8000aa4: 2302 movs r3, #2
8000aa6: 607b str r3, [r7, #4]
SdramTiming.ExitSelfRefreshDelay = 7;
8000aa8: 2307 movs r3, #7
8000aaa: 60bb str r3, [r7, #8]
SdramTiming.SelfRefreshTime = 4;
8000aac: 2304 movs r3, #4
8000aae: 60fb str r3, [r7, #12]
SdramTiming.RowCycleDelay = 7;
8000ab0: 2307 movs r3, #7
8000ab2: 613b str r3, [r7, #16]
SdramTiming.WriteRecoveryTime = 3;
8000ab4: 2303 movs r3, #3
8000ab6: 617b str r3, [r7, #20]
SdramTiming.RPDelay = 2;
8000ab8: 2302 movs r3, #2
8000aba: 61bb str r3, [r7, #24]
SdramTiming.RCDDelay = 2;
8000abc: 2302 movs r3, #2
8000abe: 61fb str r3, [r7, #28]
if (HAL_SDRAM_Init(&hsdram1, &SdramTiming) != HAL_OK)
8000ac0: 1d3b adds r3, r7, #4
8000ac2: 4619 mov r1, r3
8000ac4: 4805 ldr r0, [pc, #20] ; (8000adc <MX_FMC_Init+0x98>)
8000ac6: f002 fef0 bl 80038aa <HAL_SDRAM_Init>
8000aca: 4603 mov r3, r0
8000acc: 2b00 cmp r3, #0
8000ace: d001 beq.n 8000ad4 <MX_FMC_Init+0x90>
{
Error_Handler( );
8000ad0: f000 f95c bl 8000d8c <Error_Handler>
}
/* USER CODE BEGIN FMC_Init 2 */
/* USER CODE END FMC_Init 2 */
}
8000ad4: bf00 nop
8000ad6: 3720 adds r7, #32
8000ad8: 46bd mov sp, r7
8000ada: bd80 pop {r7, pc}
8000adc: 200002b0 .word 0x200002b0
8000ae0: a0000140 .word 0xa0000140
08000ae4 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
8000ae4: b580 push {r7, lr}
8000ae6: b08e sub sp, #56 ; 0x38
8000ae8: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000aea: f107 0324 add.w r3, r7, #36 ; 0x24
8000aee: 2200 movs r2, #0
8000af0: 601a str r2, [r3, #0]
8000af2: 605a str r2, [r3, #4]
8000af4: 609a str r2, [r3, #8]
8000af6: 60da str r2, [r3, #12]
8000af8: 611a str r2, [r3, #16]
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOE_CLK_ENABLE();
8000afa: 2300 movs r3, #0
8000afc: 623b str r3, [r7, #32]
8000afe: 4b92 ldr r3, [pc, #584] ; (8000d48 <MX_GPIO_Init+0x264>)
8000b00: 6b1b ldr r3, [r3, #48] ; 0x30
8000b02: 4a91 ldr r2, [pc, #580] ; (8000d48 <MX_GPIO_Init+0x264>)
8000b04: f043 0310 orr.w r3, r3, #16
8000b08: 6313 str r3, [r2, #48] ; 0x30
8000b0a: 4b8f ldr r3, [pc, #572] ; (8000d48 <MX_GPIO_Init+0x264>)
8000b0c: 6b1b ldr r3, [r3, #48] ; 0x30
8000b0e: f003 0310 and.w r3, r3, #16
8000b12: 623b str r3, [r7, #32]
8000b14: 6a3b ldr r3, [r7, #32]
__HAL_RCC_GPIOC_CLK_ENABLE();
8000b16: 2300 movs r3, #0
8000b18: 61fb str r3, [r7, #28]
8000b1a: 4b8b ldr r3, [pc, #556] ; (8000d48 <MX_GPIO_Init+0x264>)
8000b1c: 6b1b ldr r3, [r3, #48] ; 0x30
8000b1e: 4a8a ldr r2, [pc, #552] ; (8000d48 <MX_GPIO_Init+0x264>)
8000b20: f043 0304 orr.w r3, r3, #4
8000b24: 6313 str r3, [r2, #48] ; 0x30
8000b26: 4b88 ldr r3, [pc, #544] ; (8000d48 <MX_GPIO_Init+0x264>)
8000b28: 6b1b ldr r3, [r3, #48] ; 0x30
8000b2a: f003 0304 and.w r3, r3, #4
8000b2e: 61fb str r3, [r7, #28]
8000b30: 69fb ldr r3, [r7, #28]
__HAL_RCC_GPIOF_CLK_ENABLE();
8000b32: 2300 movs r3, #0
8000b34: 61bb str r3, [r7, #24]
8000b36: 4b84 ldr r3, [pc, #528] ; (8000d48 <MX_GPIO_Init+0x264>)
8000b38: 6b1b ldr r3, [r3, #48] ; 0x30
8000b3a: 4a83 ldr r2, [pc, #524] ; (8000d48 <MX_GPIO_Init+0x264>)
8000b3c: f043 0320 orr.w r3, r3, #32
8000b40: 6313 str r3, [r2, #48] ; 0x30
8000b42: 4b81 ldr r3, [pc, #516] ; (8000d48 <MX_GPIO_Init+0x264>)
8000b44: 6b1b ldr r3, [r3, #48] ; 0x30
8000b46: f003 0320 and.w r3, r3, #32
8000b4a: 61bb str r3, [r7, #24]
8000b4c: 69bb ldr r3, [r7, #24]
__HAL_RCC_GPIOH_CLK_ENABLE();
8000b4e: 2300 movs r3, #0
8000b50: 617b str r3, [r7, #20]
8000b52: 4b7d ldr r3, [pc, #500] ; (8000d48 <MX_GPIO_Init+0x264>)
8000b54: 6b1b ldr r3, [r3, #48] ; 0x30
8000b56: 4a7c ldr r2, [pc, #496] ; (8000d48 <MX_GPIO_Init+0x264>)
8000b58: f043 0380 orr.w r3, r3, #128 ; 0x80
8000b5c: 6313 str r3, [r2, #48] ; 0x30
8000b5e: 4b7a ldr r3, [pc, #488] ; (8000d48 <MX_GPIO_Init+0x264>)
8000b60: 6b1b ldr r3, [r3, #48] ; 0x30
8000b62: f003 0380 and.w r3, r3, #128 ; 0x80
8000b66: 617b str r3, [r7, #20]
8000b68: 697b ldr r3, [r7, #20]
__HAL_RCC_GPIOA_CLK_ENABLE();
8000b6a: 2300 movs r3, #0
8000b6c: 613b str r3, [r7, #16]
8000b6e: 4b76 ldr r3, [pc, #472] ; (8000d48 <MX_GPIO_Init+0x264>)
8000b70: 6b1b ldr r3, [r3, #48] ; 0x30
8000b72: 4a75 ldr r2, [pc, #468] ; (8000d48 <MX_GPIO_Init+0x264>)
8000b74: f043 0301 orr.w r3, r3, #1
8000b78: 6313 str r3, [r2, #48] ; 0x30
8000b7a: 4b73 ldr r3, [pc, #460] ; (8000d48 <MX_GPIO_Init+0x264>)
8000b7c: 6b1b ldr r3, [r3, #48] ; 0x30
8000b7e: f003 0301 and.w r3, r3, #1
8000b82: 613b str r3, [r7, #16]
8000b84: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOB_CLK_ENABLE();
8000b86: 2300 movs r3, #0
8000b88: 60fb str r3, [r7, #12]
8000b8a: 4b6f ldr r3, [pc, #444] ; (8000d48 <MX_GPIO_Init+0x264>)
8000b8c: 6b1b ldr r3, [r3, #48] ; 0x30
8000b8e: 4a6e ldr r2, [pc, #440] ; (8000d48 <MX_GPIO_Init+0x264>)
8000b90: f043 0302 orr.w r3, r3, #2
8000b94: 6313 str r3, [r2, #48] ; 0x30
8000b96: 4b6c ldr r3, [pc, #432] ; (8000d48 <MX_GPIO_Init+0x264>)
8000b98: 6b1b ldr r3, [r3, #48] ; 0x30
8000b9a: f003 0302 and.w r3, r3, #2
8000b9e: 60fb str r3, [r7, #12]
8000ba0: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOG_CLK_ENABLE();
8000ba2: 2300 movs r3, #0
8000ba4: 60bb str r3, [r7, #8]
8000ba6: 4b68 ldr r3, [pc, #416] ; (8000d48 <MX_GPIO_Init+0x264>)
8000ba8: 6b1b ldr r3, [r3, #48] ; 0x30
8000baa: 4a67 ldr r2, [pc, #412] ; (8000d48 <MX_GPIO_Init+0x264>)
8000bac: f043 0340 orr.w r3, r3, #64 ; 0x40
8000bb0: 6313 str r3, [r2, #48] ; 0x30
8000bb2: 4b65 ldr r3, [pc, #404] ; (8000d48 <MX_GPIO_Init+0x264>)
8000bb4: 6b1b ldr r3, [r3, #48] ; 0x30
8000bb6: f003 0340 and.w r3, r3, #64 ; 0x40
8000bba: 60bb str r3, [r7, #8]
8000bbc: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOD_CLK_ENABLE();
8000bbe: 2300 movs r3, #0
8000bc0: 607b str r3, [r7, #4]
8000bc2: 4b61 ldr r3, [pc, #388] ; (8000d48 <MX_GPIO_Init+0x264>)
8000bc4: 6b1b ldr r3, [r3, #48] ; 0x30
8000bc6: 4a60 ldr r2, [pc, #384] ; (8000d48 <MX_GPIO_Init+0x264>)
8000bc8: f043 0308 orr.w r3, r3, #8
8000bcc: 6313 str r3, [r2, #48] ; 0x30
8000bce: 4b5e ldr r3, [pc, #376] ; (8000d48 <MX_GPIO_Init+0x264>)
8000bd0: 6b1b ldr r3, [r3, #48] ; 0x30
8000bd2: f003 0308 and.w r3, r3, #8
8000bd6: 607b str r3, [r7, #4]
8000bd8: 687b ldr r3, [r7, #4]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOF, GPIO_PIN_6, GPIO_PIN_RESET);
8000bda: 2200 movs r2, #0
8000bdc: 2140 movs r1, #64 ; 0x40
8000bde: 485b ldr r0, [pc, #364] ; (8000d4c <MX_GPIO_Init+0x268>)
8000be0: f001 fa46 bl 8002070 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOC, NCS_MEMS_SPI_Pin|CSX_Pin|OTG_FS_PSO_Pin, GPIO_PIN_RESET);
8000be4: 2200 movs r2, #0
8000be6: 2116 movs r1, #22
8000be8: 4859 ldr r0, [pc, #356] ; (8000d50 <MX_GPIO_Init+0x26c>)
8000bea: f001 fa41 bl 8002070 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(ACP_RST_GPIO_Port, ACP_RST_Pin, GPIO_PIN_RESET);
8000bee: 2200 movs r2, #0
8000bf0: 2180 movs r1, #128 ; 0x80
8000bf2: 4858 ldr r0, [pc, #352] ; (8000d54 <MX_GPIO_Init+0x270>)
8000bf4: f001 fa3c bl 8002070 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOD, RDX_Pin|WRX_DCX_Pin, GPIO_PIN_RESET);
8000bf8: 2200 movs r2, #0
8000bfa: f44f 5140 mov.w r1, #12288 ; 0x3000
8000bfe: 4856 ldr r0, [pc, #344] ; (8000d58 <MX_GPIO_Init+0x274>)
8000c00: f001 fa36 bl 8002070 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOG, LD3_Pin|LD4_Pin, GPIO_PIN_RESET);
8000c04: 2200 movs r2, #0
8000c06: f44f 41c0 mov.w r1, #24576 ; 0x6000
8000c0a: 4854 ldr r0, [pc, #336] ; (8000d5c <MX_GPIO_Init+0x278>)
8000c0c: f001 fa30 bl 8002070 <HAL_GPIO_WritePin>
/*Configure GPIO pin : PF6 */
GPIO_InitStruct.Pin = GPIO_PIN_6;
8000c10: 2340 movs r3, #64 ; 0x40
8000c12: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000c14: 2301 movs r3, #1
8000c16: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000c18: 2300 movs r3, #0
8000c1a: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000c1c: 2303 movs r3, #3
8000c1e: 633b str r3, [r7, #48] ; 0x30
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
8000c20: f107 0324 add.w r3, r7, #36 ; 0x24
8000c24: 4619 mov r1, r3
8000c26: 4849 ldr r0, [pc, #292] ; (8000d4c <MX_GPIO_Init+0x268>)
8000c28: f001 f878 bl 8001d1c <HAL_GPIO_Init>
/*Configure GPIO pins : NCS_MEMS_SPI_Pin CSX_Pin OTG_FS_PSO_Pin */
GPIO_InitStruct.Pin = NCS_MEMS_SPI_Pin|CSX_Pin|OTG_FS_PSO_Pin;
8000c2c: 2316 movs r3, #22
8000c2e: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000c30: 2301 movs r3, #1
8000c32: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000c34: 2300 movs r3, #0
8000c36: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000c38: 2300 movs r3, #0
8000c3a: 633b str r3, [r7, #48] ; 0x30
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8000c3c: f107 0324 add.w r3, r7, #36 ; 0x24
8000c40: 4619 mov r1, r3
8000c42: 4843 ldr r0, [pc, #268] ; (8000d50 <MX_GPIO_Init+0x26c>)
8000c44: f001 f86a bl 8001d1c <HAL_GPIO_Init>
/*Configure GPIO pins : B1_Pin MEMS_INT1_Pin MEMS_INT2_Pin TP_INT1_Pin */
GPIO_InitStruct.Pin = B1_Pin|MEMS_INT1_Pin|MEMS_INT2_Pin|TP_INT1_Pin;
8000c48: f248 0307 movw r3, #32775 ; 0x8007
8000c4c: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_EVT_RISING;
8000c4e: 4b44 ldr r3, [pc, #272] ; (8000d60 <MX_GPIO_Init+0x27c>)
8000c50: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000c52: 2300 movs r3, #0
8000c54: 62fb str r3, [r7, #44] ; 0x2c
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000c56: f107 0324 add.w r3, r7, #36 ; 0x24
8000c5a: 4619 mov r1, r3
8000c5c: 483d ldr r0, [pc, #244] ; (8000d54 <MX_GPIO_Init+0x270>)
8000c5e: f001 f85d bl 8001d1c <HAL_GPIO_Init>
/*Configure GPIO pin : ACP_RST_Pin */
GPIO_InitStruct.Pin = ACP_RST_Pin;
8000c62: 2380 movs r3, #128 ; 0x80
8000c64: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000c66: 2301 movs r3, #1
8000c68: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000c6a: 2300 movs r3, #0
8000c6c: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000c6e: 2300 movs r3, #0
8000c70: 633b str r3, [r7, #48] ; 0x30
HAL_GPIO_Init(ACP_RST_GPIO_Port, &GPIO_InitStruct);
8000c72: f107 0324 add.w r3, r7, #36 ; 0x24
8000c76: 4619 mov r1, r3
8000c78: 4836 ldr r0, [pc, #216] ; (8000d54 <MX_GPIO_Init+0x270>)
8000c7a: f001 f84f bl 8001d1c <HAL_GPIO_Init>
/*Configure GPIO pin : OTG_FS_OC_Pin */
GPIO_InitStruct.Pin = OTG_FS_OC_Pin;
8000c7e: 2320 movs r3, #32
8000c80: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_EVT_RISING;
8000c82: 4b37 ldr r3, [pc, #220] ; (8000d60 <MX_GPIO_Init+0x27c>)
8000c84: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000c86: 2300 movs r3, #0
8000c88: 62fb str r3, [r7, #44] ; 0x2c
HAL_GPIO_Init(OTG_FS_OC_GPIO_Port, &GPIO_InitStruct);
8000c8a: f107 0324 add.w r3, r7, #36 ; 0x24
8000c8e: 4619 mov r1, r3
8000c90: 482f ldr r0, [pc, #188] ; (8000d50 <MX_GPIO_Init+0x26c>)
8000c92: f001 f843 bl 8001d1c <HAL_GPIO_Init>
/*Configure GPIO pin : BOOT1_Pin */
GPIO_InitStruct.Pin = BOOT1_Pin;
8000c96: 2304 movs r3, #4
8000c98: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8000c9a: 2300 movs r3, #0
8000c9c: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000c9e: 2300 movs r3, #0
8000ca0: 62fb str r3, [r7, #44] ; 0x2c
HAL_GPIO_Init(BOOT1_GPIO_Port, &GPIO_InitStruct);
8000ca2: f107 0324 add.w r3, r7, #36 ; 0x24
8000ca6: 4619 mov r1, r3
8000ca8: 482e ldr r0, [pc, #184] ; (8000d64 <MX_GPIO_Init+0x280>)
8000caa: f001 f837 bl 8001d1c <HAL_GPIO_Init>
/*Configure GPIO pins : OTG_HS_ID_Pin OTG_HS_DM_Pin OTG_HS_DP_Pin */
GPIO_InitStruct.Pin = OTG_HS_ID_Pin|OTG_HS_DM_Pin|OTG_HS_DP_Pin;
8000cae: f44f 4350 mov.w r3, #53248 ; 0xd000
8000cb2: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000cb4: 2302 movs r3, #2
8000cb6: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000cb8: 2300 movs r3, #0
8000cba: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000cbc: 2300 movs r3, #0
8000cbe: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF12_OTG_HS_FS;
8000cc0: 230c movs r3, #12
8000cc2: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8000cc4: f107 0324 add.w r3, r7, #36 ; 0x24
8000cc8: 4619 mov r1, r3
8000cca: 4826 ldr r0, [pc, #152] ; (8000d64 <MX_GPIO_Init+0x280>)
8000ccc: f001 f826 bl 8001d1c <HAL_GPIO_Init>
/*Configure GPIO pin : VBUS_HS_Pin */
GPIO_InitStruct.Pin = VBUS_HS_Pin;
8000cd0: f44f 5300 mov.w r3, #8192 ; 0x2000
8000cd4: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8000cd6: 2300 movs r3, #0
8000cd8: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000cda: 2300 movs r3, #0
8000cdc: 62fb str r3, [r7, #44] ; 0x2c
HAL_GPIO_Init(VBUS_HS_GPIO_Port, &GPIO_InitStruct);
8000cde: f107 0324 add.w r3, r7, #36 ; 0x24
8000ce2: 4619 mov r1, r3
8000ce4: 481f ldr r0, [pc, #124] ; (8000d64 <MX_GPIO_Init+0x280>)
8000ce6: f001 f819 bl 8001d1c <HAL_GPIO_Init>
/*Configure GPIO pin : TE_Pin */
GPIO_InitStruct.Pin = TE_Pin;
8000cea: f44f 6300 mov.w r3, #2048 ; 0x800
8000cee: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8000cf0: 2300 movs r3, #0
8000cf2: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000cf4: 2300 movs r3, #0
8000cf6: 62fb str r3, [r7, #44] ; 0x2c
HAL_GPIO_Init(TE_GPIO_Port, &GPIO_InitStruct);
8000cf8: f107 0324 add.w r3, r7, #36 ; 0x24
8000cfc: 4619 mov r1, r3
8000cfe: 4816 ldr r0, [pc, #88] ; (8000d58 <MX_GPIO_Init+0x274>)
8000d00: f001 f80c bl 8001d1c <HAL_GPIO_Init>
/*Configure GPIO pins : RDX_Pin WRX_DCX_Pin */
GPIO_InitStruct.Pin = RDX_Pin|WRX_DCX_Pin;
8000d04: f44f 5340 mov.w r3, #12288 ; 0x3000
8000d08: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000d0a: 2301 movs r3, #1
8000d0c: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000d0e: 2300 movs r3, #0
8000d10: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000d12: 2300 movs r3, #0
8000d14: 633b str r3, [r7, #48] ; 0x30
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
8000d16: f107 0324 add.w r3, r7, #36 ; 0x24
8000d1a: 4619 mov r1, r3
8000d1c: 480e ldr r0, [pc, #56] ; (8000d58 <MX_GPIO_Init+0x274>)
8000d1e: f000 fffd bl 8001d1c <HAL_GPIO_Init>
/*Configure GPIO pins : LD3_Pin LD4_Pin */
GPIO_InitStruct.Pin = LD3_Pin|LD4_Pin;
8000d22: f44f 43c0 mov.w r3, #24576 ; 0x6000
8000d26: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000d28: 2301 movs r3, #1
8000d2a: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000d2c: 2300 movs r3, #0
8000d2e: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000d30: 2300 movs r3, #0
8000d32: 633b str r3, [r7, #48] ; 0x30
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
8000d34: f107 0324 add.w r3, r7, #36 ; 0x24
8000d38: 4619 mov r1, r3
8000d3a: 4808 ldr r0, [pc, #32] ; (8000d5c <MX_GPIO_Init+0x278>)
8000d3c: f000 ffee bl 8001d1c <HAL_GPIO_Init>
}
8000d40: bf00 nop
8000d42: 3738 adds r7, #56 ; 0x38
8000d44: 46bd mov sp, r7
8000d46: bd80 pop {r7, pc}
8000d48: 40023800 .word 0x40023800
8000d4c: 40021400 .word 0x40021400
8000d50: 40020800 .word 0x40020800
8000d54: 40020000 .word 0x40020000
8000d58: 40020c00 .word 0x40020c00
8000d5c: 40021800 .word 0x40021800
8000d60: 10120000 .word 0x10120000
8000d64: 40020400 .word 0x40020400
08000d68 <HAL_TIM_PeriodElapsedCallback>:
* a global variable "uwTick" used as application time base.
* @param htim : TIM handle
* @retval None
*/
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
8000d68: b580 push {r7, lr}
8000d6a: b082 sub sp, #8
8000d6c: af00 add r7, sp, #0
8000d6e: 6078 str r0, [r7, #4]
/* USER CODE BEGIN Callback 0 */
/* USER CODE END Callback 0 */
if (htim->Instance == TIM6) {
8000d70: 687b ldr r3, [r7, #4]
8000d72: 681b ldr r3, [r3, #0]
8000d74: 4a04 ldr r2, [pc, #16] ; (8000d88 <HAL_TIM_PeriodElapsedCallback+0x20>)
8000d76: 4293 cmp r3, r2
8000d78: d101 bne.n 8000d7e <HAL_TIM_PeriodElapsedCallback+0x16>
HAL_IncTick();
8000d7a: f000 fcc5 bl 8001708 <HAL_IncTick>
}
/* USER CODE BEGIN Callback 1 */
/* USER CODE END Callback 1 */
}
8000d7e: bf00 nop
8000d80: 3708 adds r7, #8
8000d82: 46bd mov sp, r7
8000d84: bd80 pop {r7, pc}
8000d86: bf00 nop
8000d88: 40001000 .word 0x40001000
08000d8c <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
8000d8c: b480 push {r7}
8000d8e: af00 add r7, sp, #0
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
/* USER CODE END Error_Handler_Debug */
}
8000d90: bf00 nop
8000d92: 46bd mov sp, r7
8000d94: f85d 7b04 ldr.w r7, [sp], #4
8000d98: 4770 bx lr
...
08000d9c <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8000d9c: b580 push {r7, lr}
8000d9e: b082 sub sp, #8
8000da0: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8000da2: 2300 movs r3, #0
8000da4: 607b str r3, [r7, #4]
8000da6: 4b12 ldr r3, [pc, #72] ; (8000df0 <HAL_MspInit+0x54>)
8000da8: 6c5b ldr r3, [r3, #68] ; 0x44
8000daa: 4a11 ldr r2, [pc, #68] ; (8000df0 <HAL_MspInit+0x54>)
8000dac: f443 4380 orr.w r3, r3, #16384 ; 0x4000
8000db0: 6453 str r3, [r2, #68] ; 0x44
8000db2: 4b0f ldr r3, [pc, #60] ; (8000df0 <HAL_MspInit+0x54>)
8000db4: 6c5b ldr r3, [r3, #68] ; 0x44
8000db6: f403 4380 and.w r3, r3, #16384 ; 0x4000
8000dba: 607b str r3, [r7, #4]
8000dbc: 687b ldr r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
8000dbe: 2300 movs r3, #0
8000dc0: 603b str r3, [r7, #0]
8000dc2: 4b0b ldr r3, [pc, #44] ; (8000df0 <HAL_MspInit+0x54>)
8000dc4: 6c1b ldr r3, [r3, #64] ; 0x40
8000dc6: 4a0a ldr r2, [pc, #40] ; (8000df0 <HAL_MspInit+0x54>)
8000dc8: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8000dcc: 6413 str r3, [r2, #64] ; 0x40
8000dce: 4b08 ldr r3, [pc, #32] ; (8000df0 <HAL_MspInit+0x54>)
8000dd0: 6c1b ldr r3, [r3, #64] ; 0x40
8000dd2: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8000dd6: 603b str r3, [r7, #0]
8000dd8: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* PendSV_IRQn interrupt configuration */
HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
8000dda: 2200 movs r2, #0
8000ddc: 210f movs r1, #15
8000dde: f06f 0001 mvn.w r0, #1
8000de2: f000 fd69 bl 80018b8 <HAL_NVIC_SetPriority>
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
8000de6: bf00 nop
8000de8: 3708 adds r7, #8
8000dea: 46bd mov sp, r7
8000dec: bd80 pop {r7, pc}
8000dee: bf00 nop
8000df0: 40023800 .word 0x40023800
08000df4 <HAL_CRC_MspInit>:
* This function configures the hardware resources used in this example
* @param hcrc: CRC handle pointer
* @retval None
*/
void HAL_CRC_MspInit(CRC_HandleTypeDef* hcrc)
{
8000df4: b480 push {r7}
8000df6: b085 sub sp, #20
8000df8: af00 add r7, sp, #0
8000dfa: 6078 str r0, [r7, #4]
if(hcrc->Instance==CRC)
8000dfc: 687b ldr r3, [r7, #4]
8000dfe: 681b ldr r3, [r3, #0]
8000e00: 4a0b ldr r2, [pc, #44] ; (8000e30 <HAL_CRC_MspInit+0x3c>)
8000e02: 4293 cmp r3, r2
8000e04: d10d bne.n 8000e22 <HAL_CRC_MspInit+0x2e>
{
/* USER CODE BEGIN CRC_MspInit 0 */
/* USER CODE END CRC_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_CRC_CLK_ENABLE();
8000e06: 2300 movs r3, #0
8000e08: 60fb str r3, [r7, #12]
8000e0a: 4b0a ldr r3, [pc, #40] ; (8000e34 <HAL_CRC_MspInit+0x40>)
8000e0c: 6b1b ldr r3, [r3, #48] ; 0x30
8000e0e: 4a09 ldr r2, [pc, #36] ; (8000e34 <HAL_CRC_MspInit+0x40>)
8000e10: f443 5380 orr.w r3, r3, #4096 ; 0x1000
8000e14: 6313 str r3, [r2, #48] ; 0x30
8000e16: 4b07 ldr r3, [pc, #28] ; (8000e34 <HAL_CRC_MspInit+0x40>)
8000e18: 6b1b ldr r3, [r3, #48] ; 0x30
8000e1a: f403 5380 and.w r3, r3, #4096 ; 0x1000
8000e1e: 60fb str r3, [r7, #12]
8000e20: 68fb ldr r3, [r7, #12]
/* USER CODE BEGIN CRC_MspInit 1 */
/* USER CODE END CRC_MspInit 1 */
}
}
8000e22: bf00 nop
8000e24: 3714 adds r7, #20
8000e26: 46bd mov sp, r7
8000e28: f85d 7b04 ldr.w r7, [sp], #4
8000e2c: 4770 bx lr
8000e2e: bf00 nop
8000e30: 40023000 .word 0x40023000
8000e34: 40023800 .word 0x40023800
08000e38 <HAL_DMA2D_MspInit>:
* This function configures the hardware resources used in this example
* @param hdma2d: DMA2D handle pointer
* @retval None
*/
void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)
{
8000e38: b580 push {r7, lr}
8000e3a: b084 sub sp, #16
8000e3c: af00 add r7, sp, #0
8000e3e: 6078 str r0, [r7, #4]
if(hdma2d->Instance==DMA2D)
8000e40: 687b ldr r3, [r7, #4]
8000e42: 681b ldr r3, [r3, #0]
8000e44: 4a0e ldr r2, [pc, #56] ; (8000e80 <HAL_DMA2D_MspInit+0x48>)
8000e46: 4293 cmp r3, r2
8000e48: d115 bne.n 8000e76 <HAL_DMA2D_MspInit+0x3e>
{
/* USER CODE BEGIN DMA2D_MspInit 0 */
/* USER CODE END DMA2D_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_DMA2D_CLK_ENABLE();
8000e4a: 2300 movs r3, #0
8000e4c: 60fb str r3, [r7, #12]
8000e4e: 4b0d ldr r3, [pc, #52] ; (8000e84 <HAL_DMA2D_MspInit+0x4c>)
8000e50: 6b1b ldr r3, [r3, #48] ; 0x30
8000e52: 4a0c ldr r2, [pc, #48] ; (8000e84 <HAL_DMA2D_MspInit+0x4c>)
8000e54: f443 0300 orr.w r3, r3, #8388608 ; 0x800000
8000e58: 6313 str r3, [r2, #48] ; 0x30
8000e5a: 4b0a ldr r3, [pc, #40] ; (8000e84 <HAL_DMA2D_MspInit+0x4c>)
8000e5c: 6b1b ldr r3, [r3, #48] ; 0x30
8000e5e: f403 0300 and.w r3, r3, #8388608 ; 0x800000
8000e62: 60fb str r3, [r7, #12]
8000e64: 68fb ldr r3, [r7, #12]
/* DMA2D interrupt Init */
HAL_NVIC_SetPriority(DMA2D_IRQn, 5, 0);
8000e66: 2200 movs r2, #0
8000e68: 2105 movs r1, #5
8000e6a: 205a movs r0, #90 ; 0x5a
8000e6c: f000 fd24 bl 80018b8 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(DMA2D_IRQn);
8000e70: 205a movs r0, #90 ; 0x5a
8000e72: f000 fd3d bl 80018f0 <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN DMA2D_MspInit 1 */
/* USER CODE END DMA2D_MspInit 1 */
}
}
8000e76: bf00 nop
8000e78: 3710 adds r7, #16
8000e7a: 46bd mov sp, r7
8000e7c: bd80 pop {r7, pc}
8000e7e: bf00 nop
8000e80: 4002b000 .word 0x4002b000
8000e84: 40023800 .word 0x40023800
08000e88 <HAL_I2C_MspInit>:
* This function configures the hardware resources used in this example
* @param hi2c: I2C handle pointer
* @retval None
*/
void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
{
8000e88: b580 push {r7, lr}
8000e8a: b08a sub sp, #40 ; 0x28
8000e8c: af00 add r7, sp, #0
8000e8e: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000e90: f107 0314 add.w r3, r7, #20
8000e94: 2200 movs r2, #0
8000e96: 601a str r2, [r3, #0]
8000e98: 605a str r2, [r3, #4]
8000e9a: 609a str r2, [r3, #8]
8000e9c: 60da str r2, [r3, #12]
8000e9e: 611a str r2, [r3, #16]
if(hi2c->Instance==I2C3)
8000ea0: 687b ldr r3, [r7, #4]
8000ea2: 681b ldr r3, [r3, #0]
8000ea4: 4a29 ldr r2, [pc, #164] ; (8000f4c <HAL_I2C_MspInit+0xc4>)
8000ea6: 4293 cmp r3, r2
8000ea8: d14b bne.n 8000f42 <HAL_I2C_MspInit+0xba>
{
/* USER CODE BEGIN I2C3_MspInit 0 */
/* USER CODE END I2C3_MspInit 0 */
__HAL_RCC_GPIOC_CLK_ENABLE();
8000eaa: 2300 movs r3, #0
8000eac: 613b str r3, [r7, #16]
8000eae: 4b28 ldr r3, [pc, #160] ; (8000f50 <HAL_I2C_MspInit+0xc8>)
8000eb0: 6b1b ldr r3, [r3, #48] ; 0x30
8000eb2: 4a27 ldr r2, [pc, #156] ; (8000f50 <HAL_I2C_MspInit+0xc8>)
8000eb4: f043 0304 orr.w r3, r3, #4
8000eb8: 6313 str r3, [r2, #48] ; 0x30
8000eba: 4b25 ldr r3, [pc, #148] ; (8000f50 <HAL_I2C_MspInit+0xc8>)
8000ebc: 6b1b ldr r3, [r3, #48] ; 0x30
8000ebe: f003 0304 and.w r3, r3, #4
8000ec2: 613b str r3, [r7, #16]
8000ec4: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
8000ec6: 2300 movs r3, #0
8000ec8: 60fb str r3, [r7, #12]
8000eca: 4b21 ldr r3, [pc, #132] ; (8000f50 <HAL_I2C_MspInit+0xc8>)
8000ecc: 6b1b ldr r3, [r3, #48] ; 0x30
8000ece: 4a20 ldr r2, [pc, #128] ; (8000f50 <HAL_I2C_MspInit+0xc8>)
8000ed0: f043 0301 orr.w r3, r3, #1
8000ed4: 6313 str r3, [r2, #48] ; 0x30
8000ed6: 4b1e ldr r3, [pc, #120] ; (8000f50 <HAL_I2C_MspInit+0xc8>)
8000ed8: 6b1b ldr r3, [r3, #48] ; 0x30
8000eda: f003 0301 and.w r3, r3, #1
8000ede: 60fb str r3, [r7, #12]
8000ee0: 68fb ldr r3, [r7, #12]
/**I2C3 GPIO Configuration
PC9 ------> I2C3_SDA
PA8 ------> I2C3_SCL
*/
GPIO_InitStruct.Pin = I2C3_SDA_Pin;
8000ee2: f44f 7300 mov.w r3, #512 ; 0x200
8000ee6: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
8000ee8: 2312 movs r3, #18
8000eea: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_PULLUP;
8000eec: 2301 movs r3, #1
8000eee: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000ef0: 2300 movs r3, #0
8000ef2: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF4_I2C3;
8000ef4: 2304 movs r3, #4
8000ef6: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(I2C3_SDA_GPIO_Port, &GPIO_InitStruct);
8000ef8: f107 0314 add.w r3, r7, #20
8000efc: 4619 mov r1, r3
8000efe: 4815 ldr r0, [pc, #84] ; (8000f54 <HAL_I2C_MspInit+0xcc>)
8000f00: f000 ff0c bl 8001d1c <HAL_GPIO_Init>
GPIO_InitStruct.Pin = I2C3_SCL_Pin;
8000f04: f44f 7380 mov.w r3, #256 ; 0x100
8000f08: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
8000f0a: 2312 movs r3, #18
8000f0c: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_PULLUP;
8000f0e: 2301 movs r3, #1
8000f10: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000f12: 2300 movs r3, #0
8000f14: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF4_I2C3;
8000f16: 2304 movs r3, #4
8000f18: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(I2C3_SCL_GPIO_Port, &GPIO_InitStruct);
8000f1a: f107 0314 add.w r3, r7, #20
8000f1e: 4619 mov r1, r3
8000f20: 480d ldr r0, [pc, #52] ; (8000f58 <HAL_I2C_MspInit+0xd0>)
8000f22: f000 fefb bl 8001d1c <HAL_GPIO_Init>
/* Peripheral clock enable */
__HAL_RCC_I2C3_CLK_ENABLE();
8000f26: 2300 movs r3, #0
8000f28: 60bb str r3, [r7, #8]
8000f2a: 4b09 ldr r3, [pc, #36] ; (8000f50 <HAL_I2C_MspInit+0xc8>)
8000f2c: 6c1b ldr r3, [r3, #64] ; 0x40
8000f2e: 4a08 ldr r2, [pc, #32] ; (8000f50 <HAL_I2C_MspInit+0xc8>)
8000f30: f443 0300 orr.w r3, r3, #8388608 ; 0x800000
8000f34: 6413 str r3, [r2, #64] ; 0x40
8000f36: 4b06 ldr r3, [pc, #24] ; (8000f50 <HAL_I2C_MspInit+0xc8>)
8000f38: 6c1b ldr r3, [r3, #64] ; 0x40
8000f3a: f403 0300 and.w r3, r3, #8388608 ; 0x800000
8000f3e: 60bb str r3, [r7, #8]
8000f40: 68bb ldr r3, [r7, #8]
/* USER CODE BEGIN I2C3_MspInit 1 */
/* USER CODE END I2C3_MspInit 1 */
}
}
8000f42: bf00 nop
8000f44: 3728 adds r7, #40 ; 0x28
8000f46: 46bd mov sp, r7
8000f48: bd80 pop {r7, pc}
8000f4a: bf00 nop
8000f4c: 40005c00 .word 0x40005c00
8000f50: 40023800 .word 0x40023800
8000f54: 40020800 .word 0x40020800
8000f58: 40020000 .word 0x40020000
08000f5c <HAL_LTDC_MspInit>:
* This function configures the hardware resources used in this example
* @param hltdc: LTDC handle pointer
* @retval None
*/
void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc)
{
8000f5c: b580 push {r7, lr}
8000f5e: b08e sub sp, #56 ; 0x38
8000f60: af00 add r7, sp, #0
8000f62: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000f64: f107 0324 add.w r3, r7, #36 ; 0x24
8000f68: 2200 movs r2, #0
8000f6a: 601a str r2, [r3, #0]
8000f6c: 605a str r2, [r3, #4]
8000f6e: 609a str r2, [r3, #8]
8000f70: 60da str r2, [r3, #12]
8000f72: 611a str r2, [r3, #16]
if(hltdc->Instance==LTDC)
8000f74: 687b ldr r3, [r7, #4]
8000f76: 681b ldr r3, [r3, #0]
8000f78: 4a7b ldr r2, [pc, #492] ; (8001168 <HAL_LTDC_MspInit+0x20c>)
8000f7a: 4293 cmp r3, r2
8000f7c: f040 80f0 bne.w 8001160 <HAL_LTDC_MspInit+0x204>
{
/* USER CODE BEGIN LTDC_MspInit 0 */
/* USER CODE END LTDC_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_LTDC_CLK_ENABLE();
8000f80: 2300 movs r3, #0
8000f82: 623b str r3, [r7, #32]
8000f84: 4b79 ldr r3, [pc, #484] ; (800116c <HAL_LTDC_MspInit+0x210>)
8000f86: 6c5b ldr r3, [r3, #68] ; 0x44
8000f88: 4a78 ldr r2, [pc, #480] ; (800116c <HAL_LTDC_MspInit+0x210>)
8000f8a: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000
8000f8e: 6453 str r3, [r2, #68] ; 0x44
8000f90: 4b76 ldr r3, [pc, #472] ; (800116c <HAL_LTDC_MspInit+0x210>)
8000f92: 6c5b ldr r3, [r3, #68] ; 0x44
8000f94: f003 6380 and.w r3, r3, #67108864 ; 0x4000000
8000f98: 623b str r3, [r7, #32]
8000f9a: 6a3b ldr r3, [r7, #32]
__HAL_RCC_GPIOF_CLK_ENABLE();
8000f9c: 2300 movs r3, #0
8000f9e: 61fb str r3, [r7, #28]
8000fa0: 4b72 ldr r3, [pc, #456] ; (800116c <HAL_LTDC_MspInit+0x210>)
8000fa2: 6b1b ldr r3, [r3, #48] ; 0x30
8000fa4: 4a71 ldr r2, [pc, #452] ; (800116c <HAL_LTDC_MspInit+0x210>)
8000fa6: f043 0320 orr.w r3, r3, #32
8000faa: 6313 str r3, [r2, #48] ; 0x30
8000fac: 4b6f ldr r3, [pc, #444] ; (800116c <HAL_LTDC_MspInit+0x210>)
8000fae: 6b1b ldr r3, [r3, #48] ; 0x30
8000fb0: f003 0320 and.w r3, r3, #32
8000fb4: 61fb str r3, [r7, #28]
8000fb6: 69fb ldr r3, [r7, #28]
__HAL_RCC_GPIOA_CLK_ENABLE();
8000fb8: 2300 movs r3, #0
8000fba: 61bb str r3, [r7, #24]
8000fbc: 4b6b ldr r3, [pc, #428] ; (800116c <HAL_LTDC_MspInit+0x210>)
8000fbe: 6b1b ldr r3, [r3, #48] ; 0x30
8000fc0: 4a6a ldr r2, [pc, #424] ; (800116c <HAL_LTDC_MspInit+0x210>)
8000fc2: f043 0301 orr.w r3, r3, #1
8000fc6: 6313 str r3, [r2, #48] ; 0x30
8000fc8: 4b68 ldr r3, [pc, #416] ; (800116c <HAL_LTDC_MspInit+0x210>)
8000fca: 6b1b ldr r3, [r3, #48] ; 0x30
8000fcc: f003 0301 and.w r3, r3, #1
8000fd0: 61bb str r3, [r7, #24]
8000fd2: 69bb ldr r3, [r7, #24]
__HAL_RCC_GPIOB_CLK_ENABLE();
8000fd4: 2300 movs r3, #0
8000fd6: 617b str r3, [r7, #20]
8000fd8: 4b64 ldr r3, [pc, #400] ; (800116c <HAL_LTDC_MspInit+0x210>)
8000fda: 6b1b ldr r3, [r3, #48] ; 0x30
8000fdc: 4a63 ldr r2, [pc, #396] ; (800116c <HAL_LTDC_MspInit+0x210>)
8000fde: f043 0302 orr.w r3, r3, #2
8000fe2: 6313 str r3, [r2, #48] ; 0x30
8000fe4: 4b61 ldr r3, [pc, #388] ; (800116c <HAL_LTDC_MspInit+0x210>)
8000fe6: 6b1b ldr r3, [r3, #48] ; 0x30
8000fe8: f003 0302 and.w r3, r3, #2
8000fec: 617b str r3, [r7, #20]
8000fee: 697b ldr r3, [r7, #20]
__HAL_RCC_GPIOG_CLK_ENABLE();
8000ff0: 2300 movs r3, #0
8000ff2: 613b str r3, [r7, #16]
8000ff4: 4b5d ldr r3, [pc, #372] ; (800116c <HAL_LTDC_MspInit+0x210>)
8000ff6: 6b1b ldr r3, [r3, #48] ; 0x30
8000ff8: 4a5c ldr r2, [pc, #368] ; (800116c <HAL_LTDC_MspInit+0x210>)
8000ffa: f043 0340 orr.w r3, r3, #64 ; 0x40
8000ffe: 6313 str r3, [r2, #48] ; 0x30
8001000: 4b5a ldr r3, [pc, #360] ; (800116c <HAL_LTDC_MspInit+0x210>)
8001002: 6b1b ldr r3, [r3, #48] ; 0x30
8001004: f003 0340 and.w r3, r3, #64 ; 0x40
8001008: 613b str r3, [r7, #16]
800100a: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOC_CLK_ENABLE();
800100c: 2300 movs r3, #0
800100e: 60fb str r3, [r7, #12]
8001010: 4b56 ldr r3, [pc, #344] ; (800116c <HAL_LTDC_MspInit+0x210>)
8001012: 6b1b ldr r3, [r3, #48] ; 0x30
8001014: 4a55 ldr r2, [pc, #340] ; (800116c <HAL_LTDC_MspInit+0x210>)
8001016: f043 0304 orr.w r3, r3, #4
800101a: 6313 str r3, [r2, #48] ; 0x30
800101c: 4b53 ldr r3, [pc, #332] ; (800116c <HAL_LTDC_MspInit+0x210>)
800101e: 6b1b ldr r3, [r3, #48] ; 0x30
8001020: f003 0304 and.w r3, r3, #4
8001024: 60fb str r3, [r7, #12]
8001026: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOD_CLK_ENABLE();
8001028: 2300 movs r3, #0
800102a: 60bb str r3, [r7, #8]
800102c: 4b4f ldr r3, [pc, #316] ; (800116c <HAL_LTDC_MspInit+0x210>)
800102e: 6b1b ldr r3, [r3, #48] ; 0x30
8001030: 4a4e ldr r2, [pc, #312] ; (800116c <HAL_LTDC_MspInit+0x210>)
8001032: f043 0308 orr.w r3, r3, #8
8001036: 6313 str r3, [r2, #48] ; 0x30
8001038: 4b4c ldr r3, [pc, #304] ; (800116c <HAL_LTDC_MspInit+0x210>)
800103a: 6b1b ldr r3, [r3, #48] ; 0x30
800103c: f003 0308 and.w r3, r3, #8
8001040: 60bb str r3, [r7, #8]
8001042: 68bb ldr r3, [r7, #8]
PG11 ------> LTDC_B3
PG12 ------> LTDC_B4
PB8 ------> LTDC_B6
PB9 ------> LTDC_B7
*/
GPIO_InitStruct.Pin = ENABLE_Pin;
8001044: f44f 6380 mov.w r3, #1024 ; 0x400
8001048: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800104a: 2302 movs r3, #2
800104c: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
800104e: 2300 movs r3, #0
8001050: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001052: 2300 movs r3, #0
8001054: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
8001056: 230e movs r3, #14
8001058: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(ENABLE_GPIO_Port, &GPIO_InitStruct);
800105a: f107 0324 add.w r3, r7, #36 ; 0x24
800105e: 4619 mov r1, r3
8001060: 4843 ldr r0, [pc, #268] ; (8001170 <HAL_LTDC_MspInit+0x214>)
8001062: f000 fe5b bl 8001d1c <HAL_GPIO_Init>
GPIO_InitStruct.Pin = B5_Pin|VSYNC_Pin|G2_Pin|R4_Pin
8001066: f641 0358 movw r3, #6232 ; 0x1858
800106a: 627b str r3, [r7, #36] ; 0x24
|R5_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800106c: 2302 movs r3, #2
800106e: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001070: 2300 movs r3, #0
8001072: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001074: 2300 movs r3, #0
8001076: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
8001078: 230e movs r3, #14
800107a: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
800107c: f107 0324 add.w r3, r7, #36 ; 0x24
8001080: 4619 mov r1, r3
8001082: 483c ldr r0, [pc, #240] ; (8001174 <HAL_LTDC_MspInit+0x218>)
8001084: f000 fe4a bl 8001d1c <HAL_GPIO_Init>
GPIO_InitStruct.Pin = R3_Pin|R6_Pin;
8001088: 2303 movs r3, #3
800108a: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800108c: 2302 movs r3, #2
800108e: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001090: 2300 movs r3, #0
8001092: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001094: 2300 movs r3, #0
8001096: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF9_LTDC;
8001098: 2309 movs r3, #9
800109a: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
800109c: f107 0324 add.w r3, r7, #36 ; 0x24
80010a0: 4619 mov r1, r3
80010a2: 4835 ldr r0, [pc, #212] ; (8001178 <HAL_LTDC_MspInit+0x21c>)
80010a4: f000 fe3a bl 8001d1c <HAL_GPIO_Init>
GPIO_InitStruct.Pin = G4_Pin|G5_Pin|B6_Pin|B7_Pin;
80010a8: f44f 6370 mov.w r3, #3840 ; 0xf00
80010ac: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80010ae: 2302 movs r3, #2
80010b0: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80010b2: 2300 movs r3, #0
80010b4: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80010b6: 2300 movs r3, #0
80010b8: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
80010ba: 230e movs r3, #14
80010bc: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80010be: f107 0324 add.w r3, r7, #36 ; 0x24
80010c2: 4619 mov r1, r3
80010c4: 482c ldr r0, [pc, #176] ; (8001178 <HAL_LTDC_MspInit+0x21c>)
80010c6: f000 fe29 bl 8001d1c <HAL_GPIO_Init>
GPIO_InitStruct.Pin = R7_Pin|DOTCLK_Pin|B3_Pin;
80010ca: f44f 630c mov.w r3, #2240 ; 0x8c0
80010ce: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80010d0: 2302 movs r3, #2
80010d2: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80010d4: 2300 movs r3, #0
80010d6: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80010d8: 2300 movs r3, #0
80010da: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
80010dc: 230e movs r3, #14
80010de: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
80010e0: f107 0324 add.w r3, r7, #36 ; 0x24
80010e4: 4619 mov r1, r3
80010e6: 4825 ldr r0, [pc, #148] ; (800117c <HAL_LTDC_MspInit+0x220>)
80010e8: f000 fe18 bl 8001d1c <HAL_GPIO_Init>
GPIO_InitStruct.Pin = HSYNC_Pin|G6_Pin|R2_Pin;
80010ec: f44f 6398 mov.w r3, #1216 ; 0x4c0
80010f0: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80010f2: 2302 movs r3, #2
80010f4: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
80010f6: 2300 movs r3, #0
80010f8: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80010fa: 2300 movs r3, #0
80010fc: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
80010fe: 230e movs r3, #14
8001100: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8001102: f107 0324 add.w r3, r7, #36 ; 0x24
8001106: 4619 mov r1, r3
8001108: 481d ldr r0, [pc, #116] ; (8001180 <HAL_LTDC_MspInit+0x224>)
800110a: f000 fe07 bl 8001d1c <HAL_GPIO_Init>
GPIO_InitStruct.Pin = G7_Pin|B2_Pin;
800110e: 2348 movs r3, #72 ; 0x48
8001110: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001112: 2302 movs r3, #2
8001114: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001116: 2300 movs r3, #0
8001118: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
800111a: 2300 movs r3, #0
800111c: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
800111e: 230e movs r3, #14
8001120: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
8001122: f107 0324 add.w r3, r7, #36 ; 0x24
8001126: 4619 mov r1, r3
8001128: 4816 ldr r0, [pc, #88] ; (8001184 <HAL_LTDC_MspInit+0x228>)
800112a: f000 fdf7 bl 8001d1c <HAL_GPIO_Init>
GPIO_InitStruct.Pin = G3_Pin|B4_Pin;
800112e: f44f 53a0 mov.w r3, #5120 ; 0x1400
8001132: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001134: 2302 movs r3, #2
8001136: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001138: 2300 movs r3, #0
800113a: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
800113c: 2300 movs r3, #0
800113e: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Alternate = GPIO_AF9_LTDC;
8001140: 2309 movs r3, #9
8001142: 637b str r3, [r7, #52] ; 0x34
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
8001144: f107 0324 add.w r3, r7, #36 ; 0x24
8001148: 4619 mov r1, r3
800114a: 480c ldr r0, [pc, #48] ; (800117c <HAL_LTDC_MspInit+0x220>)
800114c: f000 fde6 bl 8001d1c <HAL_GPIO_Init>
/* LTDC interrupt Init */
HAL_NVIC_SetPriority(LTDC_IRQn, 5, 0);
8001150: 2200 movs r2, #0
8001152: 2105 movs r1, #5
8001154: 2058 movs r0, #88 ; 0x58
8001156: f000 fbaf bl 80018b8 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(LTDC_IRQn);
800115a: 2058 movs r0, #88 ; 0x58
800115c: f000 fbc8 bl 80018f0 <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN LTDC_MspInit 1 */
/* USER CODE END LTDC_MspInit 1 */
}
}
8001160: bf00 nop
8001162: 3738 adds r7, #56 ; 0x38
8001164: 46bd mov sp, r7
8001166: bd80 pop {r7, pc}
8001168: 40016800 .word 0x40016800
800116c: 40023800 .word 0x40023800
8001170: 40021400 .word 0x40021400
8001174: 40020000 .word 0x40020000
8001178: 40020400 .word 0x40020400
800117c: 40021800 .word 0x40021800
8001180: 40020800 .word 0x40020800
8001184: 40020c00 .word 0x40020c00
08001188 <HAL_RNG_MspInit>:
* This function configures the hardware resources used in this example
* @param hrng: RNG handle pointer
* @retval None
*/
void HAL_RNG_MspInit(RNG_HandleTypeDef* hrng)
{
8001188: b580 push {r7, lr}
800118a: b084 sub sp, #16
800118c: af00 add r7, sp, #0
800118e: 6078 str r0, [r7, #4]
if(hrng->Instance==RNG)
8001190: 687b ldr r3, [r7, #4]
8001192: 681b ldr r3, [r3, #0]
8001194: 4a0e ldr r2, [pc, #56] ; (80011d0 <HAL_RNG_MspInit+0x48>)
8001196: 4293 cmp r3, r2
8001198: d115 bne.n 80011c6 <HAL_RNG_MspInit+0x3e>
{
/* USER CODE BEGIN RNG_MspInit 0 */
/* USER CODE END RNG_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_RNG_CLK_ENABLE();
800119a: 2300 movs r3, #0
800119c: 60fb str r3, [r7, #12]
800119e: 4b0d ldr r3, [pc, #52] ; (80011d4 <HAL_RNG_MspInit+0x4c>)
80011a0: 6b5b ldr r3, [r3, #52] ; 0x34
80011a2: 4a0c ldr r2, [pc, #48] ; (80011d4 <HAL_RNG_MspInit+0x4c>)
80011a4: f043 0340 orr.w r3, r3, #64 ; 0x40
80011a8: 6353 str r3, [r2, #52] ; 0x34
80011aa: 4b0a ldr r3, [pc, #40] ; (80011d4 <HAL_RNG_MspInit+0x4c>)
80011ac: 6b5b ldr r3, [r3, #52] ; 0x34
80011ae: f003 0340 and.w r3, r3, #64 ; 0x40
80011b2: 60fb str r3, [r7, #12]
80011b4: 68fb ldr r3, [r7, #12]
/* RNG interrupt Init */
HAL_NVIC_SetPriority(HASH_RNG_IRQn, 0, 0);
80011b6: 2200 movs r2, #0
80011b8: 2100 movs r1, #0
80011ba: 2050 movs r0, #80 ; 0x50
80011bc: f000 fb7c bl 80018b8 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(HASH_RNG_IRQn);
80011c0: 2050 movs r0, #80 ; 0x50
80011c2: f000 fb95 bl 80018f0 <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN RNG_MspInit 1 */
/* USER CODE END RNG_MspInit 1 */
}
}
80011c6: bf00 nop
80011c8: 3710 adds r7, #16
80011ca: 46bd mov sp, r7
80011cc: bd80 pop {r7, pc}
80011ce: bf00 nop
80011d0: 50060800 .word 0x50060800
80011d4: 40023800 .word 0x40023800
080011d8 <HAL_SPI_MspInit>:
* This function configures the hardware resources used in this example
* @param hspi: SPI handle pointer
* @retval None
*/
void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
{
80011d8: b580 push {r7, lr}
80011da: b08c sub sp, #48 ; 0x30
80011dc: af00 add r7, sp, #0
80011de: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
80011e0: f107 031c add.w r3, r7, #28
80011e4: 2200 movs r2, #0
80011e6: 601a str r2, [r3, #0]
80011e8: 605a str r2, [r3, #4]
80011ea: 609a str r2, [r3, #8]
80011ec: 60da str r2, [r3, #12]
80011ee: 611a str r2, [r3, #16]
if(hspi->Instance==SPI4)
80011f0: 687b ldr r3, [r7, #4]
80011f2: 681b ldr r3, [r3, #0]
80011f4: 4a32 ldr r2, [pc, #200] ; (80012c0 <HAL_SPI_MspInit+0xe8>)
80011f6: 4293 cmp r3, r2
80011f8: d12c bne.n 8001254 <HAL_SPI_MspInit+0x7c>
{
/* USER CODE BEGIN SPI4_MspInit 0 */
/* USER CODE END SPI4_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_SPI4_CLK_ENABLE();
80011fa: 2300 movs r3, #0
80011fc: 61bb str r3, [r7, #24]
80011fe: 4b31 ldr r3, [pc, #196] ; (80012c4 <HAL_SPI_MspInit+0xec>)
8001200: 6c5b ldr r3, [r3, #68] ; 0x44
8001202: 4a30 ldr r2, [pc, #192] ; (80012c4 <HAL_SPI_MspInit+0xec>)
8001204: f443 5300 orr.w r3, r3, #8192 ; 0x2000
8001208: 6453 str r3, [r2, #68] ; 0x44
800120a: 4b2e ldr r3, [pc, #184] ; (80012c4 <HAL_SPI_MspInit+0xec>)
800120c: 6c5b ldr r3, [r3, #68] ; 0x44
800120e: f403 5300 and.w r3, r3, #8192 ; 0x2000
8001212: 61bb str r3, [r7, #24]
8001214: 69bb ldr r3, [r7, #24]
__HAL_RCC_GPIOE_CLK_ENABLE();
8001216: 2300 movs r3, #0
8001218: 617b str r3, [r7, #20]
800121a: 4b2a ldr r3, [pc, #168] ; (80012c4 <HAL_SPI_MspInit+0xec>)
800121c: 6b1b ldr r3, [r3, #48] ; 0x30
800121e: 4a29 ldr r2, [pc, #164] ; (80012c4 <HAL_SPI_MspInit+0xec>)
8001220: f043 0310 orr.w r3, r3, #16
8001224: 6313 str r3, [r2, #48] ; 0x30
8001226: 4b27 ldr r3, [pc, #156] ; (80012c4 <HAL_SPI_MspInit+0xec>)
8001228: 6b1b ldr r3, [r3, #48] ; 0x30
800122a: f003 0310 and.w r3, r3, #16
800122e: 617b str r3, [r7, #20]
8001230: 697b ldr r3, [r7, #20]
/**SPI4 GPIO Configuration
PE2 ------> SPI4_SCK
PE6 ------> SPI4_MOSI
*/
GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_6;
8001232: 2344 movs r3, #68 ; 0x44
8001234: 61fb str r3, [r7, #28]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001236: 2302 movs r3, #2
8001238: 623b str r3, [r7, #32]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800123a: 2300 movs r3, #0
800123c: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
800123e: 2303 movs r3, #3
8001240: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Alternate = GPIO_AF5_SPI4;
8001242: 2305 movs r3, #5
8001244: 62fb str r3, [r7, #44] ; 0x2c
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
8001246: f107 031c add.w r3, r7, #28
800124a: 4619 mov r1, r3
800124c: 481e ldr r0, [pc, #120] ; (80012c8 <HAL_SPI_MspInit+0xf0>)
800124e: f000 fd65 bl 8001d1c <HAL_GPIO_Init>
/* USER CODE BEGIN SPI5_MspInit 1 */
/* USER CODE END SPI5_MspInit 1 */
}
}
8001252: e031 b.n 80012b8 <HAL_SPI_MspInit+0xe0>
else if(hspi->Instance==SPI5)
8001254: 687b ldr r3, [r7, #4]
8001256: 681b ldr r3, [r3, #0]
8001258: 4a1c ldr r2, [pc, #112] ; (80012cc <HAL_SPI_MspInit+0xf4>)
800125a: 4293 cmp r3, r2
800125c: d12c bne.n 80012b8 <HAL_SPI_MspInit+0xe0>
__HAL_RCC_SPI5_CLK_ENABLE();
800125e: 2300 movs r3, #0
8001260: 613b str r3, [r7, #16]
8001262: 4b18 ldr r3, [pc, #96] ; (80012c4 <HAL_SPI_MspInit+0xec>)
8001264: 6c5b ldr r3, [r3, #68] ; 0x44
8001266: 4a17 ldr r2, [pc, #92] ; (80012c4 <HAL_SPI_MspInit+0xec>)
8001268: f443 1380 orr.w r3, r3, #1048576 ; 0x100000
800126c: 6453 str r3, [r2, #68] ; 0x44
800126e: 4b15 ldr r3, [pc, #84] ; (80012c4 <HAL_SPI_MspInit+0xec>)
8001270: 6c5b ldr r3, [r3, #68] ; 0x44
8001272: f403 1380 and.w r3, r3, #1048576 ; 0x100000
8001276: 613b str r3, [r7, #16]
8001278: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOF_CLK_ENABLE();
800127a: 2300 movs r3, #0
800127c: 60fb str r3, [r7, #12]
800127e: 4b11 ldr r3, [pc, #68] ; (80012c4 <HAL_SPI_MspInit+0xec>)
8001280: 6b1b ldr r3, [r3, #48] ; 0x30
8001282: 4a10 ldr r2, [pc, #64] ; (80012c4 <HAL_SPI_MspInit+0xec>)
8001284: f043 0320 orr.w r3, r3, #32
8001288: 6313 str r3, [r2, #48] ; 0x30
800128a: 4b0e ldr r3, [pc, #56] ; (80012c4 <HAL_SPI_MspInit+0xec>)
800128c: 6b1b ldr r3, [r3, #48] ; 0x30
800128e: f003 0320 and.w r3, r3, #32
8001292: 60fb str r3, [r7, #12]
8001294: 68fb ldr r3, [r7, #12]
GPIO_InitStruct.Pin = SPI5_SCK_Pin|SPI5_MISO_Pin|SPI5_MOSI_Pin;
8001296: f44f 7360 mov.w r3, #896 ; 0x380
800129a: 61fb str r3, [r7, #28]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800129c: 2302 movs r3, #2
800129e: 623b str r3, [r7, #32]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80012a0: 2300 movs r3, #0
80012a2: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80012a4: 2300 movs r3, #0
80012a6: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Alternate = GPIO_AF5_SPI5;
80012a8: 2305 movs r3, #5
80012aa: 62fb str r3, [r7, #44] ; 0x2c
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
80012ac: f107 031c add.w r3, r7, #28
80012b0: 4619 mov r1, r3
80012b2: 4807 ldr r0, [pc, #28] ; (80012d0 <HAL_SPI_MspInit+0xf8>)
80012b4: f000 fd32 bl 8001d1c <HAL_GPIO_Init>
}
80012b8: bf00 nop
80012ba: 3730 adds r7, #48 ; 0x30
80012bc: 46bd mov sp, r7
80012be: bd80 pop {r7, pc}
80012c0: 40013400 .word 0x40013400
80012c4: 40023800 .word 0x40023800
80012c8: 40021000 .word 0x40021000
80012cc: 40015000 .word 0x40015000
80012d0: 40021400 .word 0x40021400
080012d4 <HAL_TIM_Base_MspInit>:
* This function configures the hardware resources used in this example
* @param htim_base: TIM_Base handle pointer
* @retval None
*/
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
{
80012d4: b480 push {r7}
80012d6: b085 sub sp, #20
80012d8: af00 add r7, sp, #0
80012da: 6078 str r0, [r7, #4]
if(htim_base->Instance==TIM1)
80012dc: 687b ldr r3, [r7, #4]
80012de: 681b ldr r3, [r3, #0]
80012e0: 4a0b ldr r2, [pc, #44] ; (8001310 <HAL_TIM_Base_MspInit+0x3c>)
80012e2: 4293 cmp r3, r2
80012e4: d10d bne.n 8001302 <HAL_TIM_Base_MspInit+0x2e>
{
/* USER CODE BEGIN TIM1_MspInit 0 */
/* USER CODE END TIM1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_TIM1_CLK_ENABLE();
80012e6: 2300 movs r3, #0
80012e8: 60fb str r3, [r7, #12]
80012ea: 4b0a ldr r3, [pc, #40] ; (8001314 <HAL_TIM_Base_MspInit+0x40>)
80012ec: 6c5b ldr r3, [r3, #68] ; 0x44
80012ee: 4a09 ldr r2, [pc, #36] ; (8001314 <HAL_TIM_Base_MspInit+0x40>)
80012f0: f043 0301 orr.w r3, r3, #1
80012f4: 6453 str r3, [r2, #68] ; 0x44
80012f6: 4b07 ldr r3, [pc, #28] ; (8001314 <HAL_TIM_Base_MspInit+0x40>)
80012f8: 6c5b ldr r3, [r3, #68] ; 0x44
80012fa: f003 0301 and.w r3, r3, #1
80012fe: 60fb str r3, [r7, #12]
8001300: 68fb ldr r3, [r7, #12]
/* USER CODE BEGIN TIM1_MspInit 1 */
/* USER CODE END TIM1_MspInit 1 */
}
}
8001302: bf00 nop
8001304: 3714 adds r7, #20
8001306: 46bd mov sp, r7
8001308: f85d 7b04 ldr.w r7, [sp], #4
800130c: 4770 bx lr
800130e: bf00 nop
8001310: 40010000 .word 0x40010000
8001314: 40023800 .word 0x40023800
08001318 <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
8001318: b580 push {r7, lr}
800131a: b08a sub sp, #40 ; 0x28
800131c: af00 add r7, sp, #0
800131e: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001320: f107 0314 add.w r3, r7, #20
8001324: 2200 movs r2, #0
8001326: 601a str r2, [r3, #0]
8001328: 605a str r2, [r3, #4]
800132a: 609a str r2, [r3, #8]
800132c: 60da str r2, [r3, #12]
800132e: 611a str r2, [r3, #16]
if(huart->Instance==USART1)
8001330: 687b ldr r3, [r7, #4]
8001332: 681b ldr r3, [r3, #0]
8001334: 4a19 ldr r2, [pc, #100] ; (800139c <HAL_UART_MspInit+0x84>)
8001336: 4293 cmp r3, r2
8001338: d12c bne.n 8001394 <HAL_UART_MspInit+0x7c>
{
/* USER CODE BEGIN USART1_MspInit 0 */
/* USER CODE END USART1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_USART1_CLK_ENABLE();
800133a: 2300 movs r3, #0
800133c: 613b str r3, [r7, #16]
800133e: 4b18 ldr r3, [pc, #96] ; (80013a0 <HAL_UART_MspInit+0x88>)
8001340: 6c5b ldr r3, [r3, #68] ; 0x44
8001342: 4a17 ldr r2, [pc, #92] ; (80013a0 <HAL_UART_MspInit+0x88>)
8001344: f043 0310 orr.w r3, r3, #16
8001348: 6453 str r3, [r2, #68] ; 0x44
800134a: 4b15 ldr r3, [pc, #84] ; (80013a0 <HAL_UART_MspInit+0x88>)
800134c: 6c5b ldr r3, [r3, #68] ; 0x44
800134e: f003 0310 and.w r3, r3, #16
8001352: 613b str r3, [r7, #16]
8001354: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
8001356: 2300 movs r3, #0
8001358: 60fb str r3, [r7, #12]
800135a: 4b11 ldr r3, [pc, #68] ; (80013a0 <HAL_UART_MspInit+0x88>)
800135c: 6b1b ldr r3, [r3, #48] ; 0x30
800135e: 4a10 ldr r2, [pc, #64] ; (80013a0 <HAL_UART_MspInit+0x88>)
8001360: f043 0301 orr.w r3, r3, #1
8001364: 6313 str r3, [r2, #48] ; 0x30
8001366: 4b0e ldr r3, [pc, #56] ; (80013a0 <HAL_UART_MspInit+0x88>)
8001368: 6b1b ldr r3, [r3, #48] ; 0x30
800136a: f003 0301 and.w r3, r3, #1
800136e: 60fb str r3, [r7, #12]
8001370: 68fb ldr r3, [r7, #12]
/**USART1 GPIO Configuration
PA9 ------> USART1_TX
PA10 ------> USART1_RX
*/
GPIO_InitStruct.Pin = STLINK_RX_Pin|STLINK_TX_Pin;
8001372: f44f 63c0 mov.w r3, #1536 ; 0x600
8001376: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001378: 2302 movs r3, #2
800137a: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800137c: 2300 movs r3, #0
800137e: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001380: 2303 movs r3, #3
8001382: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
8001384: 2307 movs r3, #7
8001386: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001388: f107 0314 add.w r3, r7, #20
800138c: 4619 mov r1, r3
800138e: 4805 ldr r0, [pc, #20] ; (80013a4 <HAL_UART_MspInit+0x8c>)
8001390: f000 fcc4 bl 8001d1c <HAL_GPIO_Init>
/* USER CODE BEGIN USART1_MspInit 1 */
/* USER CODE END USART1_MspInit 1 */
}
}
8001394: bf00 nop
8001396: 3728 adds r7, #40 ; 0x28
8001398: 46bd mov sp, r7
800139a: bd80 pop {r7, pc}
800139c: 40011000 .word 0x40011000
80013a0: 40023800 .word 0x40023800
80013a4: 40020000 .word 0x40020000
080013a8 <HAL_FMC_MspInit>:
}
static uint32_t FMC_Initialized = 0;
static void HAL_FMC_MspInit(void){
80013a8: b580 push {r7, lr}
80013aa: b086 sub sp, #24
80013ac: af00 add r7, sp, #0
/* USER CODE BEGIN FMC_MspInit 0 */
/* USER CODE END FMC_MspInit 0 */
GPIO_InitTypeDef GPIO_InitStruct ={0};
80013ae: 1d3b adds r3, r7, #4
80013b0: 2200 movs r2, #0
80013b2: 601a str r2, [r3, #0]
80013b4: 605a str r2, [r3, #4]
80013b6: 609a str r2, [r3, #8]
80013b8: 60da str r2, [r3, #12]
80013ba: 611a str r2, [r3, #16]
if (FMC_Initialized) {
80013bc: 4b3b ldr r3, [pc, #236] ; (80014ac <HAL_FMC_MspInit+0x104>)
80013be: 681b ldr r3, [r3, #0]
80013c0: 2b00 cmp r3, #0
80013c2: d16f bne.n 80014a4 <HAL_FMC_MspInit+0xfc>
return;
}
FMC_Initialized = 1;
80013c4: 4b39 ldr r3, [pc, #228] ; (80014ac <HAL_FMC_MspInit+0x104>)
80013c6: 2201 movs r2, #1
80013c8: 601a str r2, [r3, #0]
/* Peripheral clock enable */
__HAL_RCC_FMC_CLK_ENABLE();
80013ca: 2300 movs r3, #0
80013cc: 603b str r3, [r7, #0]
80013ce: 4b38 ldr r3, [pc, #224] ; (80014b0 <HAL_FMC_MspInit+0x108>)
80013d0: 6b9b ldr r3, [r3, #56] ; 0x38
80013d2: 4a37 ldr r2, [pc, #220] ; (80014b0 <HAL_FMC_MspInit+0x108>)
80013d4: f043 0301 orr.w r3, r3, #1
80013d8: 6393 str r3, [r2, #56] ; 0x38
80013da: 4b35 ldr r3, [pc, #212] ; (80014b0 <HAL_FMC_MspInit+0x108>)
80013dc: 6b9b ldr r3, [r3, #56] ; 0x38
80013de: f003 0301 and.w r3, r3, #1
80013e2: 603b str r3, [r7, #0]
80013e4: 683b ldr r3, [r7, #0]
PB5 ------> FMC_SDCKE1
PB6 ------> FMC_SDNE1
PE0 ------> FMC_NBL0
PE1 ------> FMC_NBL1
*/
GPIO_InitStruct.Pin = A0_Pin|A1_Pin|A2_Pin|A3_Pin
80013e6: f64f 033f movw r3, #63551 ; 0xf83f
80013ea: 607b str r3, [r7, #4]
|A4_Pin|A5_Pin|SDNRAS_Pin|A6_Pin
|A7_Pin|A8_Pin|A9_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80013ec: 2302 movs r3, #2
80013ee: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80013f0: 2300 movs r3, #0
80013f2: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
80013f4: 2303 movs r3, #3
80013f6: 613b str r3, [r7, #16]
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
80013f8: 230c movs r3, #12
80013fa: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
80013fc: 1d3b adds r3, r7, #4
80013fe: 4619 mov r1, r3
8001400: 482c ldr r0, [pc, #176] ; (80014b4 <HAL_FMC_MspInit+0x10c>)
8001402: f000 fc8b bl 8001d1c <HAL_GPIO_Init>
GPIO_InitStruct.Pin = SDNWE_Pin;
8001406: 2301 movs r3, #1
8001408: 607b str r3, [r7, #4]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800140a: 2302 movs r3, #2
800140c: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800140e: 2300 movs r3, #0
8001410: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001412: 2303 movs r3, #3
8001414: 613b str r3, [r7, #16]
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
8001416: 230c movs r3, #12
8001418: 617b str r3, [r7, #20]
HAL_GPIO_Init(SDNWE_GPIO_Port, &GPIO_InitStruct);
800141a: 1d3b adds r3, r7, #4
800141c: 4619 mov r1, r3
800141e: 4826 ldr r0, [pc, #152] ; (80014b8 <HAL_FMC_MspInit+0x110>)
8001420: f000 fc7c bl 8001d1c <HAL_GPIO_Init>
GPIO_InitStruct.Pin = A10_Pin|A11_Pin|BA0_Pin|BA1_Pin
8001424: f248 1333 movw r3, #33075 ; 0x8133
8001428: 607b str r3, [r7, #4]
|SDCLK_Pin|SDNCAS_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800142a: 2302 movs r3, #2
800142c: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800142e: 2300 movs r3, #0
8001430: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001432: 2303 movs r3, #3
8001434: 613b str r3, [r7, #16]
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
8001436: 230c movs r3, #12
8001438: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
800143a: 1d3b adds r3, r7, #4
800143c: 4619 mov r1, r3
800143e: 481f ldr r0, [pc, #124] ; (80014bc <HAL_FMC_MspInit+0x114>)
8001440: f000 fc6c bl 8001d1c <HAL_GPIO_Init>
GPIO_InitStruct.Pin = D4_Pin|D5_Pin|D6_Pin|D7_Pin
8001444: f64f 7383 movw r3, #65411 ; 0xff83
8001448: 607b str r3, [r7, #4]
|D8_Pin|D9_Pin|D10_Pin|D11_Pin
|D12_Pin|NBL0_Pin|NBL1_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800144a: 2302 movs r3, #2
800144c: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800144e: 2300 movs r3, #0
8001450: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001452: 2303 movs r3, #3
8001454: 613b str r3, [r7, #16]
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
8001456: 230c movs r3, #12
8001458: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
800145a: 1d3b adds r3, r7, #4
800145c: 4619 mov r1, r3
800145e: 4818 ldr r0, [pc, #96] ; (80014c0 <HAL_FMC_MspInit+0x118>)
8001460: f000 fc5c bl 8001d1c <HAL_GPIO_Init>
GPIO_InitStruct.Pin = D13_Pin|D14_Pin|D15_Pin|D0_Pin
8001464: f24c 7303 movw r3, #50947 ; 0xc703
8001468: 607b str r3, [r7, #4]
|D1_Pin|D2_Pin|D3_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800146a: 2302 movs r3, #2
800146c: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800146e: 2300 movs r3, #0
8001470: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001472: 2303 movs r3, #3
8001474: 613b str r3, [r7, #16]
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
8001476: 230c movs r3, #12
8001478: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
800147a: 1d3b adds r3, r7, #4
800147c: 4619 mov r1, r3
800147e: 4811 ldr r0, [pc, #68] ; (80014c4 <HAL_FMC_MspInit+0x11c>)
8001480: f000 fc4c bl 8001d1c <HAL_GPIO_Init>
GPIO_InitStruct.Pin = SDCKE1_Pin|SDNE1_Pin;
8001484: 2360 movs r3, #96 ; 0x60
8001486: 607b str r3, [r7, #4]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001488: 2302 movs r3, #2
800148a: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800148c: 2300 movs r3, #0
800148e: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001490: 2303 movs r3, #3
8001492: 613b str r3, [r7, #16]
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
8001494: 230c movs r3, #12
8001496: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8001498: 1d3b adds r3, r7, #4
800149a: 4619 mov r1, r3
800149c: 480a ldr r0, [pc, #40] ; (80014c8 <HAL_FMC_MspInit+0x120>)
800149e: f000 fc3d bl 8001d1c <HAL_GPIO_Init>
80014a2: e000 b.n 80014a6 <HAL_FMC_MspInit+0xfe>
return;
80014a4: bf00 nop
/* USER CODE BEGIN FMC_MspInit 1 */
/* USER CODE END FMC_MspInit 1 */
}
80014a6: 3718 adds r7, #24
80014a8: 46bd mov sp, r7
80014aa: bd80 pop {r7, pc}
80014ac: 20000028 .word 0x20000028
80014b0: 40023800 .word 0x40023800
80014b4: 40021400 .word 0x40021400
80014b8: 40020800 .word 0x40020800
80014bc: 40021800 .word 0x40021800
80014c0: 40021000 .word 0x40021000
80014c4: 40020c00 .word 0x40020c00
80014c8: 40020400 .word 0x40020400
080014cc <HAL_SDRAM_MspInit>:
void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef* hsdram){
80014cc: b580 push {r7, lr}
80014ce: b082 sub sp, #8
80014d0: af00 add r7, sp, #0
80014d2: 6078 str r0, [r7, #4]
/* USER CODE BEGIN SDRAM_MspInit 0 */
/* USER CODE END SDRAM_MspInit 0 */
HAL_FMC_MspInit();
80014d4: f7ff ff68 bl 80013a8 <HAL_FMC_MspInit>
/* USER CODE BEGIN SDRAM_MspInit 1 */
/* USER CODE END SDRAM_MspInit 1 */
}
80014d8: bf00 nop
80014da: 3708 adds r7, #8
80014dc: 46bd mov sp, r7
80014de: bd80 pop {r7, pc}
080014e0 <HAL_InitTick>:
* reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
* @param TickPriority: Tick interrupt priority.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
80014e0: b580 push {r7, lr}
80014e2: b08c sub sp, #48 ; 0x30
80014e4: af00 add r7, sp, #0
80014e6: 6078 str r0, [r7, #4]
RCC_ClkInitTypeDef clkconfig;
uint32_t uwTimclock = 0;
80014e8: 2300 movs r3, #0
80014ea: 62fb str r3, [r7, #44] ; 0x2c
uint32_t uwPrescalerValue = 0;
80014ec: 2300 movs r3, #0
80014ee: 62bb str r3, [r7, #40] ; 0x28
uint32_t pFLatency;
/*Configure the TIM6 IRQ priority */
HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority ,0);
80014f0: 2200 movs r2, #0
80014f2: 6879 ldr r1, [r7, #4]
80014f4: 2036 movs r0, #54 ; 0x36
80014f6: f000 f9df bl 80018b8 <HAL_NVIC_SetPriority>
/* Enable the TIM6 global Interrupt */
HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
80014fa: 2036 movs r0, #54 ; 0x36
80014fc: f000 f9f8 bl 80018f0 <HAL_NVIC_EnableIRQ>
/* Enable TIM6 clock */
__HAL_RCC_TIM6_CLK_ENABLE();
8001500: 2300 movs r3, #0
8001502: 60fb str r3, [r7, #12]
8001504: 4b1f ldr r3, [pc, #124] ; (8001584 <HAL_InitTick+0xa4>)
8001506: 6c1b ldr r3, [r3, #64] ; 0x40
8001508: 4a1e ldr r2, [pc, #120] ; (8001584 <HAL_InitTick+0xa4>)
800150a: f043 0310 orr.w r3, r3, #16
800150e: 6413 str r3, [r2, #64] ; 0x40
8001510: 4b1c ldr r3, [pc, #112] ; (8001584 <HAL_InitTick+0xa4>)
8001512: 6c1b ldr r3, [r3, #64] ; 0x40
8001514: f003 0310 and.w r3, r3, #16
8001518: 60fb str r3, [r7, #12]
800151a: 68fb ldr r3, [r7, #12]
/* Get clock configuration */
HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
800151c: f107 0210 add.w r2, r7, #16
8001520: f107 0314 add.w r3, r7, #20
8001524: 4611 mov r1, r2
8001526: 4618 mov r0, r3
8001528: f001 ff3a bl 80033a0 <HAL_RCC_GetClockConfig>
/* Compute TIM6 clock */
uwTimclock = 2*HAL_RCC_GetPCLK1Freq();
800152c: f001 ff10 bl 8003350 <HAL_RCC_GetPCLK1Freq>
8001530: 4603 mov r3, r0
8001532: 005b lsls r3, r3, #1
8001534: 62fb str r3, [r7, #44] ; 0x2c
/* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */
uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000) - 1);
8001536: 6afb ldr r3, [r7, #44] ; 0x2c
8001538: 4a13 ldr r2, [pc, #76] ; (8001588 <HAL_InitTick+0xa8>)
800153a: fba2 2303 umull r2, r3, r2, r3
800153e: 0c9b lsrs r3, r3, #18
8001540: 3b01 subs r3, #1
8001542: 62bb str r3, [r7, #40] ; 0x28
/* Initialize TIM6 */
htim6.Instance = TIM6;
8001544: 4b11 ldr r3, [pc, #68] ; (800158c <HAL_InitTick+0xac>)
8001546: 4a12 ldr r2, [pc, #72] ; (8001590 <HAL_InitTick+0xb0>)
8001548: 601a str r2, [r3, #0]
+ Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base.
+ Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
+ ClockDivision = 0
+ Counter direction = Up
*/
htim6.Init.Period = (1000000 / 1000) - 1;
800154a: 4b10 ldr r3, [pc, #64] ; (800158c <HAL_InitTick+0xac>)
800154c: f240 32e7 movw r2, #999 ; 0x3e7
8001550: 60da str r2, [r3, #12]
htim6.Init.Prescaler = uwPrescalerValue;
8001552: 4a0e ldr r2, [pc, #56] ; (800158c <HAL_InitTick+0xac>)
8001554: 6abb ldr r3, [r7, #40] ; 0x28
8001556: 6053 str r3, [r2, #4]
htim6.Init.ClockDivision = 0;
8001558: 4b0c ldr r3, [pc, #48] ; (800158c <HAL_InitTick+0xac>)
800155a: 2200 movs r2, #0
800155c: 611a str r2, [r3, #16]
htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
800155e: 4b0b ldr r3, [pc, #44] ; (800158c <HAL_InitTick+0xac>)
8001560: 2200 movs r2, #0
8001562: 609a str r2, [r3, #8]
if(HAL_TIM_Base_Init(&htim6) == HAL_OK)
8001564: 4809 ldr r0, [pc, #36] ; (800158c <HAL_InitTick+0xac>)
8001566: f002 fa38 bl 80039da <HAL_TIM_Base_Init>
800156a: 4603 mov r3, r0
800156c: 2b00 cmp r3, #0
800156e: d104 bne.n 800157a <HAL_InitTick+0x9a>
{
/* Start the TIM time Base generation in interrupt mode */
return HAL_TIM_Base_Start_IT(&htim6);
8001570: 4806 ldr r0, [pc, #24] ; (800158c <HAL_InitTick+0xac>)
8001572: f002 fa5d bl 8003a30 <HAL_TIM_Base_Start_IT>
8001576: 4603 mov r3, r0
8001578: e000 b.n 800157c <HAL_InitTick+0x9c>
}
/* Return function status */
return HAL_ERROR;
800157a: 2301 movs r3, #1
}
800157c: 4618 mov r0, r3
800157e: 3730 adds r7, #48 ; 0x30
8001580: 46bd mov sp, r7
8001582: bd80 pop {r7, pc}
8001584: 40023800 .word 0x40023800
8001588: 431bde83 .word 0x431bde83
800158c: 200002e4 .word 0x200002e4
8001590: 40001000 .word 0x40001000
08001594 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8001594: b480 push {r7}
8001596: af00 add r7, sp, #0
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
/* USER CODE END NonMaskableInt_IRQn 1 */
}
8001598: bf00 nop
800159a: 46bd mov sp, r7
800159c: f85d 7b04 ldr.w r7, [sp], #4
80015a0: 4770 bx lr
080015a2 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
80015a2: b480 push {r7}
80015a4: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
80015a6: e7fe b.n 80015a6 <HardFault_Handler+0x4>
080015a8 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
80015a8: b480 push {r7}
80015aa: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
80015ac: e7fe b.n 80015ac <MemManage_Handler+0x4>
080015ae <BusFault_Handler>:
/**
* @brief This function handles Pre-fetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
80015ae: b480 push {r7}
80015b0: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
80015b2: e7fe b.n 80015b2 <BusFault_Handler+0x4>
080015b4 <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
80015b4: b480 push {r7}
80015b6: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
80015b8: e7fe b.n 80015b8 <UsageFault_Handler+0x4>
080015ba <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
80015ba: b480 push {r7}
80015bc: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
80015be: bf00 nop
80015c0: 46bd mov sp, r7
80015c2: f85d 7b04 ldr.w r7, [sp], #4
80015c6: 4770 bx lr
080015c8 <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
80015c8: b480 push {r7}
80015ca: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
80015cc: bf00 nop
80015ce: 46bd mov sp, r7
80015d0: f85d 7b04 ldr.w r7, [sp], #4
80015d4: 4770 bx lr
080015d6 <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
80015d6: b480 push {r7}
80015d8: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
80015da: bf00 nop
80015dc: 46bd mov sp, r7
80015de: f85d 7b04 ldr.w r7, [sp], #4
80015e2: 4770 bx lr
080015e4 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
80015e4: b480 push {r7}
80015e6: af00 add r7, sp, #0
/* USER CODE END SysTick_IRQn 0 */
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
80015e8: bf00 nop
80015ea: 46bd mov sp, r7
80015ec: f85d 7b04 ldr.w r7, [sp], #4
80015f0: 4770 bx lr
...
080015f4 <TIM6_DAC_IRQHandler>:
/**
* @brief This function handles TIM6 global interrupt, DAC1 and DAC2 underrun error interrupts.
*/
void TIM6_DAC_IRQHandler(void)
{
80015f4: b580 push {r7, lr}
80015f6: af00 add r7, sp, #0
/* USER CODE BEGIN TIM6_DAC_IRQn 0 */
/* USER CODE END TIM6_DAC_IRQn 0 */
HAL_TIM_IRQHandler(&htim6);
80015f8: 4802 ldr r0, [pc, #8] ; (8001604 <TIM6_DAC_IRQHandler+0x10>)
80015fa: f002 fa3d bl 8003a78 <HAL_TIM_IRQHandler>
/* USER CODE BEGIN TIM6_DAC_IRQn 1 */
/* USER CODE END TIM6_DAC_IRQn 1 */
}
80015fe: bf00 nop
8001600: bd80 pop {r7, pc}
8001602: bf00 nop
8001604: 200002e4 .word 0x200002e4
08001608 <HASH_RNG_IRQHandler>:
/**
* @brief This function handles HASH and RNG global interrupts.
*/
void HASH_RNG_IRQHandler(void)
{
8001608: b580 push {r7, lr}
800160a: af00 add r7, sp, #0
/* USER CODE BEGIN HASH_RNG_IRQn 0 */
/* USER CODE END HASH_RNG_IRQn 0 */
HAL_RNG_IRQHandler(&hrng);
800160c: 4802 ldr r0, [pc, #8] ; (8001618 <HASH_RNG_IRQHandler+0x10>)
800160e: f002 f8e1 bl 80037d4 <HAL_RNG_IRQHandler>
/* USER CODE BEGIN HASH_RNG_IRQn 1 */
/* USER CODE END HASH_RNG_IRQn 1 */
}
8001612: bf00 nop
8001614: bd80 pop {r7, pc}
8001616: bf00 nop
8001618: 20000260 .word 0x20000260
0800161c <LTDC_IRQHandler>:
/**
* @brief This function handles LTDC global interrupt.
*/
void LTDC_IRQHandler(void)
{
800161c: b580 push {r7, lr}
800161e: af00 add r7, sp, #0
/* USER CODE BEGIN LTDC_IRQn 0 */
/* USER CODE END LTDC_IRQn 0 */
HAL_LTDC_IRQHandler(&hltdc);
8001620: 4802 ldr r0, [pc, #8] ; (800162c <LTDC_IRQHandler+0x10>)
8001622: f000 ffc3 bl 80025ac <HAL_LTDC_IRQHandler>
/* USER CODE BEGIN LTDC_IRQn 1 */
/* USER CODE END LTDC_IRQn 1 */
}
8001626: bf00 nop
8001628: bd80 pop {r7, pc}
800162a: bf00 nop
800162c: 200000e0 .word 0x200000e0
08001630 <DMA2D_IRQHandler>:
/**
* @brief This function handles DMA2D global interrupt.
*/
void DMA2D_IRQHandler(void)
{
8001630: b580 push {r7, lr}
8001632: af00 add r7, sp, #0
/* USER CODE BEGIN DMA2D_IRQn 0 */
/* USER CODE END DMA2D_IRQn 0 */
HAL_DMA2D_IRQHandler(&hdma2d);
8001634: 4802 ldr r0, [pc, #8] ; (8001640 <DMA2D_IRQHandler+0x10>)
8001636: f000 f9ce bl 80019d6 <HAL_DMA2D_IRQHandler>
/* USER CODE BEGIN DMA2D_IRQn 1 */
/* USER CODE END DMA2D_IRQn 1 */
}
800163a: bf00 nop
800163c: bd80 pop {r7, pc}
800163e: bf00 nop
8001640: 20000270 .word 0x20000270
08001644 <SystemInit>:
* configuration.
* @param None
* @retval None
*/
void SystemInit(void)
{
8001644: b480 push {r7}
8001646: af00 add r7, sp, #0
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
8001648: 4b08 ldr r3, [pc, #32] ; (800166c <SystemInit+0x28>)
800164a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
800164e: 4a07 ldr r2, [pc, #28] ; (800166c <SystemInit+0x28>)
8001650: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
8001654: f8c2 3088 str.w r3, [r2, #136] ; 0x88
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
8001658: 4b04 ldr r3, [pc, #16] ; (800166c <SystemInit+0x28>)
800165a: f04f 6200 mov.w r2, #134217728 ; 0x8000000
800165e: 609a str r2, [r3, #8]
#endif
}
8001660: bf00 nop
8001662: 46bd mov sp, r7
8001664: f85d 7b04 ldr.w r7, [sp], #4
8001668: 4770 bx lr
800166a: bf00 nop
800166c: e000ed00 .word 0xe000ed00
08001670 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
8001670: f8df d034 ldr.w sp, [pc, #52] ; 80016a8 <LoopFillZerobss+0x14>
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
8001674: 2100 movs r1, #0
b LoopCopyDataInit
8001676: e003 b.n 8001680 <LoopCopyDataInit>
08001678 <CopyDataInit>:
CopyDataInit:
ldr r3, =_sidata
8001678: 4b0c ldr r3, [pc, #48] ; (80016ac <LoopFillZerobss+0x18>)
ldr r3, [r3, r1]
800167a: 585b ldr r3, [r3, r1]
str r3, [r0, r1]
800167c: 5043 str r3, [r0, r1]
adds r1, r1, #4
800167e: 3104 adds r1, #4
08001680 <LoopCopyDataInit>:
LoopCopyDataInit:
ldr r0, =_sdata
8001680: 480b ldr r0, [pc, #44] ; (80016b0 <LoopFillZerobss+0x1c>)
ldr r3, =_edata
8001682: 4b0c ldr r3, [pc, #48] ; (80016b4 <LoopFillZerobss+0x20>)
adds r2, r0, r1
8001684: 1842 adds r2, r0, r1
cmp r2, r3
8001686: 429a cmp r2, r3
bcc CopyDataInit
8001688: d3f6 bcc.n 8001678 <CopyDataInit>
ldr r2, =_sbss
800168a: 4a0b ldr r2, [pc, #44] ; (80016b8 <LoopFillZerobss+0x24>)
b LoopFillZerobss
800168c: e002 b.n 8001694 <LoopFillZerobss>
0800168e <FillZerobss>:
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
800168e: 2300 movs r3, #0
str r3, [r2], #4
8001690: f842 3b04 str.w r3, [r2], #4
08001694 <LoopFillZerobss>:
LoopFillZerobss:
ldr r3, = _ebss
8001694: 4b09 ldr r3, [pc, #36] ; (80016bc <LoopFillZerobss+0x28>)
cmp r2, r3
8001696: 429a cmp r2, r3
bcc FillZerobss
8001698: d3f9 bcc.n 800168e <FillZerobss>
/* Call the clock system intitialization function.*/
bl SystemInit
800169a: f7ff ffd3 bl 8001644 <SystemInit>
/* Call static constructors */
bl __libc_init_array
800169e: f003 fa59 bl 8004b54 <__libc_init_array>
/* Call the application's entry point.*/
bl main
80016a2: f7fe ff23 bl 80004ec <main>
bx lr
80016a6: 4770 bx lr
ldr sp, =_estack /* set stack pointer */
80016a8: 20030000 .word 0x20030000
ldr r3, =_sidata
80016ac: 08004bec .word 0x08004bec
ldr r0, =_sdata
80016b0: 20000000 .word 0x20000000
ldr r3, =_edata
80016b4: 2000000c .word 0x2000000c
ldr r2, =_sbss
80016b8: 2000000c .word 0x2000000c
ldr r3, = _ebss
80016bc: 20000328 .word 0x20000328
080016c0 <ADC_IRQHandler>:
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
80016c0: e7fe b.n 80016c0 <ADC_IRQHandler>
...
080016c4 <HAL_Init>:
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
80016c4: b580 push {r7, lr}
80016c6: af00 add r7, sp, #0
/* Configure Flash prefetch, Instruction cache, Data cache */
#if (INSTRUCTION_CACHE_ENABLE != 0U)
__HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
80016c8: 4b0e ldr r3, [pc, #56] ; (8001704 <HAL_Init+0x40>)
80016ca: 681b ldr r3, [r3, #0]
80016cc: 4a0d ldr r2, [pc, #52] ; (8001704 <HAL_Init+0x40>)
80016ce: f443 7300 orr.w r3, r3, #512 ; 0x200
80016d2: 6013 str r3, [r2, #0]
#endif /* INSTRUCTION_CACHE_ENABLE */
#if (DATA_CACHE_ENABLE != 0U)
__HAL_FLASH_DATA_CACHE_ENABLE();
80016d4: 4b0b ldr r3, [pc, #44] ; (8001704 <HAL_Init+0x40>)
80016d6: 681b ldr r3, [r3, #0]
80016d8: 4a0a ldr r2, [pc, #40] ; (8001704 <HAL_Init+0x40>)
80016da: f443 6380 orr.w r3, r3, #1024 ; 0x400
80016de: 6013 str r3, [r2, #0]
#endif /* DATA_CACHE_ENABLE */
#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
80016e0: 4b08 ldr r3, [pc, #32] ; (8001704 <HAL_Init+0x40>)
80016e2: 681b ldr r3, [r3, #0]
80016e4: 4a07 ldr r2, [pc, #28] ; (8001704 <HAL_Init+0x40>)
80016e6: f443 7380 orr.w r3, r3, #256 ; 0x100
80016ea: 6013 str r3, [r2, #0]
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
80016ec: 2003 movs r0, #3
80016ee: f000 f8d8 bl 80018a2 <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
80016f2: 2000 movs r0, #0
80016f4: f7ff fef4 bl 80014e0 <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
80016f8: f7ff fb50 bl 8000d9c <HAL_MspInit>
/* Return function status */
return HAL_OK;
80016fc: 2300 movs r3, #0
}
80016fe: 4618 mov r0, r3
8001700: bd80 pop {r7, pc}
8001702: bf00 nop
8001704: 40023c00 .word 0x40023c00
08001708 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8001708: b480 push {r7}
800170a: af00 add r7, sp, #0
uwTick += uwTickFreq;
800170c: 4b06 ldr r3, [pc, #24] ; (8001728 <HAL_IncTick+0x20>)
800170e: 781b ldrb r3, [r3, #0]
8001710: 461a mov r2, r3
8001712: 4b06 ldr r3, [pc, #24] ; (800172c <HAL_IncTick+0x24>)
8001714: 681b ldr r3, [r3, #0]
8001716: 4413 add r3, r2
8001718: 4a04 ldr r2, [pc, #16] ; (800172c <HAL_IncTick+0x24>)
800171a: 6013 str r3, [r2, #0]
}
800171c: bf00 nop
800171e: 46bd mov sp, r7
8001720: f85d 7b04 ldr.w r7, [sp], #4
8001724: 4770 bx lr
8001726: bf00 nop
8001728: 20000008 .word 0x20000008
800172c: 20000324 .word 0x20000324
08001730 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8001730: b480 push {r7}
8001732: af00 add r7, sp, #0
return uwTick;
8001734: 4b03 ldr r3, [pc, #12] ; (8001744 <HAL_GetTick+0x14>)
8001736: 681b ldr r3, [r3, #0]
}
8001738: 4618 mov r0, r3
800173a: 46bd mov sp, r7
800173c: f85d 7b04 ldr.w r7, [sp], #4
8001740: 4770 bx lr
8001742: bf00 nop
8001744: 20000324 .word 0x20000324
08001748 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8001748: b480 push {r7}
800174a: b085 sub sp, #20
800174c: af00 add r7, sp, #0
800174e: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8001750: 687b ldr r3, [r7, #4]
8001752: f003 0307 and.w r3, r3, #7
8001756: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
8001758: 4b0c ldr r3, [pc, #48] ; (800178c <__NVIC_SetPriorityGrouping+0x44>)
800175a: 68db ldr r3, [r3, #12]
800175c: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
800175e: 68ba ldr r2, [r7, #8]
8001760: f64f 03ff movw r3, #63743 ; 0xf8ff
8001764: 4013 ands r3, r2
8001766: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
8001768: 68fb ldr r3, [r7, #12]
800176a: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
800176c: 68bb ldr r3, [r7, #8]
800176e: 4313 orrs r3, r2
reg_value = (reg_value |
8001770: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000
8001774: f443 3300 orr.w r3, r3, #131072 ; 0x20000
8001778: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
800177a: 4a04 ldr r2, [pc, #16] ; (800178c <__NVIC_SetPriorityGrouping+0x44>)
800177c: 68bb ldr r3, [r7, #8]
800177e: 60d3 str r3, [r2, #12]
}
8001780: bf00 nop
8001782: 3714 adds r7, #20
8001784: 46bd mov sp, r7
8001786: f85d 7b04 ldr.w r7, [sp], #4
800178a: 4770 bx lr
800178c: e000ed00 .word 0xe000ed00
08001790 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
8001790: b480 push {r7}
8001792: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
8001794: 4b04 ldr r3, [pc, #16] ; (80017a8 <__NVIC_GetPriorityGrouping+0x18>)
8001796: 68db ldr r3, [r3, #12]
8001798: 0a1b lsrs r3, r3, #8
800179a: f003 0307 and.w r3, r3, #7
}
800179e: 4618 mov r0, r3
80017a0: 46bd mov sp, r7
80017a2: f85d 7b04 ldr.w r7, [sp], #4
80017a6: 4770 bx lr
80017a8: e000ed00 .word 0xe000ed00
080017ac <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
80017ac: b480 push {r7}
80017ae: b083 sub sp, #12
80017b0: af00 add r7, sp, #0
80017b2: 4603 mov r3, r0
80017b4: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
80017b6: f997 3007 ldrsb.w r3, [r7, #7]
80017ba: 2b00 cmp r3, #0
80017bc: db0b blt.n 80017d6 <__NVIC_EnableIRQ+0x2a>
{
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
80017be: 79fb ldrb r3, [r7, #7]
80017c0: f003 021f and.w r2, r3, #31
80017c4: 4907 ldr r1, [pc, #28] ; (80017e4 <__NVIC_EnableIRQ+0x38>)
80017c6: f997 3007 ldrsb.w r3, [r7, #7]
80017ca: 095b lsrs r3, r3, #5
80017cc: 2001 movs r0, #1
80017ce: fa00 f202 lsl.w r2, r0, r2
80017d2: f841 2023 str.w r2, [r1, r3, lsl #2]
}
}
80017d6: bf00 nop
80017d8: 370c adds r7, #12
80017da: 46bd mov sp, r7
80017dc: f85d 7b04 ldr.w r7, [sp], #4
80017e0: 4770 bx lr
80017e2: bf00 nop
80017e4: e000e100 .word 0xe000e100
080017e8 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
80017e8: b480 push {r7}
80017ea: b083 sub sp, #12
80017ec: af00 add r7, sp, #0
80017ee: 4603 mov r3, r0
80017f0: 6039 str r1, [r7, #0]
80017f2: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
80017f4: f997 3007 ldrsb.w r3, [r7, #7]
80017f8: 2b00 cmp r3, #0
80017fa: db0a blt.n 8001812 <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
80017fc: 683b ldr r3, [r7, #0]
80017fe: b2da uxtb r2, r3
8001800: 490c ldr r1, [pc, #48] ; (8001834 <__NVIC_SetPriority+0x4c>)
8001802: f997 3007 ldrsb.w r3, [r7, #7]
8001806: 0112 lsls r2, r2, #4
8001808: b2d2 uxtb r2, r2
800180a: 440b add r3, r1
800180c: f883 2300 strb.w r2, [r3, #768] ; 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
8001810: e00a b.n 8001828 <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8001812: 683b ldr r3, [r7, #0]
8001814: b2da uxtb r2, r3
8001816: 4908 ldr r1, [pc, #32] ; (8001838 <__NVIC_SetPriority+0x50>)
8001818: 79fb ldrb r3, [r7, #7]
800181a: f003 030f and.w r3, r3, #15
800181e: 3b04 subs r3, #4
8001820: 0112 lsls r2, r2, #4
8001822: b2d2 uxtb r2, r2
8001824: 440b add r3, r1
8001826: 761a strb r2, [r3, #24]
}
8001828: bf00 nop
800182a: 370c adds r7, #12
800182c: 46bd mov sp, r7
800182e: f85d 7b04 ldr.w r7, [sp], #4
8001832: 4770 bx lr
8001834: e000e100 .word 0xe000e100
8001838: e000ed00 .word 0xe000ed00
0800183c <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
800183c: b480 push {r7}
800183e: b089 sub sp, #36 ; 0x24
8001840: af00 add r7, sp, #0
8001842: 60f8 str r0, [r7, #12]
8001844: 60b9 str r1, [r7, #8]
8001846: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8001848: 68fb ldr r3, [r7, #12]
800184a: f003 0307 and.w r3, r3, #7
800184e: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
8001850: 69fb ldr r3, [r7, #28]
8001852: f1c3 0307 rsb r3, r3, #7
8001856: 2b04 cmp r3, #4
8001858: bf28 it cs
800185a: 2304 movcs r3, #4
800185c: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
800185e: 69fb ldr r3, [r7, #28]
8001860: 3304 adds r3, #4
8001862: 2b06 cmp r3, #6
8001864: d902 bls.n 800186c <NVIC_EncodePriority+0x30>
8001866: 69fb ldr r3, [r7, #28]
8001868: 3b03 subs r3, #3
800186a: e000 b.n 800186e <NVIC_EncodePriority+0x32>
800186c: 2300 movs r3, #0
800186e: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8001870: f04f 32ff mov.w r2, #4294967295
8001874: 69bb ldr r3, [r7, #24]
8001876: fa02 f303 lsl.w r3, r2, r3
800187a: 43da mvns r2, r3
800187c: 68bb ldr r3, [r7, #8]
800187e: 401a ands r2, r3
8001880: 697b ldr r3, [r7, #20]
8001882: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
8001884: f04f 31ff mov.w r1, #4294967295
8001888: 697b ldr r3, [r7, #20]
800188a: fa01 f303 lsl.w r3, r1, r3
800188e: 43d9 mvns r1, r3
8001890: 687b ldr r3, [r7, #4]
8001892: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8001894: 4313 orrs r3, r2
);
}
8001896: 4618 mov r0, r3
8001898: 3724 adds r7, #36 ; 0x24
800189a: 46bd mov sp, r7
800189c: f85d 7b04 ldr.w r7, [sp], #4
80018a0: 4770 bx lr
080018a2 <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
80018a2: b580 push {r7, lr}
80018a4: b082 sub sp, #8
80018a6: af00 add r7, sp, #0
80018a8: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
80018aa: 6878 ldr r0, [r7, #4]
80018ac: f7ff ff4c bl 8001748 <__NVIC_SetPriorityGrouping>
}
80018b0: bf00 nop
80018b2: 3708 adds r7, #8
80018b4: 46bd mov sp, r7
80018b6: bd80 pop {r7, pc}
080018b8 <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
80018b8: b580 push {r7, lr}
80018ba: b086 sub sp, #24
80018bc: af00 add r7, sp, #0
80018be: 4603 mov r3, r0
80018c0: 60b9 str r1, [r7, #8]
80018c2: 607a str r2, [r7, #4]
80018c4: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00U;
80018c6: 2300 movs r3, #0
80018c8: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
80018ca: f7ff ff61 bl 8001790 <__NVIC_GetPriorityGrouping>
80018ce: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
80018d0: 687a ldr r2, [r7, #4]
80018d2: 68b9 ldr r1, [r7, #8]
80018d4: 6978 ldr r0, [r7, #20]
80018d6: f7ff ffb1 bl 800183c <NVIC_EncodePriority>
80018da: 4602 mov r2, r0
80018dc: f997 300f ldrsb.w r3, [r7, #15]
80018e0: 4611 mov r1, r2
80018e2: 4618 mov r0, r3
80018e4: f7ff ff80 bl 80017e8 <__NVIC_SetPriority>
}
80018e8: bf00 nop
80018ea: 3718 adds r7, #24
80018ec: 46bd mov sp, r7
80018ee: bd80 pop {r7, pc}
080018f0 <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
80018f0: b580 push {r7, lr}
80018f2: b082 sub sp, #8
80018f4: af00 add r7, sp, #0
80018f6: 4603 mov r3, r0
80018f8: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
80018fa: f997 3007 ldrsb.w r3, [r7, #7]
80018fe: 4618 mov r0, r3
8001900: f7ff ff54 bl 80017ac <__NVIC_EnableIRQ>
}
8001904: bf00 nop
8001906: 3708 adds r7, #8
8001908: 46bd mov sp, r7
800190a: bd80 pop {r7, pc}
0800190c <HAL_CRC_Init>:
* parameters in the CRC_InitTypeDef and create the associated handle.
* @param hcrc CRC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
{
800190c: b580 push {r7, lr}
800190e: b082 sub sp, #8
8001910: af00 add r7, sp, #0
8001912: 6078 str r0, [r7, #4]
/* Check the CRC handle allocation */
if (hcrc == NULL)
8001914: 687b ldr r3, [r7, #4]
8001916: 2b00 cmp r3, #0
8001918: d101 bne.n 800191e <HAL_CRC_Init+0x12>
{
return HAL_ERROR;
800191a: 2301 movs r3, #1
800191c: e00e b.n 800193c <HAL_CRC_Init+0x30>
}
/* Check the parameters */
assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
if (hcrc->State == HAL_CRC_STATE_RESET)
800191e: 687b ldr r3, [r7, #4]
8001920: 795b ldrb r3, [r3, #5]
8001922: b2db uxtb r3, r3
8001924: 2b00 cmp r3, #0
8001926: d105 bne.n 8001934 <HAL_CRC_Init+0x28>
{
/* Allocate lock resource and initialize it */
hcrc->Lock = HAL_UNLOCKED;
8001928: 687b ldr r3, [r7, #4]
800192a: 2200 movs r2, #0
800192c: 711a strb r2, [r3, #4]
/* Init the low level hardware */
HAL_CRC_MspInit(hcrc);
800192e: 6878 ldr r0, [r7, #4]
8001930: f7ff fa60 bl 8000df4 <HAL_CRC_MspInit>
}
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_READY;
8001934: 687b ldr r3, [r7, #4]
8001936: 2201 movs r2, #1
8001938: 715a strb r2, [r3, #5]
/* Return function status */
return HAL_OK;
800193a: 2300 movs r3, #0
}
800193c: 4618 mov r0, r3
800193e: 3708 adds r7, #8
8001940: 46bd mov sp, r7
8001942: bd80 pop {r7, pc}
08001944 <HAL_DMA2D_Init>:
* @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
{
8001944: b580 push {r7, lr}
8001946: b082 sub sp, #8
8001948: af00 add r7, sp, #0
800194a: 6078 str r0, [r7, #4]
/* Check the DMA2D peripheral state */
if(hdma2d == NULL)
800194c: 687b ldr r3, [r7, #4]
800194e: 2b00 cmp r3, #0
8001950: d101 bne.n 8001956 <HAL_DMA2D_Init+0x12>
{
return HAL_ERROR;
8001952: 2301 movs r3, #1
8001954: e03b b.n 80019ce <HAL_DMA2D_Init+0x8a>
/* Init the low level hardware */
hdma2d->MspInitCallback(hdma2d);
}
#else
if(hdma2d->State == HAL_DMA2D_STATE_RESET)
8001956: 687b ldr r3, [r7, #4]
8001958: f893 3039 ldrb.w r3, [r3, #57] ; 0x39
800195c: b2db uxtb r3, r3
800195e: 2b00 cmp r3, #0
8001960: d106 bne.n 8001970 <HAL_DMA2D_Init+0x2c>
{
/* Allocate lock resource and initialize it */
hdma2d->Lock = HAL_UNLOCKED;
8001962: 687b ldr r3, [r7, #4]
8001964: 2200 movs r2, #0
8001966: f883 2038 strb.w r2, [r3, #56] ; 0x38
/* Init the low level hardware */
HAL_DMA2D_MspInit(hdma2d);
800196a: 6878 ldr r0, [r7, #4]
800196c: f7ff fa64 bl 8000e38 <HAL_DMA2D_MspInit>
}
#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
/* Change DMA2D peripheral state */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
8001970: 687b ldr r3, [r7, #4]
8001972: 2202 movs r2, #2
8001974: f883 2039 strb.w r2, [r3, #57] ; 0x39
/* DMA2D CR register configuration -------------------------------------------*/
MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode);
8001978: 687b ldr r3, [r7, #4]
800197a: 681b ldr r3, [r3, #0]
800197c: 681b ldr r3, [r3, #0]
800197e: f423 3140 bic.w r1, r3, #196608 ; 0x30000
8001982: 687b ldr r3, [r7, #4]
8001984: 685a ldr r2, [r3, #4]
8001986: 687b ldr r3, [r7, #4]
8001988: 681b ldr r3, [r3, #0]
800198a: 430a orrs r2, r1
800198c: 601a str r2, [r3, #0]
/* DMA2D OPFCCR register configuration ---------------------------------------*/
MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode);
800198e: 687b ldr r3, [r7, #4]
8001990: 681b ldr r3, [r3, #0]
8001992: 6b5b ldr r3, [r3, #52] ; 0x34
8001994: f023 0107 bic.w r1, r3, #7
8001998: 687b ldr r3, [r7, #4]
800199a: 689a ldr r2, [r3, #8]
800199c: 687b ldr r3, [r7, #4]
800199e: 681b ldr r3, [r3, #0]
80019a0: 430a orrs r2, r1
80019a2: 635a str r2, [r3, #52] ; 0x34
/* DMA2D OOR register configuration ------------------------------------------*/
MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset);
80019a4: 687b ldr r3, [r7, #4]
80019a6: 681b ldr r3, [r3, #0]
80019a8: 6c1b ldr r3, [r3, #64] ; 0x40
80019aa: f423 537f bic.w r3, r3, #16320 ; 0x3fc0
80019ae: f023 033f bic.w r3, r3, #63 ; 0x3f
80019b2: 687a ldr r2, [r7, #4]
80019b4: 68d1 ldr r1, [r2, #12]
80019b6: 687a ldr r2, [r7, #4]
80019b8: 6812 ldr r2, [r2, #0]
80019ba: 430b orrs r3, r1
80019bc: 6413 str r3, [r2, #64] ; 0x40
/* Update error code */
hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
80019be: 687b ldr r3, [r7, #4]
80019c0: 2200 movs r2, #0
80019c2: 63da str r2, [r3, #60] ; 0x3c
/* Initialize the DMA2D state*/
hdma2d->State = HAL_DMA2D_STATE_READY;
80019c4: 687b ldr r3, [r7, #4]
80019c6: 2201 movs r2, #1
80019c8: f883 2039 strb.w r2, [r3, #57] ; 0x39
return HAL_OK;
80019cc: 2300 movs r3, #0
}
80019ce: 4618 mov r0, r3
80019d0: 3708 adds r7, #8
80019d2: 46bd mov sp, r7
80019d4: bd80 pop {r7, pc}
080019d6 <HAL_DMA2D_IRQHandler>:
* @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @retval HAL status
*/
void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
{
80019d6: b580 push {r7, lr}
80019d8: b084 sub sp, #16
80019da: af00 add r7, sp, #0
80019dc: 6078 str r0, [r7, #4]
uint32_t isrflags = READ_REG(hdma2d->Instance->ISR);
80019de: 687b ldr r3, [r7, #4]
80019e0: 681b ldr r3, [r3, #0]
80019e2: 685b ldr r3, [r3, #4]
80019e4: 60fb str r3, [r7, #12]
uint32_t crflags = READ_REG(hdma2d->Instance->CR);
80019e6: 687b ldr r3, [r7, #4]
80019e8: 681b ldr r3, [r3, #0]
80019ea: 681b ldr r3, [r3, #0]
80019ec: 60bb str r3, [r7, #8]
/* Transfer Error Interrupt management ***************************************/
if ((isrflags & DMA2D_FLAG_TE) != 0U)
80019ee: 68fb ldr r3, [r7, #12]
80019f0: f003 0301 and.w r3, r3, #1
80019f4: 2b00 cmp r3, #0
80019f6: d026 beq.n 8001a46 <HAL_DMA2D_IRQHandler+0x70>
{
if ((crflags & DMA2D_IT_TE) != 0U)
80019f8: 68bb ldr r3, [r7, #8]
80019fa: f403 7380 and.w r3, r3, #256 ; 0x100
80019fe: 2b00 cmp r3, #0
8001a00: d021 beq.n 8001a46 <HAL_DMA2D_IRQHandler+0x70>
{
/* Disable the transfer Error interrupt */
__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE);
8001a02: 687b ldr r3, [r7, #4]
8001a04: 681b ldr r3, [r3, #0]
8001a06: 681a ldr r2, [r3, #0]
8001a08: 687b ldr r3, [r7, #4]
8001a0a: 681b ldr r3, [r3, #0]
8001a0c: f422 7280 bic.w r2, r2, #256 ; 0x100
8001a10: 601a str r2, [r3, #0]
/* Update error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
8001a12: 687b ldr r3, [r7, #4]
8001a14: 6bdb ldr r3, [r3, #60] ; 0x3c
8001a16: f043 0201 orr.w r2, r3, #1
8001a1a: 687b ldr r3, [r7, #4]
8001a1c: 63da str r2, [r3, #60] ; 0x3c
/* Clear the transfer error flag */
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE);
8001a1e: 687b ldr r3, [r7, #4]
8001a20: 681b ldr r3, [r3, #0]
8001a22: 2201 movs r2, #1
8001a24: 609a str r2, [r3, #8]
/* Change DMA2D state */
hdma2d->State = HAL_DMA2D_STATE_ERROR;
8001a26: 687b ldr r3, [r7, #4]
8001a28: 2204 movs r2, #4
8001a2a: f883 2039 strb.w r2, [r3, #57] ; 0x39
/* Process Unlocked */
__HAL_UNLOCK(hdma2d);
8001a2e: 687b ldr r3, [r7, #4]
8001a30: 2200 movs r2, #0
8001a32: f883 2038 strb.w r2, [r3, #56] ; 0x38
if(hdma2d->XferErrorCallback != NULL)
8001a36: 687b ldr r3, [r7, #4]
8001a38: 695b ldr r3, [r3, #20]
8001a3a: 2b00 cmp r3, #0
8001a3c: d003 beq.n 8001a46 <HAL_DMA2D_IRQHandler+0x70>
{
/* Transfer error Callback */
hdma2d->XferErrorCallback(hdma2d);
8001a3e: 687b ldr r3, [r7, #4]
8001a40: 695b ldr r3, [r3, #20]
8001a42: 6878 ldr r0, [r7, #4]
8001a44: 4798 blx r3
}
}
}
/* Configuration Error Interrupt management **********************************/
if ((isrflags & DMA2D_FLAG_CE) != 0U)
8001a46: 68fb ldr r3, [r7, #12]
8001a48: f003 0320 and.w r3, r3, #32
8001a4c: 2b00 cmp r3, #0
8001a4e: d026 beq.n 8001a9e <HAL_DMA2D_IRQHandler+0xc8>
{
if ((crflags & DMA2D_IT_CE) != 0U)
8001a50: 68bb ldr r3, [r7, #8]
8001a52: f403 5300 and.w r3, r3, #8192 ; 0x2000
8001a56: 2b00 cmp r3, #0
8001a58: d021 beq.n 8001a9e <HAL_DMA2D_IRQHandler+0xc8>
{
/* Disable the Configuration Error interrupt */
__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE);
8001a5a: 687b ldr r3, [r7, #4]
8001a5c: 681b ldr r3, [r3, #0]
8001a5e: 681a ldr r2, [r3, #0]
8001a60: 687b ldr r3, [r7, #4]
8001a62: 681b ldr r3, [r3, #0]
8001a64: f422 5200 bic.w r2, r2, #8192 ; 0x2000
8001a68: 601a str r2, [r3, #0]
/* Clear the Configuration error flag */
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE);
8001a6a: 687b ldr r3, [r7, #4]
8001a6c: 681b ldr r3, [r3, #0]
8001a6e: 2220 movs r2, #32
8001a70: 609a str r2, [r3, #8]
/* Update error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
8001a72: 687b ldr r3, [r7, #4]
8001a74: 6bdb ldr r3, [r3, #60] ; 0x3c
8001a76: f043 0202 orr.w r2, r3, #2
8001a7a: 687b ldr r3, [r7, #4]
8001a7c: 63da str r2, [r3, #60] ; 0x3c
/* Change DMA2D state */
hdma2d->State = HAL_DMA2D_STATE_ERROR;
8001a7e: 687b ldr r3, [r7, #4]
8001a80: 2204 movs r2, #4
8001a82: f883 2039 strb.w r2, [r3, #57] ; 0x39
/* Process Unlocked */
__HAL_UNLOCK(hdma2d);
8001a86: 687b ldr r3, [r7, #4]
8001a88: 2200 movs r2, #0
8001a8a: f883 2038 strb.w r2, [r3, #56] ; 0x38
if(hdma2d->XferErrorCallback != NULL)
8001a8e: 687b ldr r3, [r7, #4]
8001a90: 695b ldr r3, [r3, #20]
8001a92: 2b00 cmp r3, #0
8001a94: d003 beq.n 8001a9e <HAL_DMA2D_IRQHandler+0xc8>
{
/* Transfer error Callback */
hdma2d->XferErrorCallback(hdma2d);
8001a96: 687b ldr r3, [r7, #4]
8001a98: 695b ldr r3, [r3, #20]
8001a9a: 6878 ldr r0, [r7, #4]
8001a9c: 4798 blx r3
}
}
}
/* CLUT access Error Interrupt management ***********************************/
if ((isrflags & DMA2D_FLAG_CAE) != 0U)
8001a9e: 68fb ldr r3, [r7, #12]
8001aa0: f003 0308 and.w r3, r3, #8
8001aa4: 2b00 cmp r3, #0
8001aa6: d026 beq.n 8001af6 <HAL_DMA2D_IRQHandler+0x120>
{
if ((crflags & DMA2D_IT_CAE) != 0U)
8001aa8: 68bb ldr r3, [r7, #8]
8001aaa: f403 6300 and.w r3, r3, #2048 ; 0x800
8001aae: 2b00 cmp r3, #0
8001ab0: d021 beq.n 8001af6 <HAL_DMA2D_IRQHandler+0x120>
{
/* Disable the CLUT access error interrupt */
__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE);
8001ab2: 687b ldr r3, [r7, #4]
8001ab4: 681b ldr r3, [r3, #0]
8001ab6: 681a ldr r2, [r3, #0]
8001ab8: 687b ldr r3, [r7, #4]
8001aba: 681b ldr r3, [r3, #0]
8001abc: f422 6200 bic.w r2, r2, #2048 ; 0x800
8001ac0: 601a str r2, [r3, #0]
/* Clear the CLUT access error flag */
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE);
8001ac2: 687b ldr r3, [r7, #4]
8001ac4: 681b ldr r3, [r3, #0]
8001ac6: 2208 movs r2, #8
8001ac8: 609a str r2, [r3, #8]
/* Update error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
8001aca: 687b ldr r3, [r7, #4]
8001acc: 6bdb ldr r3, [r3, #60] ; 0x3c
8001ace: f043 0204 orr.w r2, r3, #4
8001ad2: 687b ldr r3, [r7, #4]
8001ad4: 63da str r2, [r3, #60] ; 0x3c
/* Change DMA2D state */
hdma2d->State = HAL_DMA2D_STATE_ERROR;
8001ad6: 687b ldr r3, [r7, #4]
8001ad8: 2204 movs r2, #4
8001ada: f883 2039 strb.w r2, [r3, #57] ; 0x39
/* Process Unlocked */
__HAL_UNLOCK(hdma2d);
8001ade: 687b ldr r3, [r7, #4]
8001ae0: 2200 movs r2, #0
8001ae2: f883 2038 strb.w r2, [r3, #56] ; 0x38
if(hdma2d->XferErrorCallback != NULL)
8001ae6: 687b ldr r3, [r7, #4]
8001ae8: 695b ldr r3, [r3, #20]
8001aea: 2b00 cmp r3, #0
8001aec: d003 beq.n 8001af6 <HAL_DMA2D_IRQHandler+0x120>
{
/* Transfer error Callback */
hdma2d->XferErrorCallback(hdma2d);
8001aee: 687b ldr r3, [r7, #4]
8001af0: 695b ldr r3, [r3, #20]
8001af2: 6878 ldr r0, [r7, #4]
8001af4: 4798 blx r3
}
}
}
/* Transfer watermark Interrupt management **********************************/
if ((isrflags & DMA2D_FLAG_TW) != 0U)
8001af6: 68fb ldr r3, [r7, #12]
8001af8: f003 0304 and.w r3, r3, #4
8001afc: 2b00 cmp r3, #0
8001afe: d013 beq.n 8001b28 <HAL_DMA2D_IRQHandler+0x152>
{
if ((crflags & DMA2D_IT_TW) != 0U)
8001b00: 68bb ldr r3, [r7, #8]
8001b02: f403 6380 and.w r3, r3, #1024 ; 0x400
8001b06: 2b00 cmp r3, #0
8001b08: d00e beq.n 8001b28 <HAL_DMA2D_IRQHandler+0x152>
{
/* Disable the transfer watermark interrupt */
__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW);
8001b0a: 687b ldr r3, [r7, #4]
8001b0c: 681b ldr r3, [r3, #0]
8001b0e: 681a ldr r2, [r3, #0]
8001b10: 687b ldr r3, [r7, #4]
8001b12: 681b ldr r3, [r3, #0]
8001b14: f422 6280 bic.w r2, r2, #1024 ; 0x400
8001b18: 601a str r2, [r3, #0]
/* Clear the transfer watermark flag */
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW);
8001b1a: 687b ldr r3, [r7, #4]
8001b1c: 681b ldr r3, [r3, #0]
8001b1e: 2204 movs r2, #4
8001b20: 609a str r2, [r3, #8]
/* Transfer watermark Callback */
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
hdma2d->LineEventCallback(hdma2d);
#else
HAL_DMA2D_LineEventCallback(hdma2d);
8001b22: 6878 ldr r0, [r7, #4]
8001b24: f000 f853 bl 8001bce <HAL_DMA2D_LineEventCallback>
#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
}
}
/* Transfer Complete Interrupt management ************************************/
if ((isrflags & DMA2D_FLAG_TC) != 0U)
8001b28: 68fb ldr r3, [r7, #12]
8001b2a: f003 0302 and.w r3, r3, #2
8001b2e: 2b00 cmp r3, #0
8001b30: d024 beq.n 8001b7c <HAL_DMA2D_IRQHandler+0x1a6>
{
if ((crflags & DMA2D_IT_TC) != 0U)
8001b32: 68bb ldr r3, [r7, #8]
8001b34: f403 7300 and.w r3, r3, #512 ; 0x200
8001b38: 2b00 cmp r3, #0
8001b3a: d01f beq.n 8001b7c <HAL_DMA2D_IRQHandler+0x1a6>
{
/* Disable the transfer complete interrupt */
__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC);
8001b3c: 687b ldr r3, [r7, #4]
8001b3e: 681b ldr r3, [r3, #0]
8001b40: 681a ldr r2, [r3, #0]
8001b42: 687b ldr r3, [r7, #4]
8001b44: 681b ldr r3, [r3, #0]
8001b46: f422 7200 bic.w r2, r2, #512 ; 0x200
8001b4a: 601a str r2, [r3, #0]
/* Clear the transfer complete flag */
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC);
8001b4c: 687b ldr r3, [r7, #4]
8001b4e: 681b ldr r3, [r3, #0]
8001b50: 2202 movs r2, #2
8001b52: 609a str r2, [r3, #8]
/* Update error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
8001b54: 687b ldr r3, [r7, #4]
8001b56: 6bda ldr r2, [r3, #60] ; 0x3c
8001b58: 687b ldr r3, [r7, #4]
8001b5a: 63da str r2, [r3, #60] ; 0x3c
/* Change DMA2D state */
hdma2d->State = HAL_DMA2D_STATE_READY;
8001b5c: 687b ldr r3, [r7, #4]
8001b5e: 2201 movs r2, #1
8001b60: f883 2039 strb.w r2, [r3, #57] ; 0x39
/* Process Unlocked */
__HAL_UNLOCK(hdma2d);
8001b64: 687b ldr r3, [r7, #4]
8001b66: 2200 movs r2, #0
8001b68: f883 2038 strb.w r2, [r3, #56] ; 0x38
if(hdma2d->XferCpltCallback != NULL)
8001b6c: 687b ldr r3, [r7, #4]
8001b6e: 691b ldr r3, [r3, #16]
8001b70: 2b00 cmp r3, #0
8001b72: d003 beq.n 8001b7c <HAL_DMA2D_IRQHandler+0x1a6>
{
/* Transfer complete Callback */
hdma2d->XferCpltCallback(hdma2d);
8001b74: 687b ldr r3, [r7, #4]
8001b76: 691b ldr r3, [r3, #16]
8001b78: 6878 ldr r0, [r7, #4]
8001b7a: 4798 blx r3
}
}
}
/* CLUT Transfer Complete Interrupt management ******************************/
if ((isrflags & DMA2D_FLAG_CTC) != 0U)
8001b7c: 68fb ldr r3, [r7, #12]
8001b7e: f003 0310 and.w r3, r3, #16
8001b82: 2b00 cmp r3, #0
8001b84: d01f beq.n 8001bc6 <HAL_DMA2D_IRQHandler+0x1f0>
{
if ((crflags & DMA2D_IT_CTC) != 0U)
8001b86: 68bb ldr r3, [r7, #8]
8001b88: f403 5380 and.w r3, r3, #4096 ; 0x1000
8001b8c: 2b00 cmp r3, #0
8001b8e: d01a beq.n 8001bc6 <HAL_DMA2D_IRQHandler+0x1f0>
{
/* Disable the CLUT transfer complete interrupt */
__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC);
8001b90: 687b ldr r3, [r7, #4]
8001b92: 681b ldr r3, [r3, #0]
8001b94: 681a ldr r2, [r3, #0]
8001b96: 687b ldr r3, [r7, #4]
8001b98: 681b ldr r3, [r3, #0]
8001b9a: f422 5280 bic.w r2, r2, #4096 ; 0x1000
8001b9e: 601a str r2, [r3, #0]
/* Clear the CLUT transfer complete flag */
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC);
8001ba0: 687b ldr r3, [r7, #4]
8001ba2: 681b ldr r3, [r3, #0]
8001ba4: 2210 movs r2, #16
8001ba6: 609a str r2, [r3, #8]
/* Update error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
8001ba8: 687b ldr r3, [r7, #4]
8001baa: 6bda ldr r2, [r3, #60] ; 0x3c
8001bac: 687b ldr r3, [r7, #4]
8001bae: 63da str r2, [r3, #60] ; 0x3c
/* Change DMA2D state */
hdma2d->State = HAL_DMA2D_STATE_READY;
8001bb0: 687b ldr r3, [r7, #4]
8001bb2: 2201 movs r2, #1
8001bb4: f883 2039 strb.w r2, [r3, #57] ; 0x39
/* Process Unlocked */
__HAL_UNLOCK(hdma2d);
8001bb8: 687b ldr r3, [r7, #4]
8001bba: 2200 movs r2, #0
8001bbc: f883 2038 strb.w r2, [r3, #56] ; 0x38
/* CLUT Transfer complete Callback */
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
hdma2d->CLUTLoadingCpltCallback(hdma2d);
#else
HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d);
8001bc0: 6878 ldr r0, [r7, #4]
8001bc2: f000 f80e bl 8001be2 <HAL_DMA2D_CLUTLoadingCpltCallback>
#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
}
}
}
8001bc6: bf00 nop
8001bc8: 3710 adds r7, #16
8001bca: 46bd mov sp, r7
8001bcc: bd80 pop {r7, pc}
08001bce <HAL_DMA2D_LineEventCallback>:
* @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @retval None
*/
__weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d)
{
8001bce: b480 push {r7}
8001bd0: b083 sub sp, #12
8001bd2: af00 add r7, sp, #0
8001bd4: 6078 str r0, [r7, #4]
UNUSED(hdma2d);
/* NOTE : This function should not be modified; when the callback is needed,
the HAL_DMA2D_LineEventCallback can be implemented in the user file.
*/
}
8001bd6: bf00 nop
8001bd8: 370c adds r7, #12
8001bda: 46bd mov sp, r7
8001bdc: f85d 7b04 ldr.w r7, [sp], #4
8001be0: 4770 bx lr
08001be2 <HAL_DMA2D_CLUTLoadingCpltCallback>:
* @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @retval None
*/
__weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d)
{
8001be2: b480 push {r7}
8001be4: b083 sub sp, #12
8001be6: af00 add r7, sp, #0
8001be8: 6078 str r0, [r7, #4]
UNUSED(hdma2d);
/* NOTE : This function should not be modified; when the callback is needed,
the HAL_DMA2D_CLUTLoadingCpltCallback can be implemented in the user file.
*/
}
8001bea: bf00 nop
8001bec: 370c adds r7, #12
8001bee: 46bd mov sp, r7
8001bf0: f85d 7b04 ldr.w r7, [sp], #4
8001bf4: 4770 bx lr
...
08001bf8 <HAL_DMA2D_ConfigLayer>:
* This parameter can be one of the following values:
* DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
{
8001bf8: b480 push {r7}
8001bfa: b087 sub sp, #28
8001bfc: af00 add r7, sp, #0
8001bfe: 6078 str r0, [r7, #4]
8001c00: 6039 str r1, [r7, #0]
uint32_t regMask, regValue;
/* Check the parameters */
assert_param(IS_DMA2D_LAYER(LayerIdx));
assert_param(IS_DMA2D_OFFSET(hdma2d->LayerCfg[LayerIdx].InputOffset));
if(hdma2d->Init.Mode != DMA2D_R2M)
8001c02: 687b ldr r3, [r7, #4]
8001c04: 685b ldr r3, [r3, #4]
8001c06: f5b3 3f40 cmp.w r3, #196608 ; 0x30000
assert_param(IS_DMA2D_ALPHA_MODE(hdma2d->LayerCfg[LayerIdx].AlphaMode));
}
}
/* Process locked */
__HAL_LOCK(hdma2d);
8001c0a: 687b ldr r3, [r7, #4]
8001c0c: f893 3038 ldrb.w r3, [r3, #56] ; 0x38
8001c10: 2b01 cmp r3, #1
8001c12: d101 bne.n 8001c18 <HAL_DMA2D_ConfigLayer+0x20>
8001c14: 2302 movs r3, #2
8001c16: e079 b.n 8001d0c <HAL_DMA2D_ConfigLayer+0x114>
8001c18: 687b ldr r3, [r7, #4]
8001c1a: 2201 movs r2, #1
8001c1c: f883 2038 strb.w r2, [r3, #56] ; 0x38
/* Change DMA2D peripheral state */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
8001c20: 687b ldr r3, [r7, #4]
8001c22: 2202 movs r2, #2
8001c24: f883 2039 strb.w r2, [r3, #57] ; 0x39
pLayerCfg = &hdma2d->LayerCfg[LayerIdx];
8001c28: 683b ldr r3, [r7, #0]
8001c2a: 011b lsls r3, r3, #4
8001c2c: 3318 adds r3, #24
8001c2e: 687a ldr r2, [r7, #4]
8001c30: 4413 add r3, r2
8001c32: 613b str r3, [r7, #16]
/* Prepare the value to be written to the BGPFCCR or FGPFCCR register */
regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos);
8001c34: 693b ldr r3, [r7, #16]
8001c36: 685a ldr r2, [r3, #4]
8001c38: 693b ldr r3, [r7, #16]
8001c3a: 689b ldr r3, [r3, #8]
8001c3c: 041b lsls r3, r3, #16
8001c3e: 4313 orrs r3, r2
8001c40: 617b str r3, [r7, #20]
regMask = DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA;
8001c42: 4b35 ldr r3, [pc, #212] ; (8001d18 <HAL_DMA2D_ConfigLayer+0x120>)
8001c44: 60fb str r3, [r7, #12]
if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
8001c46: 693b ldr r3, [r7, #16]
8001c48: 685b ldr r3, [r3, #4]
8001c4a: 2b0a cmp r3, #10
8001c4c: d003 beq.n 8001c56 <HAL_DMA2D_ConfigLayer+0x5e>
8001c4e: 693b ldr r3, [r7, #16]
8001c50: 685b ldr r3, [r3, #4]
8001c52: 2b09 cmp r3, #9
8001c54: d107 bne.n 8001c66 <HAL_DMA2D_ConfigLayer+0x6e>
{
regValue |= (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA);
8001c56: 693b ldr r3, [r7, #16]
8001c58: 68db ldr r3, [r3, #12]
8001c5a: f003 437f and.w r3, r3, #4278190080 ; 0xff000000
8001c5e: 697a ldr r2, [r7, #20]
8001c60: 4313 orrs r3, r2
8001c62: 617b str r3, [r7, #20]
8001c64: e005 b.n 8001c72 <HAL_DMA2D_ConfigLayer+0x7a>
}
else
{
regValue |= (pLayerCfg->InputAlpha << DMA2D_BGPFCCR_ALPHA_Pos);
8001c66: 693b ldr r3, [r7, #16]
8001c68: 68db ldr r3, [r3, #12]
8001c6a: 061b lsls r3, r3, #24
8001c6c: 697a ldr r2, [r7, #20]
8001c6e: 4313 orrs r3, r2
8001c70: 617b str r3, [r7, #20]
}
/* Configure the background DMA2D layer */
if(LayerIdx == DMA2D_BACKGROUND_LAYER)
8001c72: 683b ldr r3, [r7, #0]
8001c74: 2b00 cmp r3, #0
8001c76: d120 bne.n 8001cba <HAL_DMA2D_ConfigLayer+0xc2>
{
/* Write DMA2D BGPFCCR register */
MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue);
8001c78: 687b ldr r3, [r7, #4]
8001c7a: 681b ldr r3, [r3, #0]
8001c7c: 6a5a ldr r2, [r3, #36] ; 0x24
8001c7e: 68fb ldr r3, [r7, #12]
8001c80: 43db mvns r3, r3
8001c82: ea02 0103 and.w r1, r2, r3
8001c86: 687b ldr r3, [r7, #4]
8001c88: 681b ldr r3, [r3, #0]
8001c8a: 697a ldr r2, [r7, #20]
8001c8c: 430a orrs r2, r1
8001c8e: 625a str r2, [r3, #36] ; 0x24
/* DMA2D BGOR register configuration -------------------------------------*/
WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset);
8001c90: 687b ldr r3, [r7, #4]
8001c92: 681b ldr r3, [r3, #0]
8001c94: 693a ldr r2, [r7, #16]
8001c96: 6812 ldr r2, [r2, #0]
8001c98: 619a str r2, [r3, #24]
/* DMA2D BGCOLR register configuration -------------------------------------*/
if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
8001c9a: 693b ldr r3, [r7, #16]
8001c9c: 685b ldr r3, [r3, #4]
8001c9e: 2b0a cmp r3, #10
8001ca0: d003 beq.n 8001caa <HAL_DMA2D_ConfigLayer+0xb2>
8001ca2: 693b ldr r3, [r7, #16]
8001ca4: 685b ldr r3, [r3, #4]
8001ca6: 2b09 cmp r3, #9
8001ca8: d127 bne.n 8001cfa <HAL_DMA2D_ConfigLayer+0x102>
{
WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE|DMA2D_BGCOLR_GREEN|DMA2D_BGCOLR_RED));
8001caa: 693b ldr r3, [r7, #16]
8001cac: 68da ldr r2, [r3, #12]
8001cae: 687b ldr r3, [r7, #4]
8001cb0: 681b ldr r3, [r3, #0]
8001cb2: f022 427f bic.w r2, r2, #4278190080 ; 0xff000000
8001cb6: 629a str r2, [r3, #40] ; 0x28
8001cb8: e01f b.n 8001cfa <HAL_DMA2D_ConfigLayer+0x102>
else
{
/* Write DMA2D FGPFCCR register */
MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue);
8001cba: 687b ldr r3, [r7, #4]
8001cbc: 681b ldr r3, [r3, #0]
8001cbe: 69da ldr r2, [r3, #28]
8001cc0: 68fb ldr r3, [r7, #12]
8001cc2: 43db mvns r3, r3
8001cc4: ea02 0103 and.w r1, r2, r3
8001cc8: 687b ldr r3, [r7, #4]
8001cca: 681b ldr r3, [r3, #0]
8001ccc: 697a ldr r2, [r7, #20]
8001cce: 430a orrs r2, r1
8001cd0: 61da str r2, [r3, #28]
/* DMA2D FGOR register configuration -------------------------------------*/
WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset);
8001cd2: 687b ldr r3, [r7, #4]
8001cd4: 681b ldr r3, [r3, #0]
8001cd6: 693a ldr r2, [r7, #16]
8001cd8: 6812 ldr r2, [r2, #0]
8001cda: 611a str r2, [r3, #16]
/* DMA2D FGCOLR register configuration -------------------------------------*/
if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
8001cdc: 693b ldr r3, [r7, #16]
8001cde: 685b ldr r3, [r3, #4]
8001ce0: 2b0a cmp r3, #10
8001ce2: d003 beq.n 8001cec <HAL_DMA2D_ConfigLayer+0xf4>
8001ce4: 693b ldr r3, [r7, #16]
8001ce6: 685b ldr r3, [r3, #4]
8001ce8: 2b09 cmp r3, #9
8001cea: d106 bne.n 8001cfa <HAL_DMA2D_ConfigLayer+0x102>
{
WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE|DMA2D_FGCOLR_GREEN|DMA2D_FGCOLR_RED));
8001cec: 693b ldr r3, [r7, #16]
8001cee: 68da ldr r2, [r3, #12]
8001cf0: 687b ldr r3, [r7, #4]
8001cf2: 681b ldr r3, [r3, #0]
8001cf4: f022 427f bic.w r2, r2, #4278190080 ; 0xff000000
8001cf8: 621a str r2, [r3, #32]
}
}
/* Initialize the DMA2D state*/
hdma2d->State = HAL_DMA2D_STATE_READY;
8001cfa: 687b ldr r3, [r7, #4]
8001cfc: 2201 movs r2, #1
8001cfe: f883 2039 strb.w r2, [r3, #57] ; 0x39
/* Process unlocked */
__HAL_UNLOCK(hdma2d);
8001d02: 687b ldr r3, [r7, #4]
8001d04: 2200 movs r2, #0
8001d06: f883 2038 strb.w r2, [r3, #56] ; 0x38
return HAL_OK;
8001d0a: 2300 movs r3, #0
}
8001d0c: 4618 mov r0, r3
8001d0e: 371c adds r7, #28
8001d10: 46bd mov sp, r7
8001d12: f85d 7b04 ldr.w r7, [sp], #4
8001d16: 4770 bx lr
8001d18: ff03000f .word 0xff03000f
08001d1c <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
8001d1c: b480 push {r7}
8001d1e: b089 sub sp, #36 ; 0x24
8001d20: af00 add r7, sp, #0
8001d22: 6078 str r0, [r7, #4]
8001d24: 6039 str r1, [r7, #0]
uint32_t position;
uint32_t ioposition = 0x00U;
8001d26: 2300 movs r3, #0
8001d28: 617b str r3, [r7, #20]
uint32_t iocurrent = 0x00U;
8001d2a: 2300 movs r3, #0
8001d2c: 613b str r3, [r7, #16]
uint32_t temp = 0x00U;
8001d2e: 2300 movs r3, #0
8001d30: 61bb str r3, [r7, #24]
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Configure the port pins */
for(position = 0U; position < GPIO_NUMBER; position++)
8001d32: 2300 movs r3, #0
8001d34: 61fb str r3, [r7, #28]
8001d36: e177 b.n 8002028 <HAL_GPIO_Init+0x30c>
{
/* Get the IO position */
ioposition = 0x01U << position;
8001d38: 2201 movs r2, #1
8001d3a: 69fb ldr r3, [r7, #28]
8001d3c: fa02 f303 lsl.w r3, r2, r3
8001d40: 617b str r3, [r7, #20]
/* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
8001d42: 683b ldr r3, [r7, #0]
8001d44: 681b ldr r3, [r3, #0]
8001d46: 697a ldr r2, [r7, #20]
8001d48: 4013 ands r3, r2
8001d4a: 613b str r3, [r7, #16]
if(iocurrent == ioposition)
8001d4c: 693a ldr r2, [r7, #16]
8001d4e: 697b ldr r3, [r7, #20]
8001d50: 429a cmp r2, r3
8001d52: f040 8166 bne.w 8002022 <HAL_GPIO_Init+0x306>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
8001d56: 683b ldr r3, [r7, #0]
8001d58: 685b ldr r3, [r3, #4]
8001d5a: 2b01 cmp r3, #1
8001d5c: d00b beq.n 8001d76 <HAL_GPIO_Init+0x5a>
8001d5e: 683b ldr r3, [r7, #0]
8001d60: 685b ldr r3, [r3, #4]
8001d62: 2b02 cmp r3, #2
8001d64: d007 beq.n 8001d76 <HAL_GPIO_Init+0x5a>
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
8001d66: 683b ldr r3, [r7, #0]
8001d68: 685b ldr r3, [r3, #4]
if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
8001d6a: 2b11 cmp r3, #17
8001d6c: d003 beq.n 8001d76 <HAL_GPIO_Init+0x5a>
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
8001d6e: 683b ldr r3, [r7, #0]
8001d70: 685b ldr r3, [r3, #4]
8001d72: 2b12 cmp r3, #18
8001d74: d130 bne.n 8001dd8 <HAL_GPIO_Init+0xbc>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
8001d76: 687b ldr r3, [r7, #4]
8001d78: 689b ldr r3, [r3, #8]
8001d7a: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
8001d7c: 69fb ldr r3, [r7, #28]
8001d7e: 005b lsls r3, r3, #1
8001d80: 2203 movs r2, #3
8001d82: fa02 f303 lsl.w r3, r2, r3
8001d86: 43db mvns r3, r3
8001d88: 69ba ldr r2, [r7, #24]
8001d8a: 4013 ands r3, r2
8001d8c: 61bb str r3, [r7, #24]
temp |= (GPIO_Init->Speed << (position * 2U));
8001d8e: 683b ldr r3, [r7, #0]
8001d90: 68da ldr r2, [r3, #12]
8001d92: 69fb ldr r3, [r7, #28]
8001d94: 005b lsls r3, r3, #1
8001d96: fa02 f303 lsl.w r3, r2, r3
8001d9a: 69ba ldr r2, [r7, #24]
8001d9c: 4313 orrs r3, r2
8001d9e: 61bb str r3, [r7, #24]
GPIOx->OSPEEDR = temp;
8001da0: 687b ldr r3, [r7, #4]
8001da2: 69ba ldr r2, [r7, #24]
8001da4: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
8001da6: 687b ldr r3, [r7, #4]
8001da8: 685b ldr r3, [r3, #4]
8001daa: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
8001dac: 2201 movs r2, #1
8001dae: 69fb ldr r3, [r7, #28]
8001db0: fa02 f303 lsl.w r3, r2, r3
8001db4: 43db mvns r3, r3
8001db6: 69ba ldr r2, [r7, #24]
8001db8: 4013 ands r3, r2
8001dba: 61bb str r3, [r7, #24]
temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
8001dbc: 683b ldr r3, [r7, #0]
8001dbe: 685b ldr r3, [r3, #4]
8001dc0: 091b lsrs r3, r3, #4
8001dc2: f003 0201 and.w r2, r3, #1
8001dc6: 69fb ldr r3, [r7, #28]
8001dc8: fa02 f303 lsl.w r3, r2, r3
8001dcc: 69ba ldr r2, [r7, #24]
8001dce: 4313 orrs r3, r2
8001dd0: 61bb str r3, [r7, #24]
GPIOx->OTYPER = temp;
8001dd2: 687b ldr r3, [r7, #4]
8001dd4: 69ba ldr r2, [r7, #24]
8001dd6: 605a str r2, [r3, #4]
}
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
8001dd8: 687b ldr r3, [r7, #4]
8001dda: 68db ldr r3, [r3, #12]
8001ddc: 61bb str r3, [r7, #24]
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
8001dde: 69fb ldr r3, [r7, #28]
8001de0: 005b lsls r3, r3, #1
8001de2: 2203 movs r2, #3
8001de4: fa02 f303 lsl.w r3, r2, r3
8001de8: 43db mvns r3, r3
8001dea: 69ba ldr r2, [r7, #24]
8001dec: 4013 ands r3, r2
8001dee: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Pull) << (position * 2U));
8001df0: 683b ldr r3, [r7, #0]
8001df2: 689a ldr r2, [r3, #8]
8001df4: 69fb ldr r3, [r7, #28]
8001df6: 005b lsls r3, r3, #1
8001df8: fa02 f303 lsl.w r3, r2, r3
8001dfc: 69ba ldr r2, [r7, #24]
8001dfe: 4313 orrs r3, r2
8001e00: 61bb str r3, [r7, #24]
GPIOx->PUPDR = temp;
8001e02: 687b ldr r3, [r7, #4]
8001e04: 69ba ldr r2, [r7, #24]
8001e06: 60da str r2, [r3, #12]
/* In case of Alternate function mode selection */
if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
8001e08: 683b ldr r3, [r7, #0]
8001e0a: 685b ldr r3, [r3, #4]
8001e0c: 2b02 cmp r3, #2
8001e0e: d003 beq.n 8001e18 <HAL_GPIO_Init+0xfc>
8001e10: 683b ldr r3, [r7, #0]
8001e12: 685b ldr r3, [r3, #4]
8001e14: 2b12 cmp r3, #18
8001e16: d123 bne.n 8001e60 <HAL_GPIO_Init+0x144>
{
/* Check the Alternate function parameter */
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3U];
8001e18: 69fb ldr r3, [r7, #28]
8001e1a: 08da lsrs r2, r3, #3
8001e1c: 687b ldr r3, [r7, #4]
8001e1e: 3208 adds r2, #8
8001e20: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8001e24: 61bb str r3, [r7, #24]
temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
8001e26: 69fb ldr r3, [r7, #28]
8001e28: f003 0307 and.w r3, r3, #7
8001e2c: 009b lsls r3, r3, #2
8001e2e: 220f movs r2, #15
8001e30: fa02 f303 lsl.w r3, r2, r3
8001e34: 43db mvns r3, r3
8001e36: 69ba ldr r2, [r7, #24]
8001e38: 4013 ands r3, r2
8001e3a: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
8001e3c: 683b ldr r3, [r7, #0]
8001e3e: 691a ldr r2, [r3, #16]
8001e40: 69fb ldr r3, [r7, #28]
8001e42: f003 0307 and.w r3, r3, #7
8001e46: 009b lsls r3, r3, #2
8001e48: fa02 f303 lsl.w r3, r2, r3
8001e4c: 69ba ldr r2, [r7, #24]
8001e4e: 4313 orrs r3, r2
8001e50: 61bb str r3, [r7, #24]
GPIOx->AFR[position >> 3U] = temp;
8001e52: 69fb ldr r3, [r7, #28]
8001e54: 08da lsrs r2, r3, #3
8001e56: 687b ldr r3, [r7, #4]
8001e58: 3208 adds r2, #8
8001e5a: 69b9 ldr r1, [r7, #24]
8001e5c: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
8001e60: 687b ldr r3, [r7, #4]
8001e62: 681b ldr r3, [r3, #0]
8001e64: 61bb str r3, [r7, #24]
temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
8001e66: 69fb ldr r3, [r7, #28]
8001e68: 005b lsls r3, r3, #1
8001e6a: 2203 movs r2, #3
8001e6c: fa02 f303 lsl.w r3, r2, r3
8001e70: 43db mvns r3, r3
8001e72: 69ba ldr r2, [r7, #24]
8001e74: 4013 ands r3, r2
8001e76: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
8001e78: 683b ldr r3, [r7, #0]
8001e7a: 685b ldr r3, [r3, #4]
8001e7c: f003 0203 and.w r2, r3, #3
8001e80: 69fb ldr r3, [r7, #28]
8001e82: 005b lsls r3, r3, #1
8001e84: fa02 f303 lsl.w r3, r2, r3
8001e88: 69ba ldr r2, [r7, #24]
8001e8a: 4313 orrs r3, r2
8001e8c: 61bb str r3, [r7, #24]
GPIOx->MODER = temp;
8001e8e: 687b ldr r3, [r7, #4]
8001e90: 69ba ldr r2, [r7, #24]
8001e92: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
8001e94: 683b ldr r3, [r7, #0]
8001e96: 685b ldr r3, [r3, #4]
8001e98: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8001e9c: 2b00 cmp r3, #0
8001e9e: f000 80c0 beq.w 8002022 <HAL_GPIO_Init+0x306>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8001ea2: 2300 movs r3, #0
8001ea4: 60fb str r3, [r7, #12]
8001ea6: 4b65 ldr r3, [pc, #404] ; (800203c <HAL_GPIO_Init+0x320>)
8001ea8: 6c5b ldr r3, [r3, #68] ; 0x44
8001eaa: 4a64 ldr r2, [pc, #400] ; (800203c <HAL_GPIO_Init+0x320>)
8001eac: f443 4380 orr.w r3, r3, #16384 ; 0x4000
8001eb0: 6453 str r3, [r2, #68] ; 0x44
8001eb2: 4b62 ldr r3, [pc, #392] ; (800203c <HAL_GPIO_Init+0x320>)
8001eb4: 6c5b ldr r3, [r3, #68] ; 0x44
8001eb6: f403 4380 and.w r3, r3, #16384 ; 0x4000
8001eba: 60fb str r3, [r7, #12]
8001ebc: 68fb ldr r3, [r7, #12]
temp = SYSCFG->EXTICR[position >> 2U];
8001ebe: 4a60 ldr r2, [pc, #384] ; (8002040 <HAL_GPIO_Init+0x324>)
8001ec0: 69fb ldr r3, [r7, #28]
8001ec2: 089b lsrs r3, r3, #2
8001ec4: 3302 adds r3, #2
8001ec6: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8001eca: 61bb str r3, [r7, #24]
temp &= ~(0x0FU << (4U * (position & 0x03U)));
8001ecc: 69fb ldr r3, [r7, #28]
8001ece: f003 0303 and.w r3, r3, #3
8001ed2: 009b lsls r3, r3, #2
8001ed4: 220f movs r2, #15
8001ed6: fa02 f303 lsl.w r3, r2, r3
8001eda: 43db mvns r3, r3
8001edc: 69ba ldr r2, [r7, #24]
8001ede: 4013 ands r3, r2
8001ee0: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
8001ee2: 687b ldr r3, [r7, #4]
8001ee4: 4a57 ldr r2, [pc, #348] ; (8002044 <HAL_GPIO_Init+0x328>)
8001ee6: 4293 cmp r3, r2
8001ee8: d037 beq.n 8001f5a <HAL_GPIO_Init+0x23e>
8001eea: 687b ldr r3, [r7, #4]
8001eec: 4a56 ldr r2, [pc, #344] ; (8002048 <HAL_GPIO_Init+0x32c>)
8001eee: 4293 cmp r3, r2
8001ef0: d031 beq.n 8001f56 <HAL_GPIO_Init+0x23a>
8001ef2: 687b ldr r3, [r7, #4]
8001ef4: 4a55 ldr r2, [pc, #340] ; (800204c <HAL_GPIO_Init+0x330>)
8001ef6: 4293 cmp r3, r2
8001ef8: d02b beq.n 8001f52 <HAL_GPIO_Init+0x236>
8001efa: 687b ldr r3, [r7, #4]
8001efc: 4a54 ldr r2, [pc, #336] ; (8002050 <HAL_GPIO_Init+0x334>)
8001efe: 4293 cmp r3, r2
8001f00: d025 beq.n 8001f4e <HAL_GPIO_Init+0x232>
8001f02: 687b ldr r3, [r7, #4]
8001f04: 4a53 ldr r2, [pc, #332] ; (8002054 <HAL_GPIO_Init+0x338>)
8001f06: 4293 cmp r3, r2
8001f08: d01f beq.n 8001f4a <HAL_GPIO_Init+0x22e>
8001f0a: 687b ldr r3, [r7, #4]
8001f0c: 4a52 ldr r2, [pc, #328] ; (8002058 <HAL_GPIO_Init+0x33c>)
8001f0e: 4293 cmp r3, r2
8001f10: d019 beq.n 8001f46 <HAL_GPIO_Init+0x22a>
8001f12: 687b ldr r3, [r7, #4]
8001f14: 4a51 ldr r2, [pc, #324] ; (800205c <HAL_GPIO_Init+0x340>)
8001f16: 4293 cmp r3, r2
8001f18: d013 beq.n 8001f42 <HAL_GPIO_Init+0x226>
8001f1a: 687b ldr r3, [r7, #4]
8001f1c: 4a50 ldr r2, [pc, #320] ; (8002060 <HAL_GPIO_Init+0x344>)
8001f1e: 4293 cmp r3, r2
8001f20: d00d beq.n 8001f3e <HAL_GPIO_Init+0x222>
8001f22: 687b ldr r3, [r7, #4]
8001f24: 4a4f ldr r2, [pc, #316] ; (8002064 <HAL_GPIO_Init+0x348>)
8001f26: 4293 cmp r3, r2
8001f28: d007 beq.n 8001f3a <HAL_GPIO_Init+0x21e>
8001f2a: 687b ldr r3, [r7, #4]
8001f2c: 4a4e ldr r2, [pc, #312] ; (8002068 <HAL_GPIO_Init+0x34c>)
8001f2e: 4293 cmp r3, r2
8001f30: d101 bne.n 8001f36 <HAL_GPIO_Init+0x21a>
8001f32: 2309 movs r3, #9
8001f34: e012 b.n 8001f5c <HAL_GPIO_Init+0x240>
8001f36: 230a movs r3, #10
8001f38: e010 b.n 8001f5c <HAL_GPIO_Init+0x240>
8001f3a: 2308 movs r3, #8
8001f3c: e00e b.n 8001f5c <HAL_GPIO_Init+0x240>
8001f3e: 2307 movs r3, #7
8001f40: e00c b.n 8001f5c <HAL_GPIO_Init+0x240>
8001f42: 2306 movs r3, #6
8001f44: e00a b.n 8001f5c <HAL_GPIO_Init+0x240>
8001f46: 2305 movs r3, #5
8001f48: e008 b.n 8001f5c <HAL_GPIO_Init+0x240>
8001f4a: 2304 movs r3, #4
8001f4c: e006 b.n 8001f5c <HAL_GPIO_Init+0x240>
8001f4e: 2303 movs r3, #3
8001f50: e004 b.n 8001f5c <HAL_GPIO_Init+0x240>
8001f52: 2302 movs r3, #2
8001f54: e002 b.n 8001f5c <HAL_GPIO_Init+0x240>
8001f56: 2301 movs r3, #1
8001f58: e000 b.n 8001f5c <HAL_GPIO_Init+0x240>
8001f5a: 2300 movs r3, #0
8001f5c: 69fa ldr r2, [r7, #28]
8001f5e: f002 0203 and.w r2, r2, #3
8001f62: 0092 lsls r2, r2, #2
8001f64: 4093 lsls r3, r2
8001f66: 69ba ldr r2, [r7, #24]
8001f68: 4313 orrs r3, r2
8001f6a: 61bb str r3, [r7, #24]
SYSCFG->EXTICR[position >> 2U] = temp;
8001f6c: 4934 ldr r1, [pc, #208] ; (8002040 <HAL_GPIO_Init+0x324>)
8001f6e: 69fb ldr r3, [r7, #28]
8001f70: 089b lsrs r3, r3, #2
8001f72: 3302 adds r3, #2
8001f74: 69ba ldr r2, [r7, #24]
8001f76: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear EXTI line configuration */
temp = EXTI->IMR;
8001f7a: 4b3c ldr r3, [pc, #240] ; (800206c <HAL_GPIO_Init+0x350>)
8001f7c: 681b ldr r3, [r3, #0]
8001f7e: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8001f80: 693b ldr r3, [r7, #16]
8001f82: 43db mvns r3, r3
8001f84: 69ba ldr r2, [r7, #24]
8001f86: 4013 ands r3, r2
8001f88: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
8001f8a: 683b ldr r3, [r7, #0]
8001f8c: 685b ldr r3, [r3, #4]
8001f8e: f403 3380 and.w r3, r3, #65536 ; 0x10000
8001f92: 2b00 cmp r3, #0
8001f94: d003 beq.n 8001f9e <HAL_GPIO_Init+0x282>
{
temp |= iocurrent;
8001f96: 69ba ldr r2, [r7, #24]
8001f98: 693b ldr r3, [r7, #16]
8001f9a: 4313 orrs r3, r2
8001f9c: 61bb str r3, [r7, #24]
}
EXTI->IMR = temp;
8001f9e: 4a33 ldr r2, [pc, #204] ; (800206c <HAL_GPIO_Init+0x350>)
8001fa0: 69bb ldr r3, [r7, #24]
8001fa2: 6013 str r3, [r2, #0]
temp = EXTI->EMR;
8001fa4: 4b31 ldr r3, [pc, #196] ; (800206c <HAL_GPIO_Init+0x350>)
8001fa6: 685b ldr r3, [r3, #4]
8001fa8: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8001faa: 693b ldr r3, [r7, #16]
8001fac: 43db mvns r3, r3
8001fae: 69ba ldr r2, [r7, #24]
8001fb0: 4013 ands r3, r2
8001fb2: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
8001fb4: 683b ldr r3, [r7, #0]
8001fb6: 685b ldr r3, [r3, #4]
8001fb8: f403 3300 and.w r3, r3, #131072 ; 0x20000
8001fbc: 2b00 cmp r3, #0
8001fbe: d003 beq.n 8001fc8 <HAL_GPIO_Init+0x2ac>
{
temp |= iocurrent;
8001fc0: 69ba ldr r2, [r7, #24]
8001fc2: 693b ldr r3, [r7, #16]
8001fc4: 4313 orrs r3, r2
8001fc6: 61bb str r3, [r7, #24]
}
EXTI->EMR = temp;
8001fc8: 4a28 ldr r2, [pc, #160] ; (800206c <HAL_GPIO_Init+0x350>)
8001fca: 69bb ldr r3, [r7, #24]
8001fcc: 6053 str r3, [r2, #4]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
8001fce: 4b27 ldr r3, [pc, #156] ; (800206c <HAL_GPIO_Init+0x350>)
8001fd0: 689b ldr r3, [r3, #8]
8001fd2: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8001fd4: 693b ldr r3, [r7, #16]
8001fd6: 43db mvns r3, r3
8001fd8: 69ba ldr r2, [r7, #24]
8001fda: 4013 ands r3, r2
8001fdc: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
8001fde: 683b ldr r3, [r7, #0]
8001fe0: 685b ldr r3, [r3, #4]
8001fe2: f403 1380 and.w r3, r3, #1048576 ; 0x100000
8001fe6: 2b00 cmp r3, #0
8001fe8: d003 beq.n 8001ff2 <HAL_GPIO_Init+0x2d6>
{
temp |= iocurrent;
8001fea: 69ba ldr r2, [r7, #24]
8001fec: 693b ldr r3, [r7, #16]
8001fee: 4313 orrs r3, r2
8001ff0: 61bb str r3, [r7, #24]
}
EXTI->RTSR = temp;
8001ff2: 4a1e ldr r2, [pc, #120] ; (800206c <HAL_GPIO_Init+0x350>)
8001ff4: 69bb ldr r3, [r7, #24]
8001ff6: 6093 str r3, [r2, #8]
temp = EXTI->FTSR;
8001ff8: 4b1c ldr r3, [pc, #112] ; (800206c <HAL_GPIO_Init+0x350>)
8001ffa: 68db ldr r3, [r3, #12]
8001ffc: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8001ffe: 693b ldr r3, [r7, #16]
8002000: 43db mvns r3, r3
8002002: 69ba ldr r2, [r7, #24]
8002004: 4013 ands r3, r2
8002006: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
8002008: 683b ldr r3, [r7, #0]
800200a: 685b ldr r3, [r3, #4]
800200c: f403 1300 and.w r3, r3, #2097152 ; 0x200000
8002010: 2b00 cmp r3, #0
8002012: d003 beq.n 800201c <HAL_GPIO_Init+0x300>
{
temp |= iocurrent;
8002014: 69ba ldr r2, [r7, #24]
8002016: 693b ldr r3, [r7, #16]
8002018: 4313 orrs r3, r2
800201a: 61bb str r3, [r7, #24]
}
EXTI->FTSR = temp;
800201c: 4a13 ldr r2, [pc, #76] ; (800206c <HAL_GPIO_Init+0x350>)
800201e: 69bb ldr r3, [r7, #24]
8002020: 60d3 str r3, [r2, #12]
for(position = 0U; position < GPIO_NUMBER; position++)
8002022: 69fb ldr r3, [r7, #28]
8002024: 3301 adds r3, #1
8002026: 61fb str r3, [r7, #28]
8002028: 69fb ldr r3, [r7, #28]
800202a: 2b0f cmp r3, #15
800202c: f67f ae84 bls.w 8001d38 <HAL_GPIO_Init+0x1c>
}
}
}
}
8002030: bf00 nop
8002032: 3724 adds r7, #36 ; 0x24
8002034: 46bd mov sp, r7
8002036: f85d 7b04 ldr.w r7, [sp], #4
800203a: 4770 bx lr
800203c: 40023800 .word 0x40023800
8002040: 40013800 .word 0x40013800
8002044: 40020000 .word 0x40020000
8002048: 40020400 .word 0x40020400
800204c: 40020800 .word 0x40020800
8002050: 40020c00 .word 0x40020c00
8002054: 40021000 .word 0x40021000
8002058: 40021400 .word 0x40021400
800205c: 40021800 .word 0x40021800
8002060: 40021c00 .word 0x40021c00
8002064: 40022000 .word 0x40022000
8002068: 40022400 .word 0x40022400
800206c: 40013c00 .word 0x40013c00
08002070 <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
8002070: b480 push {r7}
8002072: b083 sub sp, #12
8002074: af00 add r7, sp, #0
8002076: 6078 str r0, [r7, #4]
8002078: 460b mov r3, r1
800207a: 807b strh r3, [r7, #2]
800207c: 4613 mov r3, r2
800207e: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if(PinState != GPIO_PIN_RESET)
8002080: 787b ldrb r3, [r7, #1]
8002082: 2b00 cmp r3, #0
8002084: d003 beq.n 800208e <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = GPIO_Pin;
8002086: 887a ldrh r2, [r7, #2]
8002088: 687b ldr r3, [r7, #4]
800208a: 619a str r2, [r3, #24]
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
}
}
800208c: e003 b.n 8002096 <HAL_GPIO_WritePin+0x26>
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
800208e: 887b ldrh r3, [r7, #2]
8002090: 041a lsls r2, r3, #16
8002092: 687b ldr r3, [r7, #4]
8002094: 619a str r2, [r3, #24]
}
8002096: bf00 nop
8002098: 370c adds r7, #12
800209a: 46bd mov sp, r7
800209c: f85d 7b04 ldr.w r7, [sp], #4
80020a0: 4770 bx lr
...
080020a4 <HAL_I2C_Init>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
{
80020a4: b580 push {r7, lr}
80020a6: b084 sub sp, #16
80020a8: af00 add r7, sp, #0
80020aa: 6078 str r0, [r7, #4]
uint32_t freqrange;
uint32_t pclk1;
/* Check the I2C handle allocation */
if (hi2c == NULL)
80020ac: 687b ldr r3, [r7, #4]
80020ae: 2b00 cmp r3, #0
80020b0: d101 bne.n 80020b6 <HAL_I2C_Init+0x12>
{
return HAL_ERROR;
80020b2: 2301 movs r3, #1
80020b4: e11f b.n 80022f6 <HAL_I2C_Init+0x252>
assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
if (hi2c->State == HAL_I2C_STATE_RESET)
80020b6: 687b ldr r3, [r7, #4]
80020b8: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
80020bc: b2db uxtb r3, r3
80020be: 2b00 cmp r3, #0
80020c0: d106 bne.n 80020d0 <HAL_I2C_Init+0x2c>
{
/* Allocate lock resource and initialize it */
hi2c->Lock = HAL_UNLOCKED;
80020c2: 687b ldr r3, [r7, #4]
80020c4: 2200 movs r2, #0
80020c6: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Init the low level hardware : GPIO, CLOCK, NVIC */
hi2c->MspInitCallback(hi2c);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_I2C_MspInit(hi2c);
80020ca: 6878 ldr r0, [r7, #4]
80020cc: f7fe fedc bl 8000e88 <HAL_I2C_MspInit>
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
hi2c->State = HAL_I2C_STATE_BUSY;
80020d0: 687b ldr r3, [r7, #4]
80020d2: 2224 movs r2, #36 ; 0x24
80020d4: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
80020d8: 687b ldr r3, [r7, #4]
80020da: 681b ldr r3, [r3, #0]
80020dc: 681a ldr r2, [r3, #0]
80020de: 687b ldr r3, [r7, #4]
80020e0: 681b ldr r3, [r3, #0]
80020e2: f022 0201 bic.w r2, r2, #1
80020e6: 601a str r2, [r3, #0]
/*Reset I2C*/
hi2c->Instance->CR1 |= I2C_CR1_SWRST;
80020e8: 687b ldr r3, [r7, #4]
80020ea: 681b ldr r3, [r3, #0]
80020ec: 681a ldr r2, [r3, #0]
80020ee: 687b ldr r3, [r7, #4]
80020f0: 681b ldr r3, [r3, #0]
80020f2: f442 4200 orr.w r2, r2, #32768 ; 0x8000
80020f6: 601a str r2, [r3, #0]
hi2c->Instance->CR1 &= ~I2C_CR1_SWRST;
80020f8: 687b ldr r3, [r7, #4]
80020fa: 681b ldr r3, [r3, #0]
80020fc: 681a ldr r2, [r3, #0]
80020fe: 687b ldr r3, [r7, #4]
8002100: 681b ldr r3, [r3, #0]
8002102: f422 4200 bic.w r2, r2, #32768 ; 0x8000
8002106: 601a str r2, [r3, #0]
/* Get PCLK1 frequency */
pclk1 = HAL_RCC_GetPCLK1Freq();
8002108: f001 f922 bl 8003350 <HAL_RCC_GetPCLK1Freq>
800210c: 60f8 str r0, [r7, #12]
/* Check the minimum allowed PCLK1 frequency */
if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U)
800210e: 687b ldr r3, [r7, #4]
8002110: 685b ldr r3, [r3, #4]
8002112: 4a7b ldr r2, [pc, #492] ; (8002300 <HAL_I2C_Init+0x25c>)
8002114: 4293 cmp r3, r2
8002116: d807 bhi.n 8002128 <HAL_I2C_Init+0x84>
8002118: 68fb ldr r3, [r7, #12]
800211a: 4a7a ldr r2, [pc, #488] ; (8002304 <HAL_I2C_Init+0x260>)
800211c: 4293 cmp r3, r2
800211e: bf94 ite ls
8002120: 2301 movls r3, #1
8002122: 2300 movhi r3, #0
8002124: b2db uxtb r3, r3
8002126: e006 b.n 8002136 <HAL_I2C_Init+0x92>
8002128: 68fb ldr r3, [r7, #12]
800212a: 4a77 ldr r2, [pc, #476] ; (8002308 <HAL_I2C_Init+0x264>)
800212c: 4293 cmp r3, r2
800212e: bf94 ite ls
8002130: 2301 movls r3, #1
8002132: 2300 movhi r3, #0
8002134: b2db uxtb r3, r3
8002136: 2b00 cmp r3, #0
8002138: d001 beq.n 800213e <HAL_I2C_Init+0x9a>
{
return HAL_ERROR;
800213a: 2301 movs r3, #1
800213c: e0db b.n 80022f6 <HAL_I2C_Init+0x252>
}
/* Calculate frequency range */
freqrange = I2C_FREQRANGE(pclk1);
800213e: 68fb ldr r3, [r7, #12]
8002140: 4a72 ldr r2, [pc, #456] ; (800230c <HAL_I2C_Init+0x268>)
8002142: fba2 2303 umull r2, r3, r2, r3
8002146: 0c9b lsrs r3, r3, #18
8002148: 60bb str r3, [r7, #8]
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
/* Configure I2Cx: Frequency range */
MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange);
800214a: 687b ldr r3, [r7, #4]
800214c: 681b ldr r3, [r3, #0]
800214e: 685b ldr r3, [r3, #4]
8002150: f023 013f bic.w r1, r3, #63 ; 0x3f
8002154: 687b ldr r3, [r7, #4]
8002156: 681b ldr r3, [r3, #0]
8002158: 68ba ldr r2, [r7, #8]
800215a: 430a orrs r2, r1
800215c: 605a str r2, [r3, #4]
/*---------------------------- I2Cx TRISE Configuration --------------------*/
/* Configure I2Cx: Rise Time */
MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed));
800215e: 687b ldr r3, [r7, #4]
8002160: 681b ldr r3, [r3, #0]
8002162: 6a1b ldr r3, [r3, #32]
8002164: f023 013f bic.w r1, r3, #63 ; 0x3f
8002168: 687b ldr r3, [r7, #4]
800216a: 685b ldr r3, [r3, #4]
800216c: 4a64 ldr r2, [pc, #400] ; (8002300 <HAL_I2C_Init+0x25c>)
800216e: 4293 cmp r3, r2
8002170: d802 bhi.n 8002178 <HAL_I2C_Init+0xd4>
8002172: 68bb ldr r3, [r7, #8]
8002174: 3301 adds r3, #1
8002176: e009 b.n 800218c <HAL_I2C_Init+0xe8>
8002178: 68bb ldr r3, [r7, #8]
800217a: f44f 7296 mov.w r2, #300 ; 0x12c
800217e: fb02 f303 mul.w r3, r2, r3
8002182: 4a63 ldr r2, [pc, #396] ; (8002310 <HAL_I2C_Init+0x26c>)
8002184: fba2 2303 umull r2, r3, r2, r3
8002188: 099b lsrs r3, r3, #6
800218a: 3301 adds r3, #1
800218c: 687a ldr r2, [r7, #4]
800218e: 6812 ldr r2, [r2, #0]
8002190: 430b orrs r3, r1
8002192: 6213 str r3, [r2, #32]
/*---------------------------- I2Cx CCR Configuration ----------------------*/
/* Configure I2Cx: Speed */
MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle));
8002194: 687b ldr r3, [r7, #4]
8002196: 681b ldr r3, [r3, #0]
8002198: 69db ldr r3, [r3, #28]
800219a: f423 424f bic.w r2, r3, #52992 ; 0xcf00
800219e: f022 02ff bic.w r2, r2, #255 ; 0xff
80021a2: 687b ldr r3, [r7, #4]
80021a4: 685b ldr r3, [r3, #4]
80021a6: 4956 ldr r1, [pc, #344] ; (8002300 <HAL_I2C_Init+0x25c>)
80021a8: 428b cmp r3, r1
80021aa: d80d bhi.n 80021c8 <HAL_I2C_Init+0x124>
80021ac: 68fb ldr r3, [r7, #12]
80021ae: 1e59 subs r1, r3, #1
80021b0: 687b ldr r3, [r7, #4]
80021b2: 685b ldr r3, [r3, #4]
80021b4: 005b lsls r3, r3, #1
80021b6: fbb1 f3f3 udiv r3, r1, r3
80021ba: 3301 adds r3, #1
80021bc: f3c3 030b ubfx r3, r3, #0, #12
80021c0: 2b04 cmp r3, #4
80021c2: bf38 it cc
80021c4: 2304 movcc r3, #4
80021c6: e04f b.n 8002268 <HAL_I2C_Init+0x1c4>
80021c8: 687b ldr r3, [r7, #4]
80021ca: 689b ldr r3, [r3, #8]
80021cc: 2b00 cmp r3, #0
80021ce: d111 bne.n 80021f4 <HAL_I2C_Init+0x150>
80021d0: 68fb ldr r3, [r7, #12]
80021d2: 1e58 subs r0, r3, #1
80021d4: 687b ldr r3, [r7, #4]
80021d6: 6859 ldr r1, [r3, #4]
80021d8: 460b mov r3, r1
80021da: 005b lsls r3, r3, #1
80021dc: 440b add r3, r1
80021de: fbb0 f3f3 udiv r3, r0, r3
80021e2: 3301 adds r3, #1
80021e4: f3c3 030b ubfx r3, r3, #0, #12
80021e8: 2b00 cmp r3, #0
80021ea: bf0c ite eq
80021ec: 2301 moveq r3, #1
80021ee: 2300 movne r3, #0
80021f0: b2db uxtb r3, r3
80021f2: e012 b.n 800221a <HAL_I2C_Init+0x176>
80021f4: 68fb ldr r3, [r7, #12]
80021f6: 1e58 subs r0, r3, #1
80021f8: 687b ldr r3, [r7, #4]
80021fa: 6859 ldr r1, [r3, #4]
80021fc: 460b mov r3, r1
80021fe: 009b lsls r3, r3, #2
8002200: 440b add r3, r1
8002202: 0099 lsls r1, r3, #2
8002204: 440b add r3, r1
8002206: fbb0 f3f3 udiv r3, r0, r3
800220a: 3301 adds r3, #1
800220c: f3c3 030b ubfx r3, r3, #0, #12
8002210: 2b00 cmp r3, #0
8002212: bf0c ite eq
8002214: 2301 moveq r3, #1
8002216: 2300 movne r3, #0
8002218: b2db uxtb r3, r3
800221a: 2b00 cmp r3, #0
800221c: d001 beq.n 8002222 <HAL_I2C_Init+0x17e>
800221e: 2301 movs r3, #1
8002220: e022 b.n 8002268 <HAL_I2C_Init+0x1c4>
8002222: 687b ldr r3, [r7, #4]
8002224: 689b ldr r3, [r3, #8]
8002226: 2b00 cmp r3, #0
8002228: d10e bne.n 8002248 <HAL_I2C_Init+0x1a4>
800222a: 68fb ldr r3, [r7, #12]
800222c: 1e58 subs r0, r3, #1
800222e: 687b ldr r3, [r7, #4]
8002230: 6859 ldr r1, [r3, #4]
8002232: 460b mov r3, r1
8002234: 005b lsls r3, r3, #1
8002236: 440b add r3, r1
8002238: fbb0 f3f3 udiv r3, r0, r3
800223c: 3301 adds r3, #1
800223e: f3c3 030b ubfx r3, r3, #0, #12
8002242: f443 4300 orr.w r3, r3, #32768 ; 0x8000
8002246: e00f b.n 8002268 <HAL_I2C_Init+0x1c4>
8002248: 68fb ldr r3, [r7, #12]
800224a: 1e58 subs r0, r3, #1
800224c: 687b ldr r3, [r7, #4]
800224e: 6859 ldr r1, [r3, #4]
8002250: 460b mov r3, r1
8002252: 009b lsls r3, r3, #2
8002254: 440b add r3, r1
8002256: 0099 lsls r1, r3, #2
8002258: 440b add r3, r1
800225a: fbb0 f3f3 udiv r3, r0, r3
800225e: 3301 adds r3, #1
8002260: f3c3 030b ubfx r3, r3, #0, #12
8002264: f443 4340 orr.w r3, r3, #49152 ; 0xc000
8002268: 6879 ldr r1, [r7, #4]
800226a: 6809 ldr r1, [r1, #0]
800226c: 4313 orrs r3, r2
800226e: 61cb str r3, [r1, #28]
/*---------------------------- I2Cx CR1 Configuration ----------------------*/
/* Configure I2Cx: Generalcall and NoStretch mode */
MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode));
8002270: 687b ldr r3, [r7, #4]
8002272: 681b ldr r3, [r3, #0]
8002274: 681b ldr r3, [r3, #0]
8002276: f023 01c0 bic.w r1, r3, #192 ; 0xc0
800227a: 687b ldr r3, [r7, #4]
800227c: 69da ldr r2, [r3, #28]
800227e: 687b ldr r3, [r7, #4]
8002280: 6a1b ldr r3, [r3, #32]
8002282: 431a orrs r2, r3
8002284: 687b ldr r3, [r7, #4]
8002286: 681b ldr r3, [r3, #0]
8002288: 430a orrs r2, r1
800228a: 601a str r2, [r3, #0]
/*---------------------------- I2Cx OAR1 Configuration ---------------------*/
/* Configure I2Cx: Own Address1 and addressing mode */
MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1));
800228c: 687b ldr r3, [r7, #4]
800228e: 681b ldr r3, [r3, #0]
8002290: 689b ldr r3, [r3, #8]
8002292: f423 4303 bic.w r3, r3, #33536 ; 0x8300
8002296: f023 03ff bic.w r3, r3, #255 ; 0xff
800229a: 687a ldr r2, [r7, #4]
800229c: 6911 ldr r1, [r2, #16]
800229e: 687a ldr r2, [r7, #4]
80022a0: 68d2 ldr r2, [r2, #12]
80022a2: 4311 orrs r1, r2
80022a4: 687a ldr r2, [r7, #4]
80022a6: 6812 ldr r2, [r2, #0]
80022a8: 430b orrs r3, r1
80022aa: 6093 str r3, [r2, #8]
/*---------------------------- I2Cx OAR2 Configuration ---------------------*/
/* Configure I2Cx: Dual mode and Own Address2 */
MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2));
80022ac: 687b ldr r3, [r7, #4]
80022ae: 681b ldr r3, [r3, #0]
80022b0: 68db ldr r3, [r3, #12]
80022b2: f023 01ff bic.w r1, r3, #255 ; 0xff
80022b6: 687b ldr r3, [r7, #4]
80022b8: 695a ldr r2, [r3, #20]
80022ba: 687b ldr r3, [r7, #4]
80022bc: 699b ldr r3, [r3, #24]
80022be: 431a orrs r2, r3
80022c0: 687b ldr r3, [r7, #4]
80022c2: 681b ldr r3, [r3, #0]
80022c4: 430a orrs r2, r1
80022c6: 60da str r2, [r3, #12]
/* Enable the selected I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
80022c8: 687b ldr r3, [r7, #4]
80022ca: 681b ldr r3, [r3, #0]
80022cc: 681a ldr r2, [r3, #0]
80022ce: 687b ldr r3, [r7, #4]
80022d0: 681b ldr r3, [r3, #0]
80022d2: f042 0201 orr.w r2, r2, #1
80022d6: 601a str r2, [r3, #0]
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
80022d8: 687b ldr r3, [r7, #4]
80022da: 2200 movs r2, #0
80022dc: 641a str r2, [r3, #64] ; 0x40
hi2c->State = HAL_I2C_STATE_READY;
80022de: 687b ldr r3, [r7, #4]
80022e0: 2220 movs r2, #32
80022e2: f883 203d strb.w r2, [r3, #61] ; 0x3d
hi2c->PreviousState = I2C_STATE_NONE;
80022e6: 687b ldr r3, [r7, #4]
80022e8: 2200 movs r2, #0
80022ea: 631a str r2, [r3, #48] ; 0x30
hi2c->Mode = HAL_I2C_MODE_NONE;
80022ec: 687b ldr r3, [r7, #4]
80022ee: 2200 movs r2, #0
80022f0: f883 203e strb.w r2, [r3, #62] ; 0x3e
return HAL_OK;
80022f4: 2300 movs r3, #0
}
80022f6: 4618 mov r0, r3
80022f8: 3710 adds r7, #16
80022fa: 46bd mov sp, r7
80022fc: bd80 pop {r7, pc}
80022fe: bf00 nop
8002300: 000186a0 .word 0x000186a0
8002304: 001e847f .word 0x001e847f
8002308: 003d08ff .word 0x003d08ff
800230c: 431bde83 .word 0x431bde83
8002310: 10624dd3 .word 0x10624dd3
08002314 <HAL_I2CEx_ConfigAnalogFilter>:
* the configuration information for the specified I2Cx peripheral.
* @param AnalogFilter new state of the Analog filter.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
{
8002314: b480 push {r7}
8002316: b083 sub sp, #12
8002318: af00 add r7, sp, #0
800231a: 6078 str r0, [r7, #4]
800231c: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
if (hi2c->State == HAL_I2C_STATE_READY)
800231e: 687b ldr r3, [r7, #4]
8002320: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
8002324: b2db uxtb r3, r3
8002326: 2b20 cmp r3, #32
8002328: d129 bne.n 800237e <HAL_I2CEx_ConfigAnalogFilter+0x6a>
{
hi2c->State = HAL_I2C_STATE_BUSY;
800232a: 687b ldr r3, [r7, #4]
800232c: 2224 movs r2, #36 ; 0x24
800232e: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
8002332: 687b ldr r3, [r7, #4]
8002334: 681b ldr r3, [r3, #0]
8002336: 681a ldr r2, [r3, #0]
8002338: 687b ldr r3, [r7, #4]
800233a: 681b ldr r3, [r3, #0]
800233c: f022 0201 bic.w r2, r2, #1
8002340: 601a str r2, [r3, #0]
/* Reset I2Cx ANOFF bit */
hi2c->Instance->FLTR &= ~(I2C_FLTR_ANOFF);
8002342: 687b ldr r3, [r7, #4]
8002344: 681b ldr r3, [r3, #0]
8002346: 6a5a ldr r2, [r3, #36] ; 0x24
8002348: 687b ldr r3, [r7, #4]
800234a: 681b ldr r3, [r3, #0]
800234c: f022 0210 bic.w r2, r2, #16
8002350: 625a str r2, [r3, #36] ; 0x24
/* Disable the analog filter */
hi2c->Instance->FLTR |= AnalogFilter;
8002352: 687b ldr r3, [r7, #4]
8002354: 681b ldr r3, [r3, #0]
8002356: 6a59 ldr r1, [r3, #36] ; 0x24
8002358: 687b ldr r3, [r7, #4]
800235a: 681b ldr r3, [r3, #0]
800235c: 683a ldr r2, [r7, #0]
800235e: 430a orrs r2, r1
8002360: 625a str r2, [r3, #36] ; 0x24
__HAL_I2C_ENABLE(hi2c);
8002362: 687b ldr r3, [r7, #4]
8002364: 681b ldr r3, [r3, #0]
8002366: 681a ldr r2, [r3, #0]
8002368: 687b ldr r3, [r7, #4]
800236a: 681b ldr r3, [r3, #0]
800236c: f042 0201 orr.w r2, r2, #1
8002370: 601a str r2, [r3, #0]
hi2c->State = HAL_I2C_STATE_READY;
8002372: 687b ldr r3, [r7, #4]
8002374: 2220 movs r2, #32
8002376: f883 203d strb.w r2, [r3, #61] ; 0x3d
return HAL_OK;
800237a: 2300 movs r3, #0
800237c: e000 b.n 8002380 <HAL_I2CEx_ConfigAnalogFilter+0x6c>
}
else
{
return HAL_BUSY;
800237e: 2302 movs r3, #2
}
}
8002380: 4618 mov r0, r3
8002382: 370c adds r7, #12
8002384: 46bd mov sp, r7
8002386: f85d 7b04 ldr.w r7, [sp], #4
800238a: 4770 bx lr
0800238c <HAL_I2CEx_ConfigDigitalFilter>:
* the configuration information for the specified I2Cx peripheral.
* @param DigitalFilter Coefficient of digital noise filter between 0x00 and 0x0F.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
{
800238c: b480 push {r7}
800238e: b085 sub sp, #20
8002390: af00 add r7, sp, #0
8002392: 6078 str r0, [r7, #4]
8002394: 6039 str r1, [r7, #0]
uint16_t tmpreg = 0;
8002396: 2300 movs r3, #0
8002398: 81fb strh r3, [r7, #14]
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
if (hi2c->State == HAL_I2C_STATE_READY)
800239a: 687b ldr r3, [r7, #4]
800239c: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
80023a0: b2db uxtb r3, r3
80023a2: 2b20 cmp r3, #32
80023a4: d12a bne.n 80023fc <HAL_I2CEx_ConfigDigitalFilter+0x70>
{
hi2c->State = HAL_I2C_STATE_BUSY;
80023a6: 687b ldr r3, [r7, #4]
80023a8: 2224 movs r2, #36 ; 0x24
80023aa: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
80023ae: 687b ldr r3, [r7, #4]
80023b0: 681b ldr r3, [r3, #0]
80023b2: 681a ldr r2, [r3, #0]
80023b4: 687b ldr r3, [r7, #4]
80023b6: 681b ldr r3, [r3, #0]
80023b8: f022 0201 bic.w r2, r2, #1
80023bc: 601a str r2, [r3, #0]
/* Get the old register value */
tmpreg = hi2c->Instance->FLTR;
80023be: 687b ldr r3, [r7, #4]
80023c0: 681b ldr r3, [r3, #0]
80023c2: 6a5b ldr r3, [r3, #36] ; 0x24
80023c4: 81fb strh r3, [r7, #14]
/* Reset I2Cx DNF bit [3:0] */
tmpreg &= ~(I2C_FLTR_DNF);
80023c6: 89fb ldrh r3, [r7, #14]
80023c8: f023 030f bic.w r3, r3, #15
80023cc: 81fb strh r3, [r7, #14]
/* Set I2Cx DNF coefficient */
tmpreg |= DigitalFilter;
80023ce: 683b ldr r3, [r7, #0]
80023d0: b29a uxth r2, r3
80023d2: 89fb ldrh r3, [r7, #14]
80023d4: 4313 orrs r3, r2
80023d6: 81fb strh r3, [r7, #14]
/* Store the new register value */
hi2c->Instance->FLTR = tmpreg;
80023d8: 687b ldr r3, [r7, #4]
80023da: 681b ldr r3, [r3, #0]
80023dc: 89fa ldrh r2, [r7, #14]
80023de: 625a str r2, [r3, #36] ; 0x24
__HAL_I2C_ENABLE(hi2c);
80023e0: 687b ldr r3, [r7, #4]
80023e2: 681b ldr r3, [r3, #0]
80023e4: 681a ldr r2, [r3, #0]
80023e6: 687b ldr r3, [r7, #4]
80023e8: 681b ldr r3, [r3, #0]
80023ea: f042 0201 orr.w r2, r2, #1
80023ee: 601a str r2, [r3, #0]
hi2c->State = HAL_I2C_STATE_READY;
80023f0: 687b ldr r3, [r7, #4]
80023f2: 2220 movs r2, #32
80023f4: f883 203d strb.w r2, [r3, #61] ; 0x3d
return HAL_OK;
80023f8: 2300 movs r3, #0
80023fa: e000 b.n 80023fe <HAL_I2CEx_ConfigDigitalFilter+0x72>
}
else
{
return HAL_BUSY;
80023fc: 2302 movs r3, #2
}
}
80023fe: 4618 mov r0, r3
8002400: 3714 adds r7, #20
8002402: 46bd mov sp, r7
8002404: f85d 7b04 ldr.w r7, [sp], #4
8002408: 4770 bx lr
...
0800240c <HAL_LTDC_Init>:
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc)
{
800240c: b580 push {r7, lr}
800240e: b084 sub sp, #16
8002410: af00 add r7, sp, #0
8002412: 6078 str r0, [r7, #4]
uint32_t tmp, tmp1;
/* Check the LTDC peripheral state */
if (hltdc == NULL)
8002414: 687b ldr r3, [r7, #4]
8002416: 2b00 cmp r3, #0
8002418: d101 bne.n 800241e <HAL_LTDC_Init+0x12>
{
return HAL_ERROR;
800241a: 2301 movs r3, #1
800241c: e0bf b.n 800259e <HAL_LTDC_Init+0x192>
}
/* Init the low level hardware */
hltdc->MspInitCallback(hltdc);
}
#else
if (hltdc->State == HAL_LTDC_STATE_RESET)
800241e: 687b ldr r3, [r7, #4]
8002420: f893 30a1 ldrb.w r3, [r3, #161] ; 0xa1
8002424: b2db uxtb r3, r3
8002426: 2b00 cmp r3, #0
8002428: d106 bne.n 8002438 <HAL_LTDC_Init+0x2c>
{
/* Allocate lock resource and initialize it */
hltdc->Lock = HAL_UNLOCKED;
800242a: 687b ldr r3, [r7, #4]
800242c: 2200 movs r2, #0
800242e: f883 20a0 strb.w r2, [r3, #160] ; 0xa0
/* Init the low level hardware */
HAL_LTDC_MspInit(hltdc);
8002432: 6878 ldr r0, [r7, #4]
8002434: f7fe fd92 bl 8000f5c <HAL_LTDC_MspInit>
}
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
8002438: 687b ldr r3, [r7, #4]
800243a: 2202 movs r2, #2
800243c: f883 20a1 strb.w r2, [r3, #161] ; 0xa1
/* Configure the HS, VS, DE and PC polarity */
hltdc->Instance->GCR &= ~(LTDC_GCR_HSPOL | LTDC_GCR_VSPOL | LTDC_GCR_DEPOL | LTDC_GCR_PCPOL);
8002440: 687b ldr r3, [r7, #4]
8002442: 681b ldr r3, [r3, #0]
8002444: 699a ldr r2, [r3, #24]
8002446: 687b ldr r3, [r7, #4]
8002448: 681b ldr r3, [r3, #0]
800244a: f022 4270 bic.w r2, r2, #4026531840 ; 0xf0000000
800244e: 619a str r2, [r3, #24]
hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \
8002450: 687b ldr r3, [r7, #4]
8002452: 681b ldr r3, [r3, #0]
8002454: 6999 ldr r1, [r3, #24]
8002456: 687b ldr r3, [r7, #4]
8002458: 685a ldr r2, [r3, #4]
800245a: 687b ldr r3, [r7, #4]
800245c: 689b ldr r3, [r3, #8]
800245e: 431a orrs r2, r3
hltdc->Init.DEPolarity | hltdc->Init.PCPolarity);
8002460: 687b ldr r3, [r7, #4]
8002462: 68db ldr r3, [r3, #12]
hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \
8002464: 431a orrs r2, r3
hltdc->Init.DEPolarity | hltdc->Init.PCPolarity);
8002466: 687b ldr r3, [r7, #4]
8002468: 691b ldr r3, [r3, #16]
800246a: 431a orrs r2, r3
hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \
800246c: 687b ldr r3, [r7, #4]
800246e: 681b ldr r3, [r3, #0]
8002470: 430a orrs r2, r1
8002472: 619a str r2, [r3, #24]
/* Set Synchronization size */
hltdc->Instance->SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW);
8002474: 687b ldr r3, [r7, #4]
8002476: 681b ldr r3, [r3, #0]
8002478: 6899 ldr r1, [r3, #8]
800247a: 687b ldr r3, [r7, #4]
800247c: 681a ldr r2, [r3, #0]
800247e: 4b4a ldr r3, [pc, #296] ; (80025a8 <HAL_LTDC_Init+0x19c>)
8002480: 400b ands r3, r1
8002482: 6093 str r3, [r2, #8]
tmp = (hltdc->Init.HorizontalSync << 16U);
8002484: 687b ldr r3, [r7, #4]
8002486: 695b ldr r3, [r3, #20]
8002488: 041b lsls r3, r3, #16
800248a: 60fb str r3, [r7, #12]
hltdc->Instance->SSCR |= (tmp | hltdc->Init.VerticalSync);
800248c: 687b ldr r3, [r7, #4]
800248e: 681b ldr r3, [r3, #0]
8002490: 6899 ldr r1, [r3, #8]
8002492: 687b ldr r3, [r7, #4]
8002494: 699a ldr r2, [r3, #24]
8002496: 68fb ldr r3, [r7, #12]
8002498: 431a orrs r2, r3
800249a: 687b ldr r3, [r7, #4]
800249c: 681b ldr r3, [r3, #0]
800249e: 430a orrs r2, r1
80024a0: 609a str r2, [r3, #8]
/* Set Accumulated Back porch */
hltdc->Instance->BPCR &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP);
80024a2: 687b ldr r3, [r7, #4]
80024a4: 681b ldr r3, [r3, #0]
80024a6: 68d9 ldr r1, [r3, #12]
80024a8: 687b ldr r3, [r7, #4]
80024aa: 681a ldr r2, [r3, #0]
80024ac: 4b3e ldr r3, [pc, #248] ; (80025a8 <HAL_LTDC_Init+0x19c>)
80024ae: 400b ands r3, r1
80024b0: 60d3 str r3, [r2, #12]
tmp = (hltdc->Init.AccumulatedHBP << 16U);
80024b2: 687b ldr r3, [r7, #4]
80024b4: 69db ldr r3, [r3, #28]
80024b6: 041b lsls r3, r3, #16
80024b8: 60fb str r3, [r7, #12]
hltdc->Instance->BPCR |= (tmp | hltdc->Init.AccumulatedVBP);
80024ba: 687b ldr r3, [r7, #4]
80024bc: 681b ldr r3, [r3, #0]
80024be: 68d9 ldr r1, [r3, #12]
80024c0: 687b ldr r3, [r7, #4]
80024c2: 6a1a ldr r2, [r3, #32]
80024c4: 68fb ldr r3, [r7, #12]
80024c6: 431a orrs r2, r3
80024c8: 687b ldr r3, [r7, #4]
80024ca: 681b ldr r3, [r3, #0]
80024cc: 430a orrs r2, r1
80024ce: 60da str r2, [r3, #12]
/* Set Accumulated Active Width */
hltdc->Instance->AWCR &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW);
80024d0: 687b ldr r3, [r7, #4]
80024d2: 681b ldr r3, [r3, #0]
80024d4: 6919 ldr r1, [r3, #16]
80024d6: 687b ldr r3, [r7, #4]
80024d8: 681a ldr r2, [r3, #0]
80024da: 4b33 ldr r3, [pc, #204] ; (80025a8 <HAL_LTDC_Init+0x19c>)
80024dc: 400b ands r3, r1
80024de: 6113 str r3, [r2, #16]
tmp = (hltdc->Init.AccumulatedActiveW << 16U);
80024e0: 687b ldr r3, [r7, #4]
80024e2: 6a5b ldr r3, [r3, #36] ; 0x24
80024e4: 041b lsls r3, r3, #16
80024e6: 60fb str r3, [r7, #12]
hltdc->Instance->AWCR |= (tmp | hltdc->Init.AccumulatedActiveH);
80024e8: 687b ldr r3, [r7, #4]
80024ea: 681b ldr r3, [r3, #0]
80024ec: 6919 ldr r1, [r3, #16]
80024ee: 687b ldr r3, [r7, #4]
80024f0: 6a9a ldr r2, [r3, #40] ; 0x28
80024f2: 68fb ldr r3, [r7, #12]
80024f4: 431a orrs r2, r3
80024f6: 687b ldr r3, [r7, #4]
80024f8: 681b ldr r3, [r3, #0]
80024fa: 430a orrs r2, r1
80024fc: 611a str r2, [r3, #16]
/* Set Total Width */
hltdc->Instance->TWCR &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW);
80024fe: 687b ldr r3, [r7, #4]
8002500: 681b ldr r3, [r3, #0]
8002502: 6959 ldr r1, [r3, #20]
8002504: 687b ldr r3, [r7, #4]
8002506: 681a ldr r2, [r3, #0]
8002508: 4b27 ldr r3, [pc, #156] ; (80025a8 <HAL_LTDC_Init+0x19c>)
800250a: 400b ands r3, r1
800250c: 6153 str r3, [r2, #20]
tmp = (hltdc->Init.TotalWidth << 16U);
800250e: 687b ldr r3, [r7, #4]
8002510: 6adb ldr r3, [r3, #44] ; 0x2c
8002512: 041b lsls r3, r3, #16
8002514: 60fb str r3, [r7, #12]
hltdc->Instance->TWCR |= (tmp | hltdc->Init.TotalHeigh);
8002516: 687b ldr r3, [r7, #4]
8002518: 681b ldr r3, [r3, #0]
800251a: 6959 ldr r1, [r3, #20]
800251c: 687b ldr r3, [r7, #4]
800251e: 6b1a ldr r2, [r3, #48] ; 0x30
8002520: 68fb ldr r3, [r7, #12]
8002522: 431a orrs r2, r3
8002524: 687b ldr r3, [r7, #4]
8002526: 681b ldr r3, [r3, #0]
8002528: 430a orrs r2, r1
800252a: 615a str r2, [r3, #20]
/* Set the background color value */
tmp = ((uint32_t)(hltdc->Init.Backcolor.Green) << 8U);
800252c: 687b ldr r3, [r7, #4]
800252e: f893 3035 ldrb.w r3, [r3, #53] ; 0x35
8002532: 021b lsls r3, r3, #8
8002534: 60fb str r3, [r7, #12]
tmp1 = ((uint32_t)(hltdc->Init.Backcolor.Red) << 16U);
8002536: 687b ldr r3, [r7, #4]
8002538: f893 3036 ldrb.w r3, [r3, #54] ; 0x36
800253c: 041b lsls r3, r3, #16
800253e: 60bb str r3, [r7, #8]
hltdc->Instance->BCCR &= ~(LTDC_BCCR_BCBLUE | LTDC_BCCR_BCGREEN | LTDC_BCCR_BCRED);
8002540: 687b ldr r3, [r7, #4]
8002542: 681b ldr r3, [r3, #0]
8002544: 6ada ldr r2, [r3, #44] ; 0x2c
8002546: 687b ldr r3, [r7, #4]
8002548: 681b ldr r3, [r3, #0]
800254a: f002 427f and.w r2, r2, #4278190080 ; 0xff000000
800254e: 62da str r2, [r3, #44] ; 0x2c
hltdc->Instance->BCCR |= (tmp1 | tmp | hltdc->Init.Backcolor.Blue);
8002550: 687b ldr r3, [r7, #4]
8002552: 681b ldr r3, [r3, #0]
8002554: 6ad9 ldr r1, [r3, #44] ; 0x2c
8002556: 68ba ldr r2, [r7, #8]
8002558: 68fb ldr r3, [r7, #12]
800255a: 4313 orrs r3, r2
800255c: 687a ldr r2, [r7, #4]
800255e: f892 2034 ldrb.w r2, [r2, #52] ; 0x34
8002562: 431a orrs r2, r3
8002564: 687b ldr r3, [r7, #4]
8002566: 681b ldr r3, [r3, #0]
8002568: 430a orrs r2, r1
800256a: 62da str r2, [r3, #44] ; 0x2c
/* Enable the Transfer Error and FIFO underrun interrupts */
__HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_TE | LTDC_IT_FU);
800256c: 687b ldr r3, [r7, #4]
800256e: 681b ldr r3, [r3, #0]
8002570: 6b5a ldr r2, [r3, #52] ; 0x34
8002572: 687b ldr r3, [r7, #4]
8002574: 681b ldr r3, [r3, #0]
8002576: f042 0206 orr.w r2, r2, #6
800257a: 635a str r2, [r3, #52] ; 0x34
/* Enable LTDC by setting LTDCEN bit */
__HAL_LTDC_ENABLE(hltdc);
800257c: 687b ldr r3, [r7, #4]
800257e: 681b ldr r3, [r3, #0]
8002580: 699a ldr r2, [r3, #24]
8002582: 687b ldr r3, [r7, #4]
8002584: 681b ldr r3, [r3, #0]
8002586: f042 0201 orr.w r2, r2, #1
800258a: 619a str r2, [r3, #24]
/* Initialize the error code */
hltdc->ErrorCode = HAL_LTDC_ERROR_NONE;
800258c: 687b ldr r3, [r7, #4]
800258e: 2200 movs r2, #0
8002590: f8c3 20a4 str.w r2, [r3, #164] ; 0xa4
/* Initialize the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
8002594: 687b ldr r3, [r7, #4]
8002596: 2201 movs r2, #1
8002598: f883 20a1 strb.w r2, [r3, #161] ; 0xa1
return HAL_OK;
800259c: 2300 movs r3, #0
}
800259e: 4618 mov r0, r3
80025a0: 3710 adds r7, #16
80025a2: 46bd mov sp, r7
80025a4: bd80 pop {r7, pc}
80025a6: bf00 nop
80025a8: f000f800 .word 0xf000f800
080025ac <HAL_LTDC_IRQHandler>:
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval HAL status
*/
void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc)
{
80025ac: b580 push {r7, lr}
80025ae: b084 sub sp, #16
80025b0: af00 add r7, sp, #0
80025b2: 6078 str r0, [r7, #4]
uint32_t isrflags = READ_REG(hltdc->Instance->ISR);
80025b4: 687b ldr r3, [r7, #4]
80025b6: 681b ldr r3, [r3, #0]
80025b8: 6b9b ldr r3, [r3, #56] ; 0x38
80025ba: 60fb str r3, [r7, #12]
uint32_t itsources = READ_REG(hltdc->Instance->IER);
80025bc: 687b ldr r3, [r7, #4]
80025be: 681b ldr r3, [r3, #0]
80025c0: 6b5b ldr r3, [r3, #52] ; 0x34
80025c2: 60bb str r3, [r7, #8]
/* Transfer Error Interrupt management ***************************************/
if (((isrflags & LTDC_ISR_TERRIF) != 0U) && ((itsources & LTDC_IER_TERRIE) != 0U))
80025c4: 68fb ldr r3, [r7, #12]
80025c6: f003 0304 and.w r3, r3, #4
80025ca: 2b00 cmp r3, #0
80025cc: d023 beq.n 8002616 <HAL_LTDC_IRQHandler+0x6a>
80025ce: 68bb ldr r3, [r7, #8]
80025d0: f003 0304 and.w r3, r3, #4
80025d4: 2b00 cmp r3, #0
80025d6: d01e beq.n 8002616 <HAL_LTDC_IRQHandler+0x6a>
{
/* Disable the transfer Error interrupt */
__HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_TE);
80025d8: 687b ldr r3, [r7, #4]
80025da: 681b ldr r3, [r3, #0]
80025dc: 6b5a ldr r2, [r3, #52] ; 0x34
80025de: 687b ldr r3, [r7, #4]
80025e0: 681b ldr r3, [r3, #0]
80025e2: f022 0204 bic.w r2, r2, #4
80025e6: 635a str r2, [r3, #52] ; 0x34
/* Clear the transfer error flag */
__HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_TE);
80025e8: 687b ldr r3, [r7, #4]
80025ea: 681b ldr r3, [r3, #0]
80025ec: 2204 movs r2, #4
80025ee: 63da str r2, [r3, #60] ; 0x3c
/* Update error code */
hltdc->ErrorCode |= HAL_LTDC_ERROR_TE;
80025f0: 687b ldr r3, [r7, #4]
80025f2: f8d3 30a4 ldr.w r3, [r3, #164] ; 0xa4
80025f6: f043 0201 orr.w r2, r3, #1
80025fa: 687b ldr r3, [r7, #4]
80025fc: f8c3 20a4 str.w r2, [r3, #164] ; 0xa4
/* Change LTDC state */
hltdc->State = HAL_LTDC_STATE_ERROR;
8002600: 687b ldr r3, [r7, #4]
8002602: 2204 movs r2, #4
8002604: f883 20a1 strb.w r2, [r3, #161] ; 0xa1
/* Process unlocked */
__HAL_UNLOCK(hltdc);
8002608: 687b ldr r3, [r7, #4]
800260a: 2200 movs r2, #0
800260c: f883 20a0 strb.w r2, [r3, #160] ; 0xa0
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
hltdc->ErrorCallback(hltdc);
#else
/* Call legacy error callback*/
HAL_LTDC_ErrorCallback(hltdc);
8002610: 6878 ldr r0, [r7, #4]
8002612: f000 f86f bl 80026f4 <HAL_LTDC_ErrorCallback>
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
}
/* FIFO underrun Interrupt management ***************************************/
if (((isrflags & LTDC_ISR_FUIF) != 0U) && ((itsources & LTDC_IER_FUIE) != 0U))
8002616: 68fb ldr r3, [r7, #12]
8002618: f003 0302 and.w r3, r3, #2
800261c: 2b00 cmp r3, #0
800261e: d023 beq.n 8002668 <HAL_LTDC_IRQHandler+0xbc>
8002620: 68bb ldr r3, [r7, #8]
8002622: f003 0302 and.w r3, r3, #2
8002626: 2b00 cmp r3, #0
8002628: d01e beq.n 8002668 <HAL_LTDC_IRQHandler+0xbc>
{
/* Disable the FIFO underrun interrupt */
__HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_FU);
800262a: 687b ldr r3, [r7, #4]
800262c: 681b ldr r3, [r3, #0]
800262e: 6b5a ldr r2, [r3, #52] ; 0x34
8002630: 687b ldr r3, [r7, #4]
8002632: 681b ldr r3, [r3, #0]
8002634: f022 0202 bic.w r2, r2, #2
8002638: 635a str r2, [r3, #52] ; 0x34
/* Clear the FIFO underrun flag */
__HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_FU);
800263a: 687b ldr r3, [r7, #4]
800263c: 681b ldr r3, [r3, #0]
800263e: 2202 movs r2, #2
8002640: 63da str r2, [r3, #60] ; 0x3c
/* Update error code */
hltdc->ErrorCode |= HAL_LTDC_ERROR_FU;
8002642: 687b ldr r3, [r7, #4]
8002644: f8d3 30a4 ldr.w r3, [r3, #164] ; 0xa4
8002648: f043 0202 orr.w r2, r3, #2
800264c: 687b ldr r3, [r7, #4]
800264e: f8c3 20a4 str.w r2, [r3, #164] ; 0xa4
/* Change LTDC state */
hltdc->State = HAL_LTDC_STATE_ERROR;
8002652: 687b ldr r3, [r7, #4]
8002654: 2204 movs r2, #4
8002656: f883 20a1 strb.w r2, [r3, #161] ; 0xa1
/* Process unlocked */
__HAL_UNLOCK(hltdc);
800265a: 687b ldr r3, [r7, #4]
800265c: 2200 movs r2, #0
800265e: f883 20a0 strb.w r2, [r3, #160] ; 0xa0
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
hltdc->ErrorCallback(hltdc);
#else
/* Call legacy error callback*/
HAL_LTDC_ErrorCallback(hltdc);
8002662: 6878 ldr r0, [r7, #4]
8002664: f000 f846 bl 80026f4 <HAL_LTDC_ErrorCallback>
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
}
/* Line Interrupt management ************************************************/
if (((isrflags & LTDC_ISR_LIF) != 0U) && ((itsources & LTDC_IER_LIE) != 0U))
8002668: 68fb ldr r3, [r7, #12]
800266a: f003 0301 and.w r3, r3, #1
800266e: 2b00 cmp r3, #0
8002670: d01b beq.n 80026aa <HAL_LTDC_IRQHandler+0xfe>
8002672: 68bb ldr r3, [r7, #8]
8002674: f003 0301 and.w r3, r3, #1
8002678: 2b00 cmp r3, #0
800267a: d016 beq.n 80026aa <HAL_LTDC_IRQHandler+0xfe>
{
/* Disable the Line interrupt */
__HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI);
800267c: 687b ldr r3, [r7, #4]
800267e: 681b ldr r3, [r3, #0]
8002680: 6b5a ldr r2, [r3, #52] ; 0x34
8002682: 687b ldr r3, [r7, #4]
8002684: 681b ldr r3, [r3, #0]
8002686: f022 0201 bic.w r2, r2, #1
800268a: 635a str r2, [r3, #52] ; 0x34
/* Clear the Line interrupt flag */
__HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_LI);
800268c: 687b ldr r3, [r7, #4]
800268e: 681b ldr r3, [r3, #0]
8002690: 2201 movs r2, #1
8002692: 63da str r2, [r3, #60] ; 0x3c
/* Change LTDC state */
hltdc->State = HAL_LTDC_STATE_READY;
8002694: 687b ldr r3, [r7, #4]
8002696: 2201 movs r2, #1
8002698: f883 20a1 strb.w r2, [r3, #161] ; 0xa1
/* Process unlocked */
__HAL_UNLOCK(hltdc);
800269c: 687b ldr r3, [r7, #4]
800269e: 2200 movs r2, #0
80026a0: f883 20a0 strb.w r2, [r3, #160] ; 0xa0
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
/*Call registered Line Event callback */
hltdc->LineEventCallback(hltdc);
#else
/*Call Legacy Line Event callback */
HAL_LTDC_LineEventCallback(hltdc);
80026a4: 6878 ldr r0, [r7, #4]
80026a6: f000 f82f bl 8002708 <HAL_LTDC_LineEventCallback>
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
}
/* Register reload Interrupt management ***************************************/
if (((isrflags & LTDC_ISR_RRIF) != 0U) && ((itsources & LTDC_IER_RRIE) != 0U))
80026aa: 68fb ldr r3, [r7, #12]
80026ac: f003 0308 and.w r3, r3, #8
80026b0: 2b00 cmp r3, #0
80026b2: d01b beq.n 80026ec <HAL_LTDC_IRQHandler+0x140>
80026b4: 68bb ldr r3, [r7, #8]
80026b6: f003 0308 and.w r3, r3, #8
80026ba: 2b00 cmp r3, #0
80026bc: d016 beq.n 80026ec <HAL_LTDC_IRQHandler+0x140>
{
/* Disable the register reload interrupt */
__HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_RR);
80026be: 687b ldr r3, [r7, #4]
80026c0: 681b ldr r3, [r3, #0]
80026c2: 6b5a ldr r2, [r3, #52] ; 0x34
80026c4: 687b ldr r3, [r7, #4]
80026c6: 681b ldr r3, [r3, #0]
80026c8: f022 0208 bic.w r2, r2, #8
80026cc: 635a str r2, [r3, #52] ; 0x34
/* Clear the register reload flag */
__HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_RR);
80026ce: 687b ldr r3, [r7, #4]
80026d0: 681b ldr r3, [r3, #0]
80026d2: 2208 movs r2, #8
80026d4: 63da str r2, [r3, #60] ; 0x3c
/* Change LTDC state */
hltdc->State = HAL_LTDC_STATE_READY;
80026d6: 687b ldr r3, [r7, #4]
80026d8: 2201 movs r2, #1
80026da: f883 20a1 strb.w r2, [r3, #161] ; 0xa1
/* Process unlocked */
__HAL_UNLOCK(hltdc);
80026de: 687b ldr r3, [r7, #4]
80026e0: 2200 movs r2, #0
80026e2: f883 20a0 strb.w r2, [r3, #160] ; 0xa0
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
/*Call registered reload Event callback */
hltdc->ReloadEventCallback(hltdc);
#else
/*Call Legacy Reload Event callback */
HAL_LTDC_ReloadEventCallback(hltdc);
80026e6: 6878 ldr r0, [r7, #4]
80026e8: f000 f818 bl 800271c <HAL_LTDC_ReloadEventCallback>
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
}
}
80026ec: bf00 nop
80026ee: 3710 adds r7, #16
80026f0: 46bd mov sp, r7
80026f2: bd80 pop {r7, pc}
080026f4 <HAL_LTDC_ErrorCallback>:
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval None
*/
__weak void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc)
{
80026f4: b480 push {r7}
80026f6: b083 sub sp, #12
80026f8: af00 add r7, sp, #0
80026fa: 6078 str r0, [r7, #4]
UNUSED(hltdc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_LTDC_ErrorCallback could be implemented in the user file
*/
}
80026fc: bf00 nop
80026fe: 370c adds r7, #12
8002700: 46bd mov sp, r7
8002702: f85d 7b04 ldr.w r7, [sp], #4
8002706: 4770 bx lr
08002708 <HAL_LTDC_LineEventCallback>:
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval None
*/
__weak void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc)
{
8002708: b480 push {r7}
800270a: b083 sub sp, #12
800270c: af00 add r7, sp, #0
800270e: 6078 str r0, [r7, #4]
UNUSED(hltdc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_LTDC_LineEventCallback could be implemented in the user file
*/
}
8002710: bf00 nop
8002712: 370c adds r7, #12
8002714: 46bd mov sp, r7
8002716: f85d 7b04 ldr.w r7, [sp], #4
800271a: 4770 bx lr
0800271c <HAL_LTDC_ReloadEventCallback>:
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval None
*/
__weak void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc)
{
800271c: b480 push {r7}
800271e: b083 sub sp, #12
8002720: af00 add r7, sp, #0
8002722: 6078 str r0, [r7, #4]
UNUSED(hltdc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_LTDC_ReloadEvenCallback could be implemented in the user file
*/
}
8002724: bf00 nop
8002726: 370c adds r7, #12
8002728: 46bd mov sp, r7
800272a: f85d 7b04 ldr.w r7, [sp], #4
800272e: 4770 bx lr
08002730 <HAL_LTDC_ConfigLayer>:
* This parameter can be one of the following values:
* LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
{
8002730: b5b0 push {r4, r5, r7, lr}
8002732: b084 sub sp, #16
8002734: af00 add r7, sp, #0
8002736: 60f8 str r0, [r7, #12]
8002738: 60b9 str r1, [r7, #8]
800273a: 607a str r2, [r7, #4]
assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2));
assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth));
assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight));
/* Process locked */
__HAL_LOCK(hltdc);
800273c: 68fb ldr r3, [r7, #12]
800273e: f893 30a0 ldrb.w r3, [r3, #160] ; 0xa0
8002742: 2b01 cmp r3, #1
8002744: d101 bne.n 800274a <HAL_LTDC_ConfigLayer+0x1a>
8002746: 2302 movs r3, #2
8002748: e02c b.n 80027a4 <HAL_LTDC_ConfigLayer+0x74>
800274a: 68fb ldr r3, [r7, #12]
800274c: 2201 movs r2, #1
800274e: f883 20a0 strb.w r2, [r3, #160] ; 0xa0
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
8002752: 68fb ldr r3, [r7, #12]
8002754: 2202 movs r2, #2
8002756: f883 20a1 strb.w r2, [r3, #161] ; 0xa1
/* Copy new layer configuration into handle structure */
hltdc->LayerCfg[LayerIdx] = *pLayerCfg;
800275a: 68fa ldr r2, [r7, #12]
800275c: 687b ldr r3, [r7, #4]
800275e: 2134 movs r1, #52 ; 0x34
8002760: fb01 f303 mul.w r3, r1, r3
8002764: 4413 add r3, r2
8002766: f103 0238 add.w r2, r3, #56 ; 0x38
800276a: 68bb ldr r3, [r7, #8]
800276c: 4614 mov r4, r2
800276e: 461d mov r5, r3
8002770: cd0f ldmia r5!, {r0, r1, r2, r3}
8002772: c40f stmia r4!, {r0, r1, r2, r3}
8002774: cd0f ldmia r5!, {r0, r1, r2, r3}
8002776: c40f stmia r4!, {r0, r1, r2, r3}
8002778: cd0f ldmia r5!, {r0, r1, r2, r3}
800277a: c40f stmia r4!, {r0, r1, r2, r3}
800277c: 682b ldr r3, [r5, #0]
800277e: 6023 str r3, [r4, #0]
/* Configure the LTDC Layer */
LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
8002780: 687a ldr r2, [r7, #4]
8002782: 68b9 ldr r1, [r7, #8]
8002784: 68f8 ldr r0, [r7, #12]
8002786: f000 f811 bl 80027ac <LTDC_SetConfig>
/* Set the Immediate Reload type */
hltdc->Instance->SRCR = LTDC_SRCR_IMR;
800278a: 68fb ldr r3, [r7, #12]
800278c: 681b ldr r3, [r3, #0]
800278e: 2201 movs r2, #1
8002790: 625a str r2, [r3, #36] ; 0x24
/* Initialize the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
8002792: 68fb ldr r3, [r7, #12]
8002794: 2201 movs r2, #1
8002796: f883 20a1 strb.w r2, [r3, #161] ; 0xa1
/* Process unlocked */
__HAL_UNLOCK(hltdc);
800279a: 68fb ldr r3, [r7, #12]
800279c: 2200 movs r2, #0
800279e: f883 20a0 strb.w r2, [r3, #160] ; 0xa0
return HAL_OK;
80027a2: 2300 movs r3, #0
}
80027a4: 4618 mov r0, r3
80027a6: 3710 adds r7, #16
80027a8: 46bd mov sp, r7
80027aa: bdb0 pop {r4, r5, r7, pc}
080027ac <LTDC_SetConfig>:
* @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval None
*/
static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
{
80027ac: b480 push {r7}
80027ae: b089 sub sp, #36 ; 0x24
80027b0: af00 add r7, sp, #0
80027b2: 60f8 str r0, [r7, #12]
80027b4: 60b9 str r1, [r7, #8]
80027b6: 607a str r2, [r7, #4]
uint32_t tmp;
uint32_t tmp1;
uint32_t tmp2;
/* Configure the horizontal start and stop position */
tmp = ((pLayerCfg->WindowX1 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U)) << 16U);
80027b8: 68bb ldr r3, [r7, #8]
80027ba: 685a ldr r2, [r3, #4]
80027bc: 68fb ldr r3, [r7, #12]
80027be: 681b ldr r3, [r3, #0]
80027c0: 68db ldr r3, [r3, #12]
80027c2: 0c1b lsrs r3, r3, #16
80027c4: f3c3 030b ubfx r3, r3, #0, #12
80027c8: 4413 add r3, r2
80027ca: 041b lsls r3, r3, #16
80027cc: 61fb str r3, [r7, #28]
LTDC_LAYER(hltdc, LayerIdx)->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS);
80027ce: 68fb ldr r3, [r7, #12]
80027d0: 681b ldr r3, [r3, #0]
80027d2: 461a mov r2, r3
80027d4: 687b ldr r3, [r7, #4]
80027d6: 01db lsls r3, r3, #7
80027d8: 4413 add r3, r2
80027da: 3384 adds r3, #132 ; 0x84
80027dc: 685b ldr r3, [r3, #4]
80027de: 68fa ldr r2, [r7, #12]
80027e0: 6812 ldr r2, [r2, #0]
80027e2: 4611 mov r1, r2
80027e4: 687a ldr r2, [r7, #4]
80027e6: 01d2 lsls r2, r2, #7
80027e8: 440a add r2, r1
80027ea: 3284 adds r2, #132 ; 0x84
80027ec: f403 4370 and.w r3, r3, #61440 ; 0xf000
80027f0: 6053 str r3, [r2, #4]
LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp);
80027f2: 68bb ldr r3, [r7, #8]
80027f4: 681a ldr r2, [r3, #0]
80027f6: 68fb ldr r3, [r7, #12]
80027f8: 681b ldr r3, [r3, #0]
80027fa: 68db ldr r3, [r3, #12]
80027fc: 0c1b lsrs r3, r3, #16
80027fe: f3c3 030b ubfx r3, r3, #0, #12
8002802: 4413 add r3, r2
8002804: 1c5a adds r2, r3, #1
8002806: 68fb ldr r3, [r7, #12]
8002808: 681b ldr r3, [r3, #0]
800280a: 4619 mov r1, r3
800280c: 687b ldr r3, [r7, #4]
800280e: 01db lsls r3, r3, #7
8002810: 440b add r3, r1
8002812: 3384 adds r3, #132 ; 0x84
8002814: 4619 mov r1, r3
8002816: 69fb ldr r3, [r7, #28]
8002818: 4313 orrs r3, r2
800281a: 604b str r3, [r1, #4]
/* Configure the vertical start and stop position */
tmp = ((pLayerCfg->WindowY1 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP)) << 16U);
800281c: 68bb ldr r3, [r7, #8]
800281e: 68da ldr r2, [r3, #12]
8002820: 68fb ldr r3, [r7, #12]
8002822: 681b ldr r3, [r3, #0]
8002824: 68db ldr r3, [r3, #12]
8002826: f3c3 030a ubfx r3, r3, #0, #11
800282a: 4413 add r3, r2
800282c: 041b lsls r3, r3, #16
800282e: 61fb str r3, [r7, #28]
LTDC_LAYER(hltdc, LayerIdx)->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS);
8002830: 68fb ldr r3, [r7, #12]
8002832: 681b ldr r3, [r3, #0]
8002834: 461a mov r2, r3
8002836: 687b ldr r3, [r7, #4]
8002838: 01db lsls r3, r3, #7
800283a: 4413 add r3, r2
800283c: 3384 adds r3, #132 ; 0x84
800283e: 689b ldr r3, [r3, #8]
8002840: 68fa ldr r2, [r7, #12]
8002842: 6812 ldr r2, [r2, #0]
8002844: 4611 mov r1, r2
8002846: 687a ldr r2, [r7, #4]
8002848: 01d2 lsls r2, r2, #7
800284a: 440a add r2, r1
800284c: 3284 adds r2, #132 ; 0x84
800284e: f403 4370 and.w r3, r3, #61440 ; 0xf000
8002852: 6093 str r3, [r2, #8]
LTDC_LAYER(hltdc, LayerIdx)->WVPCR = ((pLayerCfg->WindowY0 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP) + 1U) | tmp);
8002854: 68bb ldr r3, [r7, #8]
8002856: 689a ldr r2, [r3, #8]
8002858: 68fb ldr r3, [r7, #12]
800285a: 681b ldr r3, [r3, #0]
800285c: 68db ldr r3, [r3, #12]
800285e: f3c3 030a ubfx r3, r3, #0, #11
8002862: 4413 add r3, r2
8002864: 1c5a adds r2, r3, #1
8002866: 68fb ldr r3, [r7, #12]
8002868: 681b ldr r3, [r3, #0]
800286a: 4619 mov r1, r3
800286c: 687b ldr r3, [r7, #4]
800286e: 01db lsls r3, r3, #7
8002870: 440b add r3, r1
8002872: 3384 adds r3, #132 ; 0x84
8002874: 4619 mov r1, r3
8002876: 69fb ldr r3, [r7, #28]
8002878: 4313 orrs r3, r2
800287a: 608b str r3, [r1, #8]
/* Specifies the pixel format */
LTDC_LAYER(hltdc, LayerIdx)->PFCR &= ~(LTDC_LxPFCR_PF);
800287c: 68fb ldr r3, [r7, #12]
800287e: 681b ldr r3, [r3, #0]
8002880: 461a mov r2, r3
8002882: 687b ldr r3, [r7, #4]
8002884: 01db lsls r3, r3, #7
8002886: 4413 add r3, r2
8002888: 3384 adds r3, #132 ; 0x84
800288a: 691b ldr r3, [r3, #16]
800288c: 68fa ldr r2, [r7, #12]
800288e: 6812 ldr r2, [r2, #0]
8002890: 4611 mov r1, r2
8002892: 687a ldr r2, [r7, #4]
8002894: 01d2 lsls r2, r2, #7
8002896: 440a add r2, r1
8002898: 3284 adds r2, #132 ; 0x84
800289a: f023 0307 bic.w r3, r3, #7
800289e: 6113 str r3, [r2, #16]
LTDC_LAYER(hltdc, LayerIdx)->PFCR = (pLayerCfg->PixelFormat);
80028a0: 68fb ldr r3, [r7, #12]
80028a2: 681b ldr r3, [r3, #0]
80028a4: 461a mov r2, r3
80028a6: 687b ldr r3, [r7, #4]
80028a8: 01db lsls r3, r3, #7
80028aa: 4413 add r3, r2
80028ac: 3384 adds r3, #132 ; 0x84
80028ae: 461a mov r2, r3
80028b0: 68bb ldr r3, [r7, #8]
80028b2: 691b ldr r3, [r3, #16]
80028b4: 6113 str r3, [r2, #16]
/* Configure the default color values */
tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8U);
80028b6: 68bb ldr r3, [r7, #8]
80028b8: f893 3031 ldrb.w r3, [r3, #49] ; 0x31
80028bc: 021b lsls r3, r3, #8
80028be: 61fb str r3, [r7, #28]
tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16U);
80028c0: 68bb ldr r3, [r7, #8]
80028c2: f893 3032 ldrb.w r3, [r3, #50] ; 0x32
80028c6: 041b lsls r3, r3, #16
80028c8: 61bb str r3, [r7, #24]
tmp2 = (pLayerCfg->Alpha0 << 24U);
80028ca: 68bb ldr r3, [r7, #8]
80028cc: 699b ldr r3, [r3, #24]
80028ce: 061b lsls r3, r3, #24
80028d0: 617b str r3, [r7, #20]
LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | LTDC_LxDCCR_DCALPHA);
80028d2: 68fb ldr r3, [r7, #12]
80028d4: 681b ldr r3, [r3, #0]
80028d6: 461a mov r2, r3
80028d8: 687b ldr r3, [r7, #4]
80028da: 01db lsls r3, r3, #7
80028dc: 4413 add r3, r2
80028de: 3384 adds r3, #132 ; 0x84
80028e0: 699b ldr r3, [r3, #24]
80028e2: 68fb ldr r3, [r7, #12]
80028e4: 681b ldr r3, [r3, #0]
80028e6: 461a mov r2, r3
80028e8: 687b ldr r3, [r7, #4]
80028ea: 01db lsls r3, r3, #7
80028ec: 4413 add r3, r2
80028ee: 3384 adds r3, #132 ; 0x84
80028f0: 461a mov r2, r3
80028f2: 2300 movs r3, #0
80028f4: 6193 str r3, [r2, #24]
LTDC_LAYER(hltdc, LayerIdx)->DCCR = (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2);
80028f6: 68bb ldr r3, [r7, #8]
80028f8: f893 3030 ldrb.w r3, [r3, #48] ; 0x30
80028fc: 461a mov r2, r3
80028fe: 69fb ldr r3, [r7, #28]
8002900: 431a orrs r2, r3
8002902: 69bb ldr r3, [r7, #24]
8002904: 431a orrs r2, r3
8002906: 68fb ldr r3, [r7, #12]
8002908: 681b ldr r3, [r3, #0]
800290a: 4619 mov r1, r3
800290c: 687b ldr r3, [r7, #4]
800290e: 01db lsls r3, r3, #7
8002910: 440b add r3, r1
8002912: 3384 adds r3, #132 ; 0x84
8002914: 4619 mov r1, r3
8002916: 697b ldr r3, [r7, #20]
8002918: 4313 orrs r3, r2
800291a: 618b str r3, [r1, #24]
/* Specifies the constant alpha value */
LTDC_LAYER(hltdc, LayerIdx)->CACR &= ~(LTDC_LxCACR_CONSTA);
800291c: 68fb ldr r3, [r7, #12]
800291e: 681b ldr r3, [r3, #0]
8002920: 461a mov r2, r3
8002922: 687b ldr r3, [r7, #4]
8002924: 01db lsls r3, r3, #7
8002926: 4413 add r3, r2
8002928: 3384 adds r3, #132 ; 0x84
800292a: 695b ldr r3, [r3, #20]
800292c: 68fa ldr r2, [r7, #12]
800292e: 6812 ldr r2, [r2, #0]
8002930: 4611 mov r1, r2
8002932: 687a ldr r2, [r7, #4]
8002934: 01d2 lsls r2, r2, #7
8002936: 440a add r2, r1
8002938: 3284 adds r2, #132 ; 0x84
800293a: f023 03ff bic.w r3, r3, #255 ; 0xff
800293e: 6153 str r3, [r2, #20]
LTDC_LAYER(hltdc, LayerIdx)->CACR = (pLayerCfg->Alpha);
8002940: 68fb ldr r3, [r7, #12]
8002942: 681b ldr r3, [r3, #0]
8002944: 461a mov r2, r3
8002946: 687b ldr r3, [r7, #4]
8002948: 01db lsls r3, r3, #7
800294a: 4413 add r3, r2
800294c: 3384 adds r3, #132 ; 0x84
800294e: 461a mov r2, r3
8002950: 68bb ldr r3, [r7, #8]
8002952: 695b ldr r3, [r3, #20]
8002954: 6153 str r3, [r2, #20]
/* Specifies the blending factors */
LTDC_LAYER(hltdc, LayerIdx)->BFCR &= ~(LTDC_LxBFCR_BF2 | LTDC_LxBFCR_BF1);
8002956: 68fb ldr r3, [r7, #12]
8002958: 681b ldr r3, [r3, #0]
800295a: 461a mov r2, r3
800295c: 687b ldr r3, [r7, #4]
800295e: 01db lsls r3, r3, #7
8002960: 4413 add r3, r2
8002962: 3384 adds r3, #132 ; 0x84
8002964: 69db ldr r3, [r3, #28]
8002966: 68fa ldr r2, [r7, #12]
8002968: 6812 ldr r2, [r2, #0]
800296a: 4611 mov r1, r2
800296c: 687a ldr r2, [r7, #4]
800296e: 01d2 lsls r2, r2, #7
8002970: 440a add r2, r1
8002972: 3284 adds r2, #132 ; 0x84
8002974: f423 63e0 bic.w r3, r3, #1792 ; 0x700
8002978: f023 0307 bic.w r3, r3, #7
800297c: 61d3 str r3, [r2, #28]
LTDC_LAYER(hltdc, LayerIdx)->BFCR = (pLayerCfg->BlendingFactor1 | pLayerCfg->BlendingFactor2);
800297e: 68bb ldr r3, [r7, #8]
8002980: 69da ldr r2, [r3, #28]
8002982: 68bb ldr r3, [r7, #8]
8002984: 6a1b ldr r3, [r3, #32]
8002986: 68f9 ldr r1, [r7, #12]
8002988: 6809 ldr r1, [r1, #0]
800298a: 4608 mov r0, r1
800298c: 6879 ldr r1, [r7, #4]
800298e: 01c9 lsls r1, r1, #7
8002990: 4401 add r1, r0
8002992: 3184 adds r1, #132 ; 0x84
8002994: 4313 orrs r3, r2
8002996: 61cb str r3, [r1, #28]
/* Configure the color frame buffer start address */
LTDC_LAYER(hltdc, LayerIdx)->CFBAR &= ~(LTDC_LxCFBAR_CFBADD);
8002998: 68fb ldr r3, [r7, #12]
800299a: 681b ldr r3, [r3, #0]
800299c: 461a mov r2, r3
800299e: 687b ldr r3, [r7, #4]
80029a0: 01db lsls r3, r3, #7
80029a2: 4413 add r3, r2
80029a4: 3384 adds r3, #132 ; 0x84
80029a6: 6a9b ldr r3, [r3, #40] ; 0x28
80029a8: 68fb ldr r3, [r7, #12]
80029aa: 681b ldr r3, [r3, #0]
80029ac: 461a mov r2, r3
80029ae: 687b ldr r3, [r7, #4]
80029b0: 01db lsls r3, r3, #7
80029b2: 4413 add r3, r2
80029b4: 3384 adds r3, #132 ; 0x84
80029b6: 461a mov r2, r3
80029b8: 2300 movs r3, #0
80029ba: 6293 str r3, [r2, #40] ; 0x28
LTDC_LAYER(hltdc, LayerIdx)->CFBAR = (pLayerCfg->FBStartAdress);
80029bc: 68fb ldr r3, [r7, #12]
80029be: 681b ldr r3, [r3, #0]
80029c0: 461a mov r2, r3
80029c2: 687b ldr r3, [r7, #4]
80029c4: 01db lsls r3, r3, #7
80029c6: 4413 add r3, r2
80029c8: 3384 adds r3, #132 ; 0x84
80029ca: 461a mov r2, r3
80029cc: 68bb ldr r3, [r7, #8]
80029ce: 6a5b ldr r3, [r3, #36] ; 0x24
80029d0: 6293 str r3, [r2, #40] ; 0x28
if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
80029d2: 68bb ldr r3, [r7, #8]
80029d4: 691b ldr r3, [r3, #16]
80029d6: 2b00 cmp r3, #0
80029d8: d102 bne.n 80029e0 <LTDC_SetConfig+0x234>
{
tmp = 4U;
80029da: 2304 movs r3, #4
80029dc: 61fb str r3, [r7, #28]
80029de: e01b b.n 8002a18 <LTDC_SetConfig+0x26c>
}
else if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB888)
80029e0: 68bb ldr r3, [r7, #8]
80029e2: 691b ldr r3, [r3, #16]
80029e4: 2b01 cmp r3, #1
80029e6: d102 bne.n 80029ee <LTDC_SetConfig+0x242>
{
tmp = 3U;
80029e8: 2303 movs r3, #3
80029ea: 61fb str r3, [r7, #28]
80029ec: e014 b.n 8002a18 <LTDC_SetConfig+0x26c>
}
else if ((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
80029ee: 68bb ldr r3, [r7, #8]
80029f0: 691b ldr r3, [r3, #16]
80029f2: 2b04 cmp r3, #4
80029f4: d00b beq.n 8002a0e <LTDC_SetConfig+0x262>
(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \
80029f6: 68bb ldr r3, [r7, #8]
80029f8: 691b ldr r3, [r3, #16]
else if ((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
80029fa: 2b02 cmp r3, #2
80029fc: d007 beq.n 8002a0e <LTDC_SetConfig+0x262>
(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
80029fe: 68bb ldr r3, [r7, #8]
8002a00: 691b ldr r3, [r3, #16]
(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \
8002a02: 2b03 cmp r3, #3
8002a04: d003 beq.n 8002a0e <LTDC_SetConfig+0x262>
(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_AL88))
8002a06: 68bb ldr r3, [r7, #8]
8002a08: 691b ldr r3, [r3, #16]
(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
8002a0a: 2b07 cmp r3, #7
8002a0c: d102 bne.n 8002a14 <LTDC_SetConfig+0x268>
{
tmp = 2U;
8002a0e: 2302 movs r3, #2
8002a10: 61fb str r3, [r7, #28]
8002a12: e001 b.n 8002a18 <LTDC_SetConfig+0x26c>
}
else
{
tmp = 1U;
8002a14: 2301 movs r3, #1
8002a16: 61fb str r3, [r7, #28]
}
/* Configure the color frame buffer pitch in byte */
LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP);
8002a18: 68fb ldr r3, [r7, #12]
8002a1a: 681b ldr r3, [r3, #0]
8002a1c: 461a mov r2, r3
8002a1e: 687b ldr r3, [r7, #4]
8002a20: 01db lsls r3, r3, #7
8002a22: 4413 add r3, r2
8002a24: 3384 adds r3, #132 ; 0x84
8002a26: 6adb ldr r3, [r3, #44] ; 0x2c
8002a28: 68fa ldr r2, [r7, #12]
8002a2a: 6812 ldr r2, [r2, #0]
8002a2c: 4611 mov r1, r2
8002a2e: 687a ldr r2, [r7, #4]
8002a30: 01d2 lsls r2, r2, #7
8002a32: 440a add r2, r1
8002a34: 3284 adds r2, #132 ; 0x84
8002a36: f003 23e0 and.w r3, r3, #3758153728 ; 0xe000e000
8002a3a: 62d3 str r3, [r2, #44] ; 0x2c
LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16U) | (((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp) + 3U));
8002a3c: 68bb ldr r3, [r7, #8]
8002a3e: 6a9b ldr r3, [r3, #40] ; 0x28
8002a40: 69fa ldr r2, [r7, #28]
8002a42: fb02 f303 mul.w r3, r2, r3
8002a46: 041a lsls r2, r3, #16
8002a48: 68bb ldr r3, [r7, #8]
8002a4a: 6859 ldr r1, [r3, #4]
8002a4c: 68bb ldr r3, [r7, #8]
8002a4e: 681b ldr r3, [r3, #0]
8002a50: 1acb subs r3, r1, r3
8002a52: 69f9 ldr r1, [r7, #28]
8002a54: fb01 f303 mul.w r3, r1, r3
8002a58: 3303 adds r3, #3
8002a5a: 68f9 ldr r1, [r7, #12]
8002a5c: 6809 ldr r1, [r1, #0]
8002a5e: 4608 mov r0, r1
8002a60: 6879 ldr r1, [r7, #4]
8002a62: 01c9 lsls r1, r1, #7
8002a64: 4401 add r1, r0
8002a66: 3184 adds r1, #132 ; 0x84
8002a68: 4313 orrs r3, r2
8002a6a: 62cb str r3, [r1, #44] ; 0x2c
/* Configure the frame buffer line number */
LTDC_LAYER(hltdc, LayerIdx)->CFBLNR &= ~(LTDC_LxCFBLNR_CFBLNBR);
8002a6c: 68fb ldr r3, [r7, #12]
8002a6e: 681b ldr r3, [r3, #0]
8002a70: 461a mov r2, r3
8002a72: 687b ldr r3, [r7, #4]
8002a74: 01db lsls r3, r3, #7
8002a76: 4413 add r3, r2
8002a78: 3384 adds r3, #132 ; 0x84
8002a7a: 6b1b ldr r3, [r3, #48] ; 0x30
8002a7c: 68fa ldr r2, [r7, #12]
8002a7e: 6812 ldr r2, [r2, #0]
8002a80: 4611 mov r1, r2
8002a82: 687a ldr r2, [r7, #4]
8002a84: 01d2 lsls r2, r2, #7
8002a86: 440a add r2, r1
8002a88: 3284 adds r2, #132 ; 0x84
8002a8a: f423 63ff bic.w r3, r3, #2040 ; 0x7f8
8002a8e: f023 0307 bic.w r3, r3, #7
8002a92: 6313 str r3, [r2, #48] ; 0x30
LTDC_LAYER(hltdc, LayerIdx)->CFBLNR = (pLayerCfg->ImageHeight);
8002a94: 68fb ldr r3, [r7, #12]
8002a96: 681b ldr r3, [r3, #0]
8002a98: 461a mov r2, r3
8002a9a: 687b ldr r3, [r7, #4]
8002a9c: 01db lsls r3, r3, #7
8002a9e: 4413 add r3, r2
8002aa0: 3384 adds r3, #132 ; 0x84
8002aa2: 461a mov r2, r3
8002aa4: 68bb ldr r3, [r7, #8]
8002aa6: 6adb ldr r3, [r3, #44] ; 0x2c
8002aa8: 6313 str r3, [r2, #48] ; 0x30
/* Enable LTDC_Layer by setting LEN bit */
LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_LEN;
8002aaa: 68fb ldr r3, [r7, #12]
8002aac: 681b ldr r3, [r3, #0]
8002aae: 461a mov r2, r3
8002ab0: 687b ldr r3, [r7, #4]
8002ab2: 01db lsls r3, r3, #7
8002ab4: 4413 add r3, r2
8002ab6: 3384 adds r3, #132 ; 0x84
8002ab8: 681b ldr r3, [r3, #0]
8002aba: 68fa ldr r2, [r7, #12]
8002abc: 6812 ldr r2, [r2, #0]
8002abe: 4611 mov r1, r2
8002ac0: 687a ldr r2, [r7, #4]
8002ac2: 01d2 lsls r2, r2, #7
8002ac4: 440a add r2, r1
8002ac6: 3284 adds r2, #132 ; 0x84
8002ac8: f043 0301 orr.w r3, r3, #1
8002acc: 6013 str r3, [r2, #0]
}
8002ace: bf00 nop
8002ad0: 3724 adds r7, #36 ; 0x24
8002ad2: 46bd mov sp, r7
8002ad4: f85d 7b04 ldr.w r7, [sp], #4
8002ad8: 4770 bx lr
...
08002adc <HAL_RCC_OscConfig>:
* supported by this API. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8002adc: b580 push {r7, lr}
8002ade: b086 sub sp, #24
8002ae0: af00 add r7, sp, #0
8002ae2: 6078 str r0, [r7, #4]
uint32_t tickstart, pll_config;
/* Check Null pointer */
if(RCC_OscInitStruct == NULL)
8002ae4: 687b ldr r3, [r7, #4]
8002ae6: 2b00 cmp r3, #0
8002ae8: d101 bne.n 8002aee <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
8002aea: 2301 movs r3, #1
8002aec: e25b b.n 8002fa6 <HAL_RCC_OscConfig+0x4ca>
}
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
8002aee: 687b ldr r3, [r7, #4]
8002af0: 681b ldr r3, [r3, #0]
8002af2: f003 0301 and.w r3, r3, #1
8002af6: 2b00 cmp r3, #0
8002af8: d075 beq.n 8002be6 <HAL_RCC_OscConfig+0x10a>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
8002afa: 4ba3 ldr r3, [pc, #652] ; (8002d88 <HAL_RCC_OscConfig+0x2ac>)
8002afc: 689b ldr r3, [r3, #8]
8002afe: f003 030c and.w r3, r3, #12
8002b02: 2b04 cmp r3, #4
8002b04: d00c beq.n 8002b20 <HAL_RCC_OscConfig+0x44>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
8002b06: 4ba0 ldr r3, [pc, #640] ; (8002d88 <HAL_RCC_OscConfig+0x2ac>)
8002b08: 689b ldr r3, [r3, #8]
8002b0a: f003 030c and.w r3, r3, #12
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
8002b0e: 2b08 cmp r3, #8
8002b10: d112 bne.n 8002b38 <HAL_RCC_OscConfig+0x5c>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
8002b12: 4b9d ldr r3, [pc, #628] ; (8002d88 <HAL_RCC_OscConfig+0x2ac>)
8002b14: 685b ldr r3, [r3, #4]
8002b16: f403 0380 and.w r3, r3, #4194304 ; 0x400000
8002b1a: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
8002b1e: d10b bne.n 8002b38 <HAL_RCC_OscConfig+0x5c>
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8002b20: 4b99 ldr r3, [pc, #612] ; (8002d88 <HAL_RCC_OscConfig+0x2ac>)
8002b22: 681b ldr r3, [r3, #0]
8002b24: f403 3300 and.w r3, r3, #131072 ; 0x20000
8002b28: 2b00 cmp r3, #0
8002b2a: d05b beq.n 8002be4 <HAL_RCC_OscConfig+0x108>
8002b2c: 687b ldr r3, [r7, #4]
8002b2e: 685b ldr r3, [r3, #4]
8002b30: 2b00 cmp r3, #0
8002b32: d157 bne.n 8002be4 <HAL_RCC_OscConfig+0x108>
{
return HAL_ERROR;
8002b34: 2301 movs r3, #1
8002b36: e236 b.n 8002fa6 <HAL_RCC_OscConfig+0x4ca>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8002b38: 687b ldr r3, [r7, #4]
8002b3a: 685b ldr r3, [r3, #4]
8002b3c: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8002b40: d106 bne.n 8002b50 <HAL_RCC_OscConfig+0x74>
8002b42: 4b91 ldr r3, [pc, #580] ; (8002d88 <HAL_RCC_OscConfig+0x2ac>)
8002b44: 681b ldr r3, [r3, #0]
8002b46: 4a90 ldr r2, [pc, #576] ; (8002d88 <HAL_RCC_OscConfig+0x2ac>)
8002b48: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8002b4c: 6013 str r3, [r2, #0]
8002b4e: e01d b.n 8002b8c <HAL_RCC_OscConfig+0xb0>
8002b50: 687b ldr r3, [r7, #4]
8002b52: 685b ldr r3, [r3, #4]
8002b54: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
8002b58: d10c bne.n 8002b74 <HAL_RCC_OscConfig+0x98>
8002b5a: 4b8b ldr r3, [pc, #556] ; (8002d88 <HAL_RCC_OscConfig+0x2ac>)
8002b5c: 681b ldr r3, [r3, #0]
8002b5e: 4a8a ldr r2, [pc, #552] ; (8002d88 <HAL_RCC_OscConfig+0x2ac>)
8002b60: f443 2380 orr.w r3, r3, #262144 ; 0x40000
8002b64: 6013 str r3, [r2, #0]
8002b66: 4b88 ldr r3, [pc, #544] ; (8002d88 <HAL_RCC_OscConfig+0x2ac>)
8002b68: 681b ldr r3, [r3, #0]
8002b6a: 4a87 ldr r2, [pc, #540] ; (8002d88 <HAL_RCC_OscConfig+0x2ac>)
8002b6c: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8002b70: 6013 str r3, [r2, #0]
8002b72: e00b b.n 8002b8c <HAL_RCC_OscConfig+0xb0>
8002b74: 4b84 ldr r3, [pc, #528] ; (8002d88 <HAL_RCC_OscConfig+0x2ac>)
8002b76: 681b ldr r3, [r3, #0]
8002b78: 4a83 ldr r2, [pc, #524] ; (8002d88 <HAL_RCC_OscConfig+0x2ac>)
8002b7a: f423 3380 bic.w r3, r3, #65536 ; 0x10000
8002b7e: 6013 str r3, [r2, #0]
8002b80: 4b81 ldr r3, [pc, #516] ; (8002d88 <HAL_RCC_OscConfig+0x2ac>)
8002b82: 681b ldr r3, [r3, #0]
8002b84: 4a80 ldr r2, [pc, #512] ; (8002d88 <HAL_RCC_OscConfig+0x2ac>)
8002b86: f423 2380 bic.w r3, r3, #262144 ; 0x40000
8002b8a: 6013 str r3, [r2, #0]
/* Check the HSE State */
if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
8002b8c: 687b ldr r3, [r7, #4]
8002b8e: 685b ldr r3, [r3, #4]
8002b90: 2b00 cmp r3, #0
8002b92: d013 beq.n 8002bbc <HAL_RCC_OscConfig+0xe0>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8002b94: f7fe fdcc bl 8001730 <HAL_GetTick>
8002b98: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8002b9a: e008 b.n 8002bae <HAL_RCC_OscConfig+0xd2>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
8002b9c: f7fe fdc8 bl 8001730 <HAL_GetTick>
8002ba0: 4602 mov r2, r0
8002ba2: 693b ldr r3, [r7, #16]
8002ba4: 1ad3 subs r3, r2, r3
8002ba6: 2b64 cmp r3, #100 ; 0x64
8002ba8: d901 bls.n 8002bae <HAL_RCC_OscConfig+0xd2>
{
return HAL_TIMEOUT;
8002baa: 2303 movs r3, #3
8002bac: e1fb b.n 8002fa6 <HAL_RCC_OscConfig+0x4ca>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8002bae: 4b76 ldr r3, [pc, #472] ; (8002d88 <HAL_RCC_OscConfig+0x2ac>)
8002bb0: 681b ldr r3, [r3, #0]
8002bb2: f403 3300 and.w r3, r3, #131072 ; 0x20000
8002bb6: 2b00 cmp r3, #0
8002bb8: d0f0 beq.n 8002b9c <HAL_RCC_OscConfig+0xc0>
8002bba: e014 b.n 8002be6 <HAL_RCC_OscConfig+0x10a>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8002bbc: f7fe fdb8 bl 8001730 <HAL_GetTick>
8002bc0: 6138 str r0, [r7, #16]
/* Wait till HSE is bypassed or disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8002bc2: e008 b.n 8002bd6 <HAL_RCC_OscConfig+0xfa>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
8002bc4: f7fe fdb4 bl 8001730 <HAL_GetTick>
8002bc8: 4602 mov r2, r0
8002bca: 693b ldr r3, [r7, #16]
8002bcc: 1ad3 subs r3, r2, r3
8002bce: 2b64 cmp r3, #100 ; 0x64
8002bd0: d901 bls.n 8002bd6 <HAL_RCC_OscConfig+0xfa>
{
return HAL_TIMEOUT;
8002bd2: 2303 movs r3, #3
8002bd4: e1e7 b.n 8002fa6 <HAL_RCC_OscConfig+0x4ca>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8002bd6: 4b6c ldr r3, [pc, #432] ; (8002d88 <HAL_RCC_OscConfig+0x2ac>)
8002bd8: 681b ldr r3, [r3, #0]
8002bda: f403 3300 and.w r3, r3, #131072 ; 0x20000
8002bde: 2b00 cmp r3, #0
8002be0: d1f0 bne.n 8002bc4 <HAL_RCC_OscConfig+0xe8>
8002be2: e000 b.n 8002be6 <HAL_RCC_OscConfig+0x10a>
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8002be4: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
8002be6: 687b ldr r3, [r7, #4]
8002be8: 681b ldr r3, [r3, #0]
8002bea: f003 0302 and.w r3, r3, #2
8002bee: 2b00 cmp r3, #0
8002bf0: d063 beq.n 8002cba <HAL_RCC_OscConfig+0x1de>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
8002bf2: 4b65 ldr r3, [pc, #404] ; (8002d88 <HAL_RCC_OscConfig+0x2ac>)
8002bf4: 689b ldr r3, [r3, #8]
8002bf6: f003 030c and.w r3, r3, #12
8002bfa: 2b00 cmp r3, #0
8002bfc: d00b beq.n 8002c16 <HAL_RCC_OscConfig+0x13a>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
8002bfe: 4b62 ldr r3, [pc, #392] ; (8002d88 <HAL_RCC_OscConfig+0x2ac>)
8002c00: 689b ldr r3, [r3, #8]
8002c02: f003 030c and.w r3, r3, #12
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
8002c06: 2b08 cmp r3, #8
8002c08: d11c bne.n 8002c44 <HAL_RCC_OscConfig+0x168>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
8002c0a: 4b5f ldr r3, [pc, #380] ; (8002d88 <HAL_RCC_OscConfig+0x2ac>)
8002c0c: 685b ldr r3, [r3, #4]
8002c0e: f403 0380 and.w r3, r3, #4194304 ; 0x400000
8002c12: 2b00 cmp r3, #0
8002c14: d116 bne.n 8002c44 <HAL_RCC_OscConfig+0x168>
{
/* When HSI is used as system clock it will not disabled */
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8002c16: 4b5c ldr r3, [pc, #368] ; (8002d88 <HAL_RCC_OscConfig+0x2ac>)
8002c18: 681b ldr r3, [r3, #0]
8002c1a: f003 0302 and.w r3, r3, #2
8002c1e: 2b00 cmp r3, #0
8002c20: d005 beq.n 8002c2e <HAL_RCC_OscConfig+0x152>
8002c22: 687b ldr r3, [r7, #4]
8002c24: 68db ldr r3, [r3, #12]
8002c26: 2b01 cmp r3, #1
8002c28: d001 beq.n 8002c2e <HAL_RCC_OscConfig+0x152>
{
return HAL_ERROR;
8002c2a: 2301 movs r3, #1
8002c2c: e1bb b.n 8002fa6 <HAL_RCC_OscConfig+0x4ca>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8002c2e: 4b56 ldr r3, [pc, #344] ; (8002d88 <HAL_RCC_OscConfig+0x2ac>)
8002c30: 681b ldr r3, [r3, #0]
8002c32: f023 02f8 bic.w r2, r3, #248 ; 0xf8
8002c36: 687b ldr r3, [r7, #4]
8002c38: 691b ldr r3, [r3, #16]
8002c3a: 00db lsls r3, r3, #3
8002c3c: 4952 ldr r1, [pc, #328] ; (8002d88 <HAL_RCC_OscConfig+0x2ac>)
8002c3e: 4313 orrs r3, r2
8002c40: 600b str r3, [r1, #0]
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8002c42: e03a b.n 8002cba <HAL_RCC_OscConfig+0x1de>
}
}
else
{
/* Check the HSI State */
if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
8002c44: 687b ldr r3, [r7, #4]
8002c46: 68db ldr r3, [r3, #12]
8002c48: 2b00 cmp r3, #0
8002c4a: d020 beq.n 8002c8e <HAL_RCC_OscConfig+0x1b2>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8002c4c: 4b4f ldr r3, [pc, #316] ; (8002d8c <HAL_RCC_OscConfig+0x2b0>)
8002c4e: 2201 movs r2, #1
8002c50: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002c52: f7fe fd6d bl 8001730 <HAL_GetTick>
8002c56: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8002c58: e008 b.n 8002c6c <HAL_RCC_OscConfig+0x190>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
8002c5a: f7fe fd69 bl 8001730 <HAL_GetTick>
8002c5e: 4602 mov r2, r0
8002c60: 693b ldr r3, [r7, #16]
8002c62: 1ad3 subs r3, r2, r3
8002c64: 2b02 cmp r3, #2
8002c66: d901 bls.n 8002c6c <HAL_RCC_OscConfig+0x190>
{
return HAL_TIMEOUT;
8002c68: 2303 movs r3, #3
8002c6a: e19c b.n 8002fa6 <HAL_RCC_OscConfig+0x4ca>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8002c6c: 4b46 ldr r3, [pc, #280] ; (8002d88 <HAL_RCC_OscConfig+0x2ac>)
8002c6e: 681b ldr r3, [r3, #0]
8002c70: f003 0302 and.w r3, r3, #2
8002c74: 2b00 cmp r3, #0
8002c76: d0f0 beq.n 8002c5a <HAL_RCC_OscConfig+0x17e>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value. */
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8002c78: 4b43 ldr r3, [pc, #268] ; (8002d88 <HAL_RCC_OscConfig+0x2ac>)
8002c7a: 681b ldr r3, [r3, #0]
8002c7c: f023 02f8 bic.w r2, r3, #248 ; 0xf8
8002c80: 687b ldr r3, [r7, #4]
8002c82: 691b ldr r3, [r3, #16]
8002c84: 00db lsls r3, r3, #3
8002c86: 4940 ldr r1, [pc, #256] ; (8002d88 <HAL_RCC_OscConfig+0x2ac>)
8002c88: 4313 orrs r3, r2
8002c8a: 600b str r3, [r1, #0]
8002c8c: e015 b.n 8002cba <HAL_RCC_OscConfig+0x1de>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
8002c8e: 4b3f ldr r3, [pc, #252] ; (8002d8c <HAL_RCC_OscConfig+0x2b0>)
8002c90: 2200 movs r2, #0
8002c92: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002c94: f7fe fd4c bl 8001730 <HAL_GetTick>
8002c98: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8002c9a: e008 b.n 8002cae <HAL_RCC_OscConfig+0x1d2>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
8002c9c: f7fe fd48 bl 8001730 <HAL_GetTick>
8002ca0: 4602 mov r2, r0
8002ca2: 693b ldr r3, [r7, #16]
8002ca4: 1ad3 subs r3, r2, r3
8002ca6: 2b02 cmp r3, #2
8002ca8: d901 bls.n 8002cae <HAL_RCC_OscConfig+0x1d2>
{
return HAL_TIMEOUT;
8002caa: 2303 movs r3, #3
8002cac: e17b b.n 8002fa6 <HAL_RCC_OscConfig+0x4ca>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8002cae: 4b36 ldr r3, [pc, #216] ; (8002d88 <HAL_RCC_OscConfig+0x2ac>)
8002cb0: 681b ldr r3, [r3, #0]
8002cb2: f003 0302 and.w r3, r3, #2
8002cb6: 2b00 cmp r3, #0
8002cb8: d1f0 bne.n 8002c9c <HAL_RCC_OscConfig+0x1c0>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
8002cba: 687b ldr r3, [r7, #4]
8002cbc: 681b ldr r3, [r3, #0]
8002cbe: f003 0308 and.w r3, r3, #8
8002cc2: 2b00 cmp r3, #0
8002cc4: d030 beq.n 8002d28 <HAL_RCC_OscConfig+0x24c>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
8002cc6: 687b ldr r3, [r7, #4]
8002cc8: 695b ldr r3, [r3, #20]
8002cca: 2b00 cmp r3, #0
8002ccc: d016 beq.n 8002cfc <HAL_RCC_OscConfig+0x220>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8002cce: 4b30 ldr r3, [pc, #192] ; (8002d90 <HAL_RCC_OscConfig+0x2b4>)
8002cd0: 2201 movs r2, #1
8002cd2: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002cd4: f7fe fd2c bl 8001730 <HAL_GetTick>
8002cd8: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8002cda: e008 b.n 8002cee <HAL_RCC_OscConfig+0x212>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
8002cdc: f7fe fd28 bl 8001730 <HAL_GetTick>
8002ce0: 4602 mov r2, r0
8002ce2: 693b ldr r3, [r7, #16]
8002ce4: 1ad3 subs r3, r2, r3
8002ce6: 2b02 cmp r3, #2
8002ce8: d901 bls.n 8002cee <HAL_RCC_OscConfig+0x212>
{
return HAL_TIMEOUT;
8002cea: 2303 movs r3, #3
8002cec: e15b b.n 8002fa6 <HAL_RCC_OscConfig+0x4ca>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8002cee: 4b26 ldr r3, [pc, #152] ; (8002d88 <HAL_RCC_OscConfig+0x2ac>)
8002cf0: 6f5b ldr r3, [r3, #116] ; 0x74
8002cf2: f003 0302 and.w r3, r3, #2
8002cf6: 2b00 cmp r3, #0
8002cf8: d0f0 beq.n 8002cdc <HAL_RCC_OscConfig+0x200>
8002cfa: e015 b.n 8002d28 <HAL_RCC_OscConfig+0x24c>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8002cfc: 4b24 ldr r3, [pc, #144] ; (8002d90 <HAL_RCC_OscConfig+0x2b4>)
8002cfe: 2200 movs r2, #0
8002d00: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8002d02: f7fe fd15 bl 8001730 <HAL_GetTick>
8002d06: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8002d08: e008 b.n 8002d1c <HAL_RCC_OscConfig+0x240>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
8002d0a: f7fe fd11 bl 8001730 <HAL_GetTick>
8002d0e: 4602 mov r2, r0
8002d10: 693b ldr r3, [r7, #16]
8002d12: 1ad3 subs r3, r2, r3
8002d14: 2b02 cmp r3, #2
8002d16: d901 bls.n 8002d1c <HAL_RCC_OscConfig+0x240>
{
return HAL_TIMEOUT;
8002d18: 2303 movs r3, #3
8002d1a: e144 b.n 8002fa6 <HAL_RCC_OscConfig+0x4ca>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8002d1c: 4b1a ldr r3, [pc, #104] ; (8002d88 <HAL_RCC_OscConfig+0x2ac>)
8002d1e: 6f5b ldr r3, [r3, #116] ; 0x74
8002d20: f003 0302 and.w r3, r3, #2
8002d24: 2b00 cmp r3, #0
8002d26: d1f0 bne.n 8002d0a <HAL_RCC_OscConfig+0x22e>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8002d28: 687b ldr r3, [r7, #4]
8002d2a: 681b ldr r3, [r3, #0]
8002d2c: f003 0304 and.w r3, r3, #4
8002d30: 2b00 cmp r3, #0
8002d32: f000 80a0 beq.w 8002e76 <HAL_RCC_OscConfig+0x39a>
{
FlagStatus pwrclkchanged = RESET;
8002d36: 2300 movs r3, #0
8002d38: 75fb strb r3, [r7, #23]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
8002d3a: 4b13 ldr r3, [pc, #76] ; (8002d88 <HAL_RCC_OscConfig+0x2ac>)
8002d3c: 6c1b ldr r3, [r3, #64] ; 0x40
8002d3e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8002d42: 2b00 cmp r3, #0
8002d44: d10f bne.n 8002d66 <HAL_RCC_OscConfig+0x28a>
{
__HAL_RCC_PWR_CLK_ENABLE();
8002d46: 2300 movs r3, #0
8002d48: 60bb str r3, [r7, #8]
8002d4a: 4b0f ldr r3, [pc, #60] ; (8002d88 <HAL_RCC_OscConfig+0x2ac>)
8002d4c: 6c1b ldr r3, [r3, #64] ; 0x40
8002d4e: 4a0e ldr r2, [pc, #56] ; (8002d88 <HAL_RCC_OscConfig+0x2ac>)
8002d50: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8002d54: 6413 str r3, [r2, #64] ; 0x40
8002d56: 4b0c ldr r3, [pc, #48] ; (8002d88 <HAL_RCC_OscConfig+0x2ac>)
8002d58: 6c1b ldr r3, [r3, #64] ; 0x40
8002d5a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8002d5e: 60bb str r3, [r7, #8]
8002d60: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8002d62: 2301 movs r3, #1
8002d64: 75fb strb r3, [r7, #23]
}
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8002d66: 4b0b ldr r3, [pc, #44] ; (8002d94 <HAL_RCC_OscConfig+0x2b8>)
8002d68: 681b ldr r3, [r3, #0]
8002d6a: f403 7380 and.w r3, r3, #256 ; 0x100
8002d6e: 2b00 cmp r3, #0
8002d70: d121 bne.n 8002db6 <HAL_RCC_OscConfig+0x2da>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
8002d72: 4b08 ldr r3, [pc, #32] ; (8002d94 <HAL_RCC_OscConfig+0x2b8>)
8002d74: 681b ldr r3, [r3, #0]
8002d76: 4a07 ldr r2, [pc, #28] ; (8002d94 <HAL_RCC_OscConfig+0x2b8>)
8002d78: f443 7380 orr.w r3, r3, #256 ; 0x100
8002d7c: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8002d7e: f7fe fcd7 bl 8001730 <HAL_GetTick>
8002d82: 6138 str r0, [r7, #16]
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8002d84: e011 b.n 8002daa <HAL_RCC_OscConfig+0x2ce>
8002d86: bf00 nop
8002d88: 40023800 .word 0x40023800
8002d8c: 42470000 .word 0x42470000
8002d90: 42470e80 .word 0x42470e80
8002d94: 40007000 .word 0x40007000
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8002d98: f7fe fcca bl 8001730 <HAL_GetTick>
8002d9c: 4602 mov r2, r0
8002d9e: 693b ldr r3, [r7, #16]
8002da0: 1ad3 subs r3, r2, r3
8002da2: 2b02 cmp r3, #2
8002da4: d901 bls.n 8002daa <HAL_RCC_OscConfig+0x2ce>
{
return HAL_TIMEOUT;
8002da6: 2303 movs r3, #3
8002da8: e0fd b.n 8002fa6 <HAL_RCC_OscConfig+0x4ca>
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8002daa: 4b81 ldr r3, [pc, #516] ; (8002fb0 <HAL_RCC_OscConfig+0x4d4>)
8002dac: 681b ldr r3, [r3, #0]
8002dae: f403 7380 and.w r3, r3, #256 ; 0x100
8002db2: 2b00 cmp r3, #0
8002db4: d0f0 beq.n 8002d98 <HAL_RCC_OscConfig+0x2bc>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8002db6: 687b ldr r3, [r7, #4]
8002db8: 689b ldr r3, [r3, #8]
8002dba: 2b01 cmp r3, #1
8002dbc: d106 bne.n 8002dcc <HAL_RCC_OscConfig+0x2f0>
8002dbe: 4b7d ldr r3, [pc, #500] ; (8002fb4 <HAL_RCC_OscConfig+0x4d8>)
8002dc0: 6f1b ldr r3, [r3, #112] ; 0x70
8002dc2: 4a7c ldr r2, [pc, #496] ; (8002fb4 <HAL_RCC_OscConfig+0x4d8>)
8002dc4: f043 0301 orr.w r3, r3, #1
8002dc8: 6713 str r3, [r2, #112] ; 0x70
8002dca: e01c b.n 8002e06 <HAL_RCC_OscConfig+0x32a>
8002dcc: 687b ldr r3, [r7, #4]
8002dce: 689b ldr r3, [r3, #8]
8002dd0: 2b05 cmp r3, #5
8002dd2: d10c bne.n 8002dee <HAL_RCC_OscConfig+0x312>
8002dd4: 4b77 ldr r3, [pc, #476] ; (8002fb4 <HAL_RCC_OscConfig+0x4d8>)
8002dd6: 6f1b ldr r3, [r3, #112] ; 0x70
8002dd8: 4a76 ldr r2, [pc, #472] ; (8002fb4 <HAL_RCC_OscConfig+0x4d8>)
8002dda: f043 0304 orr.w r3, r3, #4
8002dde: 6713 str r3, [r2, #112] ; 0x70
8002de0: 4b74 ldr r3, [pc, #464] ; (8002fb4 <HAL_RCC_OscConfig+0x4d8>)
8002de2: 6f1b ldr r3, [r3, #112] ; 0x70
8002de4: 4a73 ldr r2, [pc, #460] ; (8002fb4 <HAL_RCC_OscConfig+0x4d8>)
8002de6: f043 0301 orr.w r3, r3, #1
8002dea: 6713 str r3, [r2, #112] ; 0x70
8002dec: e00b b.n 8002e06 <HAL_RCC_OscConfig+0x32a>
8002dee: 4b71 ldr r3, [pc, #452] ; (8002fb4 <HAL_RCC_OscConfig+0x4d8>)
8002df0: 6f1b ldr r3, [r3, #112] ; 0x70
8002df2: 4a70 ldr r2, [pc, #448] ; (8002fb4 <HAL_RCC_OscConfig+0x4d8>)
8002df4: f023 0301 bic.w r3, r3, #1
8002df8: 6713 str r3, [r2, #112] ; 0x70
8002dfa: 4b6e ldr r3, [pc, #440] ; (8002fb4 <HAL_RCC_OscConfig+0x4d8>)
8002dfc: 6f1b ldr r3, [r3, #112] ; 0x70
8002dfe: 4a6d ldr r2, [pc, #436] ; (8002fb4 <HAL_RCC_OscConfig+0x4d8>)
8002e00: f023 0304 bic.w r3, r3, #4
8002e04: 6713 str r3, [r2, #112] ; 0x70
/* Check the LSE State */
if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
8002e06: 687b ldr r3, [r7, #4]
8002e08: 689b ldr r3, [r3, #8]
8002e0a: 2b00 cmp r3, #0
8002e0c: d015 beq.n 8002e3a <HAL_RCC_OscConfig+0x35e>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002e0e: f7fe fc8f bl 8001730 <HAL_GetTick>
8002e12: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8002e14: e00a b.n 8002e2c <HAL_RCC_OscConfig+0x350>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
8002e16: f7fe fc8b bl 8001730 <HAL_GetTick>
8002e1a: 4602 mov r2, r0
8002e1c: 693b ldr r3, [r7, #16]
8002e1e: 1ad3 subs r3, r2, r3
8002e20: f241 3288 movw r2, #5000 ; 0x1388
8002e24: 4293 cmp r3, r2
8002e26: d901 bls.n 8002e2c <HAL_RCC_OscConfig+0x350>
{
return HAL_TIMEOUT;
8002e28: 2303 movs r3, #3
8002e2a: e0bc b.n 8002fa6 <HAL_RCC_OscConfig+0x4ca>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8002e2c: 4b61 ldr r3, [pc, #388] ; (8002fb4 <HAL_RCC_OscConfig+0x4d8>)
8002e2e: 6f1b ldr r3, [r3, #112] ; 0x70
8002e30: f003 0302 and.w r3, r3, #2
8002e34: 2b00 cmp r3, #0
8002e36: d0ee beq.n 8002e16 <HAL_RCC_OscConfig+0x33a>
8002e38: e014 b.n 8002e64 <HAL_RCC_OscConfig+0x388>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8002e3a: f7fe fc79 bl 8001730 <HAL_GetTick>
8002e3e: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8002e40: e00a b.n 8002e58 <HAL_RCC_OscConfig+0x37c>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
8002e42: f7fe fc75 bl 8001730 <HAL_GetTick>
8002e46: 4602 mov r2, r0
8002e48: 693b ldr r3, [r7, #16]
8002e4a: 1ad3 subs r3, r2, r3
8002e4c: f241 3288 movw r2, #5000 ; 0x1388
8002e50: 4293 cmp r3, r2
8002e52: d901 bls.n 8002e58 <HAL_RCC_OscConfig+0x37c>
{
return HAL_TIMEOUT;
8002e54: 2303 movs r3, #3
8002e56: e0a6 b.n 8002fa6 <HAL_RCC_OscConfig+0x4ca>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8002e58: 4b56 ldr r3, [pc, #344] ; (8002fb4 <HAL_RCC_OscConfig+0x4d8>)
8002e5a: 6f1b ldr r3, [r3, #112] ; 0x70
8002e5c: f003 0302 and.w r3, r3, #2
8002e60: 2b00 cmp r3, #0
8002e62: d1ee bne.n 8002e42 <HAL_RCC_OscConfig+0x366>
}
}
}
/* Restore clock configuration if changed */
if(pwrclkchanged == SET)
8002e64: 7dfb ldrb r3, [r7, #23]
8002e66: 2b01 cmp r3, #1
8002e68: d105 bne.n 8002e76 <HAL_RCC_OscConfig+0x39a>
{
__HAL_RCC_PWR_CLK_DISABLE();
8002e6a: 4b52 ldr r3, [pc, #328] ; (8002fb4 <HAL_RCC_OscConfig+0x4d8>)
8002e6c: 6c1b ldr r3, [r3, #64] ; 0x40
8002e6e: 4a51 ldr r2, [pc, #324] ; (8002fb4 <HAL_RCC_OscConfig+0x4d8>)
8002e70: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
8002e74: 6413 str r3, [r2, #64] ; 0x40
}
}
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
8002e76: 687b ldr r3, [r7, #4]
8002e78: 699b ldr r3, [r3, #24]
8002e7a: 2b00 cmp r3, #0
8002e7c: f000 8092 beq.w 8002fa4 <HAL_RCC_OscConfig+0x4c8>
{
/* Check if the PLL is used as system clock or not */
if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
8002e80: 4b4c ldr r3, [pc, #304] ; (8002fb4 <HAL_RCC_OscConfig+0x4d8>)
8002e82: 689b ldr r3, [r3, #8]
8002e84: f003 030c and.w r3, r3, #12
8002e88: 2b08 cmp r3, #8
8002e8a: d05c beq.n 8002f46 <HAL_RCC_OscConfig+0x46a>
{
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
8002e8c: 687b ldr r3, [r7, #4]
8002e8e: 699b ldr r3, [r3, #24]
8002e90: 2b02 cmp r3, #2
8002e92: d141 bne.n 8002f18 <HAL_RCC_OscConfig+0x43c>
assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8002e94: 4b48 ldr r3, [pc, #288] ; (8002fb8 <HAL_RCC_OscConfig+0x4dc>)
8002e96: 2200 movs r2, #0
8002e98: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8002e9a: f7fe fc49 bl 8001730 <HAL_GetTick>
8002e9e: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8002ea0: e008 b.n 8002eb4 <HAL_RCC_OscConfig+0x3d8>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8002ea2: f7fe fc45 bl 8001730 <HAL_GetTick>
8002ea6: 4602 mov r2, r0
8002ea8: 693b ldr r3, [r7, #16]
8002eaa: 1ad3 subs r3, r2, r3
8002eac: 2b02 cmp r3, #2
8002eae: d901 bls.n 8002eb4 <HAL_RCC_OscConfig+0x3d8>
{
return HAL_TIMEOUT;
8002eb0: 2303 movs r3, #3
8002eb2: e078 b.n 8002fa6 <HAL_RCC_OscConfig+0x4ca>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8002eb4: 4b3f ldr r3, [pc, #252] ; (8002fb4 <HAL_RCC_OscConfig+0x4d8>)
8002eb6: 681b ldr r3, [r3, #0]
8002eb8: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8002ebc: 2b00 cmp r3, #0
8002ebe: d1f0 bne.n 8002ea2 <HAL_RCC_OscConfig+0x3c6>
}
}
/* Configure the main PLL clock source, multiplication and division factors. */
WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \
8002ec0: 687b ldr r3, [r7, #4]
8002ec2: 69da ldr r2, [r3, #28]
8002ec4: 687b ldr r3, [r7, #4]
8002ec6: 6a1b ldr r3, [r3, #32]
8002ec8: 431a orrs r2, r3
8002eca: 687b ldr r3, [r7, #4]
8002ecc: 6a5b ldr r3, [r3, #36] ; 0x24
8002ece: 019b lsls r3, r3, #6
8002ed0: 431a orrs r2, r3
8002ed2: 687b ldr r3, [r7, #4]
8002ed4: 6a9b ldr r3, [r3, #40] ; 0x28
8002ed6: 085b lsrs r3, r3, #1
8002ed8: 3b01 subs r3, #1
8002eda: 041b lsls r3, r3, #16
8002edc: 431a orrs r2, r3
8002ede: 687b ldr r3, [r7, #4]
8002ee0: 6adb ldr r3, [r3, #44] ; 0x2c
8002ee2: 061b lsls r3, r3, #24
8002ee4: 4933 ldr r1, [pc, #204] ; (8002fb4 <HAL_RCC_OscConfig+0x4d8>)
8002ee6: 4313 orrs r3, r2
8002ee8: 604b str r3, [r1, #4]
RCC_OscInitStruct->PLL.PLLM | \
(RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \
(((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \
(RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)));
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8002eea: 4b33 ldr r3, [pc, #204] ; (8002fb8 <HAL_RCC_OscConfig+0x4dc>)
8002eec: 2201 movs r2, #1
8002eee: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8002ef0: f7fe fc1e bl 8001730 <HAL_GetTick>
8002ef4: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8002ef6: e008 b.n 8002f0a <HAL_RCC_OscConfig+0x42e>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8002ef8: f7fe fc1a bl 8001730 <HAL_GetTick>
8002efc: 4602 mov r2, r0
8002efe: 693b ldr r3, [r7, #16]
8002f00: 1ad3 subs r3, r2, r3
8002f02: 2b02 cmp r3, #2
8002f04: d901 bls.n 8002f0a <HAL_RCC_OscConfig+0x42e>
{
return HAL_TIMEOUT;
8002f06: 2303 movs r3, #3
8002f08: e04d b.n 8002fa6 <HAL_RCC_OscConfig+0x4ca>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8002f0a: 4b2a ldr r3, [pc, #168] ; (8002fb4 <HAL_RCC_OscConfig+0x4d8>)
8002f0c: 681b ldr r3, [r3, #0]
8002f0e: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8002f12: 2b00 cmp r3, #0
8002f14: d0f0 beq.n 8002ef8 <HAL_RCC_OscConfig+0x41c>
8002f16: e045 b.n 8002fa4 <HAL_RCC_OscConfig+0x4c8>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8002f18: 4b27 ldr r3, [pc, #156] ; (8002fb8 <HAL_RCC_OscConfig+0x4dc>)
8002f1a: 2200 movs r2, #0
8002f1c: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8002f1e: f7fe fc07 bl 8001730 <HAL_GetTick>
8002f22: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8002f24: e008 b.n 8002f38 <HAL_RCC_OscConfig+0x45c>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8002f26: f7fe fc03 bl 8001730 <HAL_GetTick>
8002f2a: 4602 mov r2, r0
8002f2c: 693b ldr r3, [r7, #16]
8002f2e: 1ad3 subs r3, r2, r3
8002f30: 2b02 cmp r3, #2
8002f32: d901 bls.n 8002f38 <HAL_RCC_OscConfig+0x45c>
{
return HAL_TIMEOUT;
8002f34: 2303 movs r3, #3
8002f36: e036 b.n 8002fa6 <HAL_RCC_OscConfig+0x4ca>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8002f38: 4b1e ldr r3, [pc, #120] ; (8002fb4 <HAL_RCC_OscConfig+0x4d8>)
8002f3a: 681b ldr r3, [r3, #0]
8002f3c: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8002f40: 2b00 cmp r3, #0
8002f42: d1f0 bne.n 8002f26 <HAL_RCC_OscConfig+0x44a>
8002f44: e02e b.n 8002fa4 <HAL_RCC_OscConfig+0x4c8>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
8002f46: 687b ldr r3, [r7, #4]
8002f48: 699b ldr r3, [r3, #24]
8002f4a: 2b01 cmp r3, #1
8002f4c: d101 bne.n 8002f52 <HAL_RCC_OscConfig+0x476>
{
return HAL_ERROR;
8002f4e: 2301 movs r3, #1
8002f50: e029 b.n 8002fa6 <HAL_RCC_OscConfig+0x4ca>
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->PLLCFGR;
8002f52: 4b18 ldr r3, [pc, #96] ; (8002fb4 <HAL_RCC_OscConfig+0x4d8>)
8002f54: 685b ldr r3, [r3, #4]
8002f56: 60fb str r3, [r7, #12]
if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8002f58: 68fb ldr r3, [r7, #12]
8002f5a: f403 0280 and.w r2, r3, #4194304 ; 0x400000
8002f5e: 687b ldr r3, [r7, #4]
8002f60: 69db ldr r3, [r3, #28]
8002f62: 429a cmp r2, r3
8002f64: d11c bne.n 8002fa0 <HAL_RCC_OscConfig+0x4c4>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
8002f66: 68fb ldr r3, [r7, #12]
8002f68: f003 023f and.w r2, r3, #63 ; 0x3f
8002f6c: 687b ldr r3, [r7, #4]
8002f6e: 6a1b ldr r3, [r3, #32]
if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8002f70: 429a cmp r2, r3
8002f72: d115 bne.n 8002fa0 <HAL_RCC_OscConfig+0x4c4>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != RCC_OscInitStruct->PLL.PLLN) ||
8002f74: 68fa ldr r2, [r7, #12]
8002f76: f647 73c0 movw r3, #32704 ; 0x7fc0
8002f7a: 4013 ands r3, r2
8002f7c: 687a ldr r2, [r7, #4]
8002f7e: 6a52 ldr r2, [r2, #36] ; 0x24
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
8002f80: 4293 cmp r3, r2
8002f82: d10d bne.n 8002fa0 <HAL_RCC_OscConfig+0x4c4>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) ||
8002f84: 68fb ldr r3, [r7, #12]
8002f86: f403 3240 and.w r2, r3, #196608 ; 0x30000
8002f8a: 687b ldr r3, [r7, #4]
8002f8c: 6a9b ldr r3, [r3, #40] ; 0x28
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != RCC_OscInitStruct->PLL.PLLN) ||
8002f8e: 429a cmp r2, r3
8002f90: d106 bne.n 8002fa0 <HAL_RCC_OscConfig+0x4c4>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ))
8002f92: 68fb ldr r3, [r7, #12]
8002f94: f003 6270 and.w r2, r3, #251658240 ; 0xf000000
8002f98: 687b ldr r3, [r7, #4]
8002f9a: 6adb ldr r3, [r3, #44] ; 0x2c
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) ||
8002f9c: 429a cmp r2, r3
8002f9e: d001 beq.n 8002fa4 <HAL_RCC_OscConfig+0x4c8>
{
return HAL_ERROR;
8002fa0: 2301 movs r3, #1
8002fa2: e000 b.n 8002fa6 <HAL_RCC_OscConfig+0x4ca>
}
}
}
}
return HAL_OK;
8002fa4: 2300 movs r3, #0
}
8002fa6: 4618 mov r0, r3
8002fa8: 3718 adds r7, #24
8002faa: 46bd mov sp, r7
8002fac: bd80 pop {r7, pc}
8002fae: bf00 nop
8002fb0: 40007000 .word 0x40007000
8002fb4: 40023800 .word 0x40023800
8002fb8: 42470060 .word 0x42470060
08002fbc <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval None
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8002fbc: b580 push {r7, lr}
8002fbe: b084 sub sp, #16
8002fc0: af00 add r7, sp, #0
8002fc2: 6078 str r0, [r7, #4]
8002fc4: 6039 str r1, [r7, #0]
uint32_t tickstart;
/* Check Null pointer */
if(RCC_ClkInitStruct == NULL)
8002fc6: 687b ldr r3, [r7, #4]
8002fc8: 2b00 cmp r3, #0
8002fca: d101 bne.n 8002fd0 <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
8002fcc: 2301 movs r3, #1
8002fce: e0cc b.n 800316a <HAL_RCC_ClockConfig+0x1ae>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if(FLatency > __HAL_FLASH_GET_LATENCY())
8002fd0: 4b68 ldr r3, [pc, #416] ; (8003174 <HAL_RCC_ClockConfig+0x1b8>)
8002fd2: 681b ldr r3, [r3, #0]
8002fd4: f003 030f and.w r3, r3, #15
8002fd8: 683a ldr r2, [r7, #0]
8002fda: 429a cmp r2, r3
8002fdc: d90c bls.n 8002ff8 <HAL_RCC_ClockConfig+0x3c>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8002fde: 4b65 ldr r3, [pc, #404] ; (8003174 <HAL_RCC_ClockConfig+0x1b8>)
8002fe0: 683a ldr r2, [r7, #0]
8002fe2: b2d2 uxtb r2, r2
8002fe4: 701a strb r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
8002fe6: 4b63 ldr r3, [pc, #396] ; (8003174 <HAL_RCC_ClockConfig+0x1b8>)
8002fe8: 681b ldr r3, [r3, #0]
8002fea: f003 030f and.w r3, r3, #15
8002fee: 683a ldr r2, [r7, #0]
8002ff0: 429a cmp r2, r3
8002ff2: d001 beq.n 8002ff8 <HAL_RCC_ClockConfig+0x3c>
{
return HAL_ERROR;
8002ff4: 2301 movs r3, #1
8002ff6: e0b8 b.n 800316a <HAL_RCC_ClockConfig+0x1ae>
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8002ff8: 687b ldr r3, [r7, #4]
8002ffa: 681b ldr r3, [r3, #0]
8002ffc: f003 0302 and.w r3, r3, #2
8003000: 2b00 cmp r3, #0
8003002: d020 beq.n 8003046 <HAL_RCC_ClockConfig+0x8a>
{
/* Set the highest APBx dividers in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8003004: 687b ldr r3, [r7, #4]
8003006: 681b ldr r3, [r3, #0]
8003008: f003 0304 and.w r3, r3, #4
800300c: 2b00 cmp r3, #0
800300e: d005 beq.n 800301c <HAL_RCC_ClockConfig+0x60>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
8003010: 4b59 ldr r3, [pc, #356] ; (8003178 <HAL_RCC_ClockConfig+0x1bc>)
8003012: 689b ldr r3, [r3, #8]
8003014: 4a58 ldr r2, [pc, #352] ; (8003178 <HAL_RCC_ClockConfig+0x1bc>)
8003016: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00
800301a: 6093 str r3, [r2, #8]
}
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
800301c: 687b ldr r3, [r7, #4]
800301e: 681b ldr r3, [r3, #0]
8003020: f003 0308 and.w r3, r3, #8
8003024: 2b00 cmp r3, #0
8003026: d005 beq.n 8003034 <HAL_RCC_ClockConfig+0x78>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
8003028: 4b53 ldr r3, [pc, #332] ; (8003178 <HAL_RCC_ClockConfig+0x1bc>)
800302a: 689b ldr r3, [r3, #8]
800302c: 4a52 ldr r2, [pc, #328] ; (8003178 <HAL_RCC_ClockConfig+0x1bc>)
800302e: f443 4360 orr.w r3, r3, #57344 ; 0xe000
8003032: 6093 str r3, [r2, #8]
}
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8003034: 4b50 ldr r3, [pc, #320] ; (8003178 <HAL_RCC_ClockConfig+0x1bc>)
8003036: 689b ldr r3, [r3, #8]
8003038: f023 02f0 bic.w r2, r3, #240 ; 0xf0
800303c: 687b ldr r3, [r7, #4]
800303e: 689b ldr r3, [r3, #8]
8003040: 494d ldr r1, [pc, #308] ; (8003178 <HAL_RCC_ClockConfig+0x1bc>)
8003042: 4313 orrs r3, r2
8003044: 608b str r3, [r1, #8]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8003046: 687b ldr r3, [r7, #4]
8003048: 681b ldr r3, [r3, #0]
800304a: f003 0301 and.w r3, r3, #1
800304e: 2b00 cmp r3, #0
8003050: d044 beq.n 80030dc <HAL_RCC_ClockConfig+0x120>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8003052: 687b ldr r3, [r7, #4]
8003054: 685b ldr r3, [r3, #4]
8003056: 2b01 cmp r3, #1
8003058: d107 bne.n 800306a <HAL_RCC_ClockConfig+0xae>
{
/* Check the HSE ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
800305a: 4b47 ldr r3, [pc, #284] ; (8003178 <HAL_RCC_ClockConfig+0x1bc>)
800305c: 681b ldr r3, [r3, #0]
800305e: f403 3300 and.w r3, r3, #131072 ; 0x20000
8003062: 2b00 cmp r3, #0
8003064: d119 bne.n 800309a <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8003066: 2301 movs r3, #1
8003068: e07f b.n 800316a <HAL_RCC_ClockConfig+0x1ae>
}
}
/* PLL is selected as System Clock Source */
else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
800306a: 687b ldr r3, [r7, #4]
800306c: 685b ldr r3, [r3, #4]
800306e: 2b02 cmp r3, #2
8003070: d003 beq.n 800307a <HAL_RCC_ClockConfig+0xbe>
(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
8003072: 687b ldr r3, [r7, #4]
8003074: 685b ldr r3, [r3, #4]
else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
8003076: 2b03 cmp r3, #3
8003078: d107 bne.n 800308a <HAL_RCC_ClockConfig+0xce>
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
800307a: 4b3f ldr r3, [pc, #252] ; (8003178 <HAL_RCC_ClockConfig+0x1bc>)
800307c: 681b ldr r3, [r3, #0]
800307e: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8003082: 2b00 cmp r3, #0
8003084: d109 bne.n 800309a <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8003086: 2301 movs r3, #1
8003088: e06f b.n 800316a <HAL_RCC_ClockConfig+0x1ae>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
800308a: 4b3b ldr r3, [pc, #236] ; (8003178 <HAL_RCC_ClockConfig+0x1bc>)
800308c: 681b ldr r3, [r3, #0]
800308e: f003 0302 and.w r3, r3, #2
8003092: 2b00 cmp r3, #0
8003094: d101 bne.n 800309a <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8003096: 2301 movs r3, #1
8003098: e067 b.n 800316a <HAL_RCC_ClockConfig+0x1ae>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
800309a: 4b37 ldr r3, [pc, #220] ; (8003178 <HAL_RCC_ClockConfig+0x1bc>)
800309c: 689b ldr r3, [r3, #8]
800309e: f023 0203 bic.w r2, r3, #3
80030a2: 687b ldr r3, [r7, #4]
80030a4: 685b ldr r3, [r3, #4]
80030a6: 4934 ldr r1, [pc, #208] ; (8003178 <HAL_RCC_ClockConfig+0x1bc>)
80030a8: 4313 orrs r3, r2
80030aa: 608b str r3, [r1, #8]
/* Get Start Tick */
tickstart = HAL_GetTick();
80030ac: f7fe fb40 bl 8001730 <HAL_GetTick>
80030b0: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
80030b2: e00a b.n 80030ca <HAL_RCC_ClockConfig+0x10e>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
80030b4: f7fe fb3c bl 8001730 <HAL_GetTick>
80030b8: 4602 mov r2, r0
80030ba: 68fb ldr r3, [r7, #12]
80030bc: 1ad3 subs r3, r2, r3
80030be: f241 3288 movw r2, #5000 ; 0x1388
80030c2: 4293 cmp r3, r2
80030c4: d901 bls.n 80030ca <HAL_RCC_ClockConfig+0x10e>
{
return HAL_TIMEOUT;
80030c6: 2303 movs r3, #3
80030c8: e04f b.n 800316a <HAL_RCC_ClockConfig+0x1ae>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
80030ca: 4b2b ldr r3, [pc, #172] ; (8003178 <HAL_RCC_ClockConfig+0x1bc>)
80030cc: 689b ldr r3, [r3, #8]
80030ce: f003 020c and.w r2, r3, #12
80030d2: 687b ldr r3, [r7, #4]
80030d4: 685b ldr r3, [r3, #4]
80030d6: 009b lsls r3, r3, #2
80030d8: 429a cmp r2, r3
80030da: d1eb bne.n 80030b4 <HAL_RCC_ClockConfig+0xf8>
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLatency < __HAL_FLASH_GET_LATENCY())
80030dc: 4b25 ldr r3, [pc, #148] ; (8003174 <HAL_RCC_ClockConfig+0x1b8>)
80030de: 681b ldr r3, [r3, #0]
80030e0: f003 030f and.w r3, r3, #15
80030e4: 683a ldr r2, [r7, #0]
80030e6: 429a cmp r2, r3
80030e8: d20c bcs.n 8003104 <HAL_RCC_ClockConfig+0x148>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
80030ea: 4b22 ldr r3, [pc, #136] ; (8003174 <HAL_RCC_ClockConfig+0x1b8>)
80030ec: 683a ldr r2, [r7, #0]
80030ee: b2d2 uxtb r2, r2
80030f0: 701a strb r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
80030f2: 4b20 ldr r3, [pc, #128] ; (8003174 <HAL_RCC_ClockConfig+0x1b8>)
80030f4: 681b ldr r3, [r3, #0]
80030f6: f003 030f and.w r3, r3, #15
80030fa: 683a ldr r2, [r7, #0]
80030fc: 429a cmp r2, r3
80030fe: d001 beq.n 8003104 <HAL_RCC_ClockConfig+0x148>
{
return HAL_ERROR;
8003100: 2301 movs r3, #1
8003102: e032 b.n 800316a <HAL_RCC_ClockConfig+0x1ae>
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8003104: 687b ldr r3, [r7, #4]
8003106: 681b ldr r3, [r3, #0]
8003108: f003 0304 and.w r3, r3, #4
800310c: 2b00 cmp r3, #0
800310e: d008 beq.n 8003122 <HAL_RCC_ClockConfig+0x166>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
8003110: 4b19 ldr r3, [pc, #100] ; (8003178 <HAL_RCC_ClockConfig+0x1bc>)
8003112: 689b ldr r3, [r3, #8]
8003114: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00
8003118: 687b ldr r3, [r7, #4]
800311a: 68db ldr r3, [r3, #12]
800311c: 4916 ldr r1, [pc, #88] ; (8003178 <HAL_RCC_ClockConfig+0x1bc>)
800311e: 4313 orrs r3, r2
8003120: 608b str r3, [r1, #8]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8003122: 687b ldr r3, [r7, #4]
8003124: 681b ldr r3, [r3, #0]
8003126: f003 0308 and.w r3, r3, #8
800312a: 2b00 cmp r3, #0
800312c: d009 beq.n 8003142 <HAL_RCC_ClockConfig+0x186>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
800312e: 4b12 ldr r3, [pc, #72] ; (8003178 <HAL_RCC_ClockConfig+0x1bc>)
8003130: 689b ldr r3, [r3, #8]
8003132: f423 4260 bic.w r2, r3, #57344 ; 0xe000
8003136: 687b ldr r3, [r7, #4]
8003138: 691b ldr r3, [r3, #16]
800313a: 00db lsls r3, r3, #3
800313c: 490e ldr r1, [pc, #56] ; (8003178 <HAL_RCC_ClockConfig+0x1bc>)
800313e: 4313 orrs r3, r2
8003140: 608b str r3, [r1, #8]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
8003142: f000 f821 bl 8003188 <HAL_RCC_GetSysClockFreq>
8003146: 4601 mov r1, r0
8003148: 4b0b ldr r3, [pc, #44] ; (8003178 <HAL_RCC_ClockConfig+0x1bc>)
800314a: 689b ldr r3, [r3, #8]
800314c: 091b lsrs r3, r3, #4
800314e: f003 030f and.w r3, r3, #15
8003152: 4a0a ldr r2, [pc, #40] ; (800317c <HAL_RCC_ClockConfig+0x1c0>)
8003154: 5cd3 ldrb r3, [r2, r3]
8003156: fa21 f303 lsr.w r3, r1, r3
800315a: 4a09 ldr r2, [pc, #36] ; (8003180 <HAL_RCC_ClockConfig+0x1c4>)
800315c: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings */
HAL_InitTick (uwTickPrio);
800315e: 4b09 ldr r3, [pc, #36] ; (8003184 <HAL_RCC_ClockConfig+0x1c8>)
8003160: 681b ldr r3, [r3, #0]
8003162: 4618 mov r0, r3
8003164: f7fe f9bc bl 80014e0 <HAL_InitTick>
return HAL_OK;
8003168: 2300 movs r3, #0
}
800316a: 4618 mov r0, r3
800316c: 3710 adds r7, #16
800316e: 46bd mov sp, r7
8003170: bd80 pop {r7, pc}
8003172: bf00 nop
8003174: 40023c00 .word 0x40023c00
8003178: 40023800 .word 0x40023800
800317c: 08004bc4 .word 0x08004bc4
8003180: 20000000 .word 0x20000000
8003184: 20000004 .word 0x20000004
08003188 <HAL_RCC_GetSysClockFreq>:
*
*
* @retval SYSCLK frequency
*/
__weak uint32_t HAL_RCC_GetSysClockFreq(void)
{
8003188: b5f0 push {r4, r5, r6, r7, lr}
800318a: b085 sub sp, #20
800318c: af00 add r7, sp, #0
uint32_t pllm = 0U, pllvco = 0U, pllp = 0U;
800318e: 2300 movs r3, #0
8003190: 607b str r3, [r7, #4]
8003192: 2300 movs r3, #0
8003194: 60fb str r3, [r7, #12]
8003196: 2300 movs r3, #0
8003198: 603b str r3, [r7, #0]
uint32_t sysclockfreq = 0U;
800319a: 2300 movs r3, #0
800319c: 60bb str r3, [r7, #8]
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
800319e: 4b63 ldr r3, [pc, #396] ; (800332c <HAL_RCC_GetSysClockFreq+0x1a4>)
80031a0: 689b ldr r3, [r3, #8]
80031a2: f003 030c and.w r3, r3, #12
80031a6: 2b04 cmp r3, #4
80031a8: d007 beq.n 80031ba <HAL_RCC_GetSysClockFreq+0x32>
80031aa: 2b08 cmp r3, #8
80031ac: d008 beq.n 80031c0 <HAL_RCC_GetSysClockFreq+0x38>
80031ae: 2b00 cmp r3, #0
80031b0: f040 80b4 bne.w 800331c <HAL_RCC_GetSysClockFreq+0x194>
{
case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
{
sysclockfreq = HSI_VALUE;
80031b4: 4b5e ldr r3, [pc, #376] ; (8003330 <HAL_RCC_GetSysClockFreq+0x1a8>)
80031b6: 60bb str r3, [r7, #8]
break;
80031b8: e0b3 b.n 8003322 <HAL_RCC_GetSysClockFreq+0x19a>
}
case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
{
sysclockfreq = HSE_VALUE;
80031ba: 4b5e ldr r3, [pc, #376] ; (8003334 <HAL_RCC_GetSysClockFreq+0x1ac>)
80031bc: 60bb str r3, [r7, #8]
break;
80031be: e0b0 b.n 8003322 <HAL_RCC_GetSysClockFreq+0x19a>
}
case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */
{
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
SYSCLK = PLL_VCO / PLLP */
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
80031c0: 4b5a ldr r3, [pc, #360] ; (800332c <HAL_RCC_GetSysClockFreq+0x1a4>)
80031c2: 685b ldr r3, [r3, #4]
80031c4: f003 033f and.w r3, r3, #63 ; 0x3f
80031c8: 607b str r3, [r7, #4]
if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
80031ca: 4b58 ldr r3, [pc, #352] ; (800332c <HAL_RCC_GetSysClockFreq+0x1a4>)
80031cc: 685b ldr r3, [r3, #4]
80031ce: f403 0380 and.w r3, r3, #4194304 ; 0x400000
80031d2: 2b00 cmp r3, #0
80031d4: d04a beq.n 800326c <HAL_RCC_GetSysClockFreq+0xe4>
{
/* HSE used as PLL clock source */
pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
80031d6: 4b55 ldr r3, [pc, #340] ; (800332c <HAL_RCC_GetSysClockFreq+0x1a4>)
80031d8: 685b ldr r3, [r3, #4]
80031da: 099b lsrs r3, r3, #6
80031dc: f04f 0400 mov.w r4, #0
80031e0: f240 11ff movw r1, #511 ; 0x1ff
80031e4: f04f 0200 mov.w r2, #0
80031e8: ea03 0501 and.w r5, r3, r1
80031ec: ea04 0602 and.w r6, r4, r2
80031f0: 4629 mov r1, r5
80031f2: 4632 mov r2, r6
80031f4: f04f 0300 mov.w r3, #0
80031f8: f04f 0400 mov.w r4, #0
80031fc: 0154 lsls r4, r2, #5
80031fe: ea44 64d1 orr.w r4, r4, r1, lsr #27
8003202: 014b lsls r3, r1, #5
8003204: 4619 mov r1, r3
8003206: 4622 mov r2, r4
8003208: 1b49 subs r1, r1, r5
800320a: eb62 0206 sbc.w r2, r2, r6
800320e: f04f 0300 mov.w r3, #0
8003212: f04f 0400 mov.w r4, #0
8003216: 0194 lsls r4, r2, #6
8003218: ea44 6491 orr.w r4, r4, r1, lsr #26
800321c: 018b lsls r3, r1, #6
800321e: 1a5b subs r3, r3, r1
8003220: eb64 0402 sbc.w r4, r4, r2
8003224: f04f 0100 mov.w r1, #0
8003228: f04f 0200 mov.w r2, #0
800322c: 00e2 lsls r2, r4, #3
800322e: ea42 7253 orr.w r2, r2, r3, lsr #29
8003232: 00d9 lsls r1, r3, #3
8003234: 460b mov r3, r1
8003236: 4614 mov r4, r2
8003238: 195b adds r3, r3, r5
800323a: eb44 0406 adc.w r4, r4, r6
800323e: f04f 0100 mov.w r1, #0
8003242: f04f 0200 mov.w r2, #0
8003246: 0262 lsls r2, r4, #9
8003248: ea42 52d3 orr.w r2, r2, r3, lsr #23
800324c: 0259 lsls r1, r3, #9
800324e: 460b mov r3, r1
8003250: 4614 mov r4, r2
8003252: 4618 mov r0, r3
8003254: 4621 mov r1, r4
8003256: 687b ldr r3, [r7, #4]
8003258: f04f 0400 mov.w r4, #0
800325c: 461a mov r2, r3
800325e: 4623 mov r3, r4
8003260: f7fc ffc4 bl 80001ec <__aeabi_uldivmod>
8003264: 4603 mov r3, r0
8003266: 460c mov r4, r1
8003268: 60fb str r3, [r7, #12]
800326a: e049 b.n 8003300 <HAL_RCC_GetSysClockFreq+0x178>
}
else
{
/* HSI used as PLL clock source */
pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
800326c: 4b2f ldr r3, [pc, #188] ; (800332c <HAL_RCC_GetSysClockFreq+0x1a4>)
800326e: 685b ldr r3, [r3, #4]
8003270: 099b lsrs r3, r3, #6
8003272: f04f 0400 mov.w r4, #0
8003276: f240 11ff movw r1, #511 ; 0x1ff
800327a: f04f 0200 mov.w r2, #0
800327e: ea03 0501 and.w r5, r3, r1
8003282: ea04 0602 and.w r6, r4, r2
8003286: 4629 mov r1, r5
8003288: 4632 mov r2, r6
800328a: f04f 0300 mov.w r3, #0
800328e: f04f 0400 mov.w r4, #0
8003292: 0154 lsls r4, r2, #5
8003294: ea44 64d1 orr.w r4, r4, r1, lsr #27
8003298: 014b lsls r3, r1, #5
800329a: 4619 mov r1, r3
800329c: 4622 mov r2, r4
800329e: 1b49 subs r1, r1, r5
80032a0: eb62 0206 sbc.w r2, r2, r6
80032a4: f04f 0300 mov.w r3, #0
80032a8: f04f 0400 mov.w r4, #0
80032ac: 0194 lsls r4, r2, #6
80032ae: ea44 6491 orr.w r4, r4, r1, lsr #26
80032b2: 018b lsls r3, r1, #6
80032b4: 1a5b subs r3, r3, r1
80032b6: eb64 0402 sbc.w r4, r4, r2
80032ba: f04f 0100 mov.w r1, #0
80032be: f04f 0200 mov.w r2, #0
80032c2: 00e2 lsls r2, r4, #3
80032c4: ea42 7253 orr.w r2, r2, r3, lsr #29
80032c8: 00d9 lsls r1, r3, #3
80032ca: 460b mov r3, r1
80032cc: 4614 mov r4, r2
80032ce: 195b adds r3, r3, r5
80032d0: eb44 0406 adc.w r4, r4, r6
80032d4: f04f 0100 mov.w r1, #0
80032d8: f04f 0200 mov.w r2, #0
80032dc: 02a2 lsls r2, r4, #10
80032de: ea42 5293 orr.w r2, r2, r3, lsr #22
80032e2: 0299 lsls r1, r3, #10
80032e4: 460b mov r3, r1
80032e6: 4614 mov r4, r2
80032e8: 4618 mov r0, r3
80032ea: 4621 mov r1, r4
80032ec: 687b ldr r3, [r7, #4]
80032ee: f04f 0400 mov.w r4, #0
80032f2: 461a mov r2, r3
80032f4: 4623 mov r3, r4
80032f6: f7fc ff79 bl 80001ec <__aeabi_uldivmod>
80032fa: 4603 mov r3, r0
80032fc: 460c mov r4, r1
80032fe: 60fb str r3, [r7, #12]
}
pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U);
8003300: 4b0a ldr r3, [pc, #40] ; (800332c <HAL_RCC_GetSysClockFreq+0x1a4>)
8003302: 685b ldr r3, [r3, #4]
8003304: 0c1b lsrs r3, r3, #16
8003306: f003 0303 and.w r3, r3, #3
800330a: 3301 adds r3, #1
800330c: 005b lsls r3, r3, #1
800330e: 603b str r3, [r7, #0]
sysclockfreq = pllvco/pllp;
8003310: 68fa ldr r2, [r7, #12]
8003312: 683b ldr r3, [r7, #0]
8003314: fbb2 f3f3 udiv r3, r2, r3
8003318: 60bb str r3, [r7, #8]
break;
800331a: e002 b.n 8003322 <HAL_RCC_GetSysClockFreq+0x19a>
}
default:
{
sysclockfreq = HSI_VALUE;
800331c: 4b04 ldr r3, [pc, #16] ; (8003330 <HAL_RCC_GetSysClockFreq+0x1a8>)
800331e: 60bb str r3, [r7, #8]
break;
8003320: bf00 nop
}
}
return sysclockfreq;
8003322: 68bb ldr r3, [r7, #8]
}
8003324: 4618 mov r0, r3
8003326: 3714 adds r7, #20
8003328: 46bd mov sp, r7
800332a: bdf0 pop {r4, r5, r6, r7, pc}
800332c: 40023800 .word 0x40023800
8003330: 00f42400 .word 0x00f42400
8003334: 007a1200 .word 0x007a1200
08003338 <HAL_RCC_GetHCLKFreq>:
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
* and updated within this function
* @retval HCLK frequency
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
8003338: b480 push {r7}
800333a: af00 add r7, sp, #0
return SystemCoreClock;
800333c: 4b03 ldr r3, [pc, #12] ; (800334c <HAL_RCC_GetHCLKFreq+0x14>)
800333e: 681b ldr r3, [r3, #0]
}
8003340: 4618 mov r0, r3
8003342: 46bd mov sp, r7
8003344: f85d 7b04 ldr.w r7, [sp], #4
8003348: 4770 bx lr
800334a: bf00 nop
800334c: 20000000 .word 0x20000000
08003350 <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
8003350: b580 push {r7, lr}
8003352: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]);
8003354: f7ff fff0 bl 8003338 <HAL_RCC_GetHCLKFreq>
8003358: 4601 mov r1, r0
800335a: 4b05 ldr r3, [pc, #20] ; (8003370 <HAL_RCC_GetPCLK1Freq+0x20>)
800335c: 689b ldr r3, [r3, #8]
800335e: 0a9b lsrs r3, r3, #10
8003360: f003 0307 and.w r3, r3, #7
8003364: 4a03 ldr r2, [pc, #12] ; (8003374 <HAL_RCC_GetPCLK1Freq+0x24>)
8003366: 5cd3 ldrb r3, [r2, r3]
8003368: fa21 f303 lsr.w r3, r1, r3
}
800336c: 4618 mov r0, r3
800336e: bd80 pop {r7, pc}
8003370: 40023800 .word 0x40023800
8003374: 08004bd4 .word 0x08004bd4
08003378 <HAL_RCC_GetPCLK2Freq>:
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK2 frequency
*/
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
8003378: b580 push {r7, lr}
800337a: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]);
800337c: f7ff ffdc bl 8003338 <HAL_RCC_GetHCLKFreq>
8003380: 4601 mov r1, r0
8003382: 4b05 ldr r3, [pc, #20] ; (8003398 <HAL_RCC_GetPCLK2Freq+0x20>)
8003384: 689b ldr r3, [r3, #8]
8003386: 0b5b lsrs r3, r3, #13
8003388: f003 0307 and.w r3, r3, #7
800338c: 4a03 ldr r2, [pc, #12] ; (800339c <HAL_RCC_GetPCLK2Freq+0x24>)
800338e: 5cd3 ldrb r3, [r2, r3]
8003390: fa21 f303 lsr.w r3, r1, r3
}
8003394: 4618 mov r0, r3
8003396: bd80 pop {r7, pc}
8003398: 40023800 .word 0x40023800
800339c: 08004bd4 .word 0x08004bd4
080033a0 <HAL_RCC_GetClockConfig>:
* will be configured.
* @param pFLatency Pointer on the Flash Latency.
* @retval None
*/
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
{
80033a0: b480 push {r7}
80033a2: b083 sub sp, #12
80033a4: af00 add r7, sp, #0
80033a6: 6078 str r0, [r7, #4]
80033a8: 6039 str r1, [r7, #0]
/* Set all possible values for the Clock type parameter --------------------*/
RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
80033aa: 687b ldr r3, [r7, #4]
80033ac: 220f movs r2, #15
80033ae: 601a str r2, [r3, #0]
/* Get the SYSCLK configuration --------------------------------------------*/
RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
80033b0: 4b12 ldr r3, [pc, #72] ; (80033fc <HAL_RCC_GetClockConfig+0x5c>)
80033b2: 689b ldr r3, [r3, #8]
80033b4: f003 0203 and.w r2, r3, #3
80033b8: 687b ldr r3, [r7, #4]
80033ba: 605a str r2, [r3, #4]
/* Get the HCLK configuration ----------------------------------------------*/
RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
80033bc: 4b0f ldr r3, [pc, #60] ; (80033fc <HAL_RCC_GetClockConfig+0x5c>)
80033be: 689b ldr r3, [r3, #8]
80033c0: f003 02f0 and.w r2, r3, #240 ; 0xf0
80033c4: 687b ldr r3, [r7, #4]
80033c6: 609a str r2, [r3, #8]
/* Get the APB1 configuration ----------------------------------------------*/
RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
80033c8: 4b0c ldr r3, [pc, #48] ; (80033fc <HAL_RCC_GetClockConfig+0x5c>)
80033ca: 689b ldr r3, [r3, #8]
80033cc: f403 52e0 and.w r2, r3, #7168 ; 0x1c00
80033d0: 687b ldr r3, [r7, #4]
80033d2: 60da str r2, [r3, #12]
/* Get the APB2 configuration ----------------------------------------------*/
RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U);
80033d4: 4b09 ldr r3, [pc, #36] ; (80033fc <HAL_RCC_GetClockConfig+0x5c>)
80033d6: 689b ldr r3, [r3, #8]
80033d8: 08db lsrs r3, r3, #3
80033da: f403 52e0 and.w r2, r3, #7168 ; 0x1c00
80033de: 687b ldr r3, [r7, #4]
80033e0: 611a str r2, [r3, #16]
/* Get the Flash Wait State (Latency) configuration ------------------------*/
*pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
80033e2: 4b07 ldr r3, [pc, #28] ; (8003400 <HAL_RCC_GetClockConfig+0x60>)
80033e4: 681b ldr r3, [r3, #0]
80033e6: f003 020f and.w r2, r3, #15
80033ea: 683b ldr r3, [r7, #0]
80033ec: 601a str r2, [r3, #0]
}
80033ee: bf00 nop
80033f0: 370c adds r7, #12
80033f2: 46bd mov sp, r7
80033f4: f85d 7b04 ldr.w r7, [sp], #4
80033f8: 4770 bx lr
80033fa: bf00 nop
80033fc: 40023800 .word 0x40023800
8003400: 40023c00 .word 0x40023c00
08003404 <HAL_RCCEx_PeriphCLKConfig>:
* the backup registers) and RCC_BDCR register are set to their reset values.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
8003404: b580 push {r7, lr}
8003406: b086 sub sp, #24
8003408: af00 add r7, sp, #0
800340a: 6078 str r0, [r7, #4]
uint32_t tickstart = 0U;
800340c: 2300 movs r3, #0
800340e: 617b str r3, [r7, #20]
uint32_t tmpreg1 = 0U;
8003410: 2300 movs r3, #0
8003412: 613b str r3, [r7, #16]
/*----------------------- SAI/I2S Configuration (PLLI2S) -------------------*/
/*----------------------- Common configuration SAI/I2S ---------------------*/
/* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division
factor is common parameters for both peripherals */
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||
8003414: 687b ldr r3, [r7, #4]
8003416: 681b ldr r3, [r3, #0]
8003418: f003 0301 and.w r3, r3, #1
800341c: 2b00 cmp r3, #0
800341e: d10b bne.n 8003438 <HAL_RCCEx_PeriphCLKConfig+0x34>
(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S) ||
8003420: 687b ldr r3, [r7, #4]
8003422: 681b ldr r3, [r3, #0]
8003424: f003 0302 and.w r3, r3, #2
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||
8003428: 2b00 cmp r3, #0
800342a: d105 bne.n 8003438 <HAL_RCCEx_PeriphCLKConfig+0x34>
(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))
800342c: 687b ldr r3, [r7, #4]
800342e: 681b ldr r3, [r3, #0]
8003430: f003 0340 and.w r3, r3, #64 ; 0x40
(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S) ||
8003434: 2b00 cmp r3, #0
8003436: d075 beq.n 8003524 <HAL_RCCEx_PeriphCLKConfig+0x120>
{
/* check for Parameters */
assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
/* Disable the PLLI2S */
__HAL_RCC_PLLI2S_DISABLE();
8003438: 4bad ldr r3, [pc, #692] ; (80036f0 <HAL_RCCEx_PeriphCLKConfig+0x2ec>)
800343a: 2200 movs r2, #0
800343c: 601a str r2, [r3, #0]
/* Get tick */
tickstart = HAL_GetTick();
800343e: f7fe f977 bl 8001730 <HAL_GetTick>
8003442: 6178 str r0, [r7, #20]
/* Wait till PLLI2S is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
8003444: e008 b.n 8003458 <HAL_RCCEx_PeriphCLKConfig+0x54>
{
if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
8003446: f7fe f973 bl 8001730 <HAL_GetTick>
800344a: 4602 mov r2, r0
800344c: 697b ldr r3, [r7, #20]
800344e: 1ad3 subs r3, r2, r3
8003450: 2b02 cmp r3, #2
8003452: d901 bls.n 8003458 <HAL_RCCEx_PeriphCLKConfig+0x54>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
8003454: 2303 movs r3, #3
8003456: e18b b.n 8003770 <HAL_RCCEx_PeriphCLKConfig+0x36c>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
8003458: 4ba6 ldr r3, [pc, #664] ; (80036f4 <HAL_RCCEx_PeriphCLKConfig+0x2f0>)
800345a: 681b ldr r3, [r3, #0]
800345c: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
8003460: 2b00 cmp r3, #0
8003462: d1f0 bne.n 8003446 <HAL_RCCEx_PeriphCLKConfig+0x42>
}
/*---------------------------- I2S configuration -------------------------*/
/* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added
only for I2S configuration */
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
8003464: 687b ldr r3, [r7, #4]
8003466: 681b ldr r3, [r3, #0]
8003468: f003 0301 and.w r3, r3, #1
800346c: 2b00 cmp r3, #0
800346e: d009 beq.n 8003484 <HAL_RCCEx_PeriphCLKConfig+0x80>
/* check for Parameters */
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */
/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
8003470: 687b ldr r3, [r7, #4]
8003472: 685b ldr r3, [r3, #4]
8003474: 019a lsls r2, r3, #6
8003476: 687b ldr r3, [r7, #4]
8003478: 689b ldr r3, [r3, #8]
800347a: 071b lsls r3, r3, #28
800347c: 499d ldr r1, [pc, #628] ; (80036f4 <HAL_RCCEx_PeriphCLKConfig+0x2f0>)
800347e: 4313 orrs r3, r2
8003480: f8c1 3084 str.w r3, [r1, #132] ; 0x84
}
/*---------------------------- SAI configuration -------------------------*/
/* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must
be added only for SAI configuration */
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S))
8003484: 687b ldr r3, [r7, #4]
8003486: 681b ldr r3, [r3, #0]
8003488: f003 0302 and.w r3, r3, #2
800348c: 2b00 cmp r3, #0
800348e: d01f beq.n 80034d0 <HAL_RCCEx_PeriphCLKConfig+0xcc>
/* Check the PLLI2S division factors */
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
/* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
8003490: 4b98 ldr r3, [pc, #608] ; (80036f4 <HAL_RCCEx_PeriphCLKConfig+0x2f0>)
8003492: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
8003496: 0f1b lsrs r3, r3, #28
8003498: f003 0307 and.w r3, r3, #7
800349c: 613b str r3, [r7, #16]
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
__HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg1);
800349e: 687b ldr r3, [r7, #4]
80034a0: 685b ldr r3, [r3, #4]
80034a2: 019a lsls r2, r3, #6
80034a4: 687b ldr r3, [r7, #4]
80034a6: 68db ldr r3, [r3, #12]
80034a8: 061b lsls r3, r3, #24
80034aa: 431a orrs r2, r3
80034ac: 693b ldr r3, [r7, #16]
80034ae: 071b lsls r3, r3, #28
80034b0: 4990 ldr r1, [pc, #576] ; (80036f4 <HAL_RCCEx_PeriphCLKConfig+0x2f0>)
80034b2: 4313 orrs r3, r2
80034b4: f8c1 3084 str.w r3, [r1, #132] ; 0x84
/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
80034b8: 4b8e ldr r3, [pc, #568] ; (80036f4 <HAL_RCCEx_PeriphCLKConfig+0x2f0>)
80034ba: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
80034be: f023 021f bic.w r2, r3, #31
80034c2: 687b ldr r3, [r7, #4]
80034c4: 69db ldr r3, [r3, #28]
80034c6: 3b01 subs r3, #1
80034c8: 498a ldr r1, [pc, #552] ; (80036f4 <HAL_RCCEx_PeriphCLKConfig+0x2f0>)
80034ca: 4313 orrs r3, r2
80034cc: f8c1 308c str.w r3, [r1, #140] ; 0x8c
}
/*----------------- In Case of PLLI2S is just selected -----------------*/
if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
80034d0: 687b ldr r3, [r7, #4]
80034d2: 681b ldr r3, [r3, #0]
80034d4: f003 0340 and.w r3, r3, #64 ; 0x40
80034d8: 2b00 cmp r3, #0
80034da: d00d beq.n 80034f8 <HAL_RCCEx_PeriphCLKConfig+0xf4>
/* Check for Parameters */
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
/* Configure the PLLI2S multiplication and division factors */
__HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
80034dc: 687b ldr r3, [r7, #4]
80034de: 685b ldr r3, [r3, #4]
80034e0: 019a lsls r2, r3, #6
80034e2: 687b ldr r3, [r7, #4]
80034e4: 68db ldr r3, [r3, #12]
80034e6: 061b lsls r3, r3, #24
80034e8: 431a orrs r2, r3
80034ea: 687b ldr r3, [r7, #4]
80034ec: 689b ldr r3, [r3, #8]
80034ee: 071b lsls r3, r3, #28
80034f0: 4980 ldr r1, [pc, #512] ; (80036f4 <HAL_RCCEx_PeriphCLKConfig+0x2f0>)
80034f2: 4313 orrs r3, r2
80034f4: f8c1 3084 str.w r3, [r1, #132] ; 0x84
}
/* Enable the PLLI2S */
__HAL_RCC_PLLI2S_ENABLE();
80034f8: 4b7d ldr r3, [pc, #500] ; (80036f0 <HAL_RCCEx_PeriphCLKConfig+0x2ec>)
80034fa: 2201 movs r2, #1
80034fc: 601a str r2, [r3, #0]
/* Get tick */
tickstart = HAL_GetTick();
80034fe: f7fe f917 bl 8001730 <HAL_GetTick>
8003502: 6178 str r0, [r7, #20]
/* Wait till PLLI2S is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
8003504: e008 b.n 8003518 <HAL_RCCEx_PeriphCLKConfig+0x114>
{
if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
8003506: f7fe f913 bl 8001730 <HAL_GetTick>
800350a: 4602 mov r2, r0
800350c: 697b ldr r3, [r7, #20]
800350e: 1ad3 subs r3, r2, r3
8003510: 2b02 cmp r3, #2
8003512: d901 bls.n 8003518 <HAL_RCCEx_PeriphCLKConfig+0x114>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
8003514: 2303 movs r3, #3
8003516: e12b b.n 8003770 <HAL_RCCEx_PeriphCLKConfig+0x36c>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
8003518: 4b76 ldr r3, [pc, #472] ; (80036f4 <HAL_RCCEx_PeriphCLKConfig+0x2f0>)
800351a: 681b ldr r3, [r3, #0]
800351c: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
8003520: 2b00 cmp r3, #0
8003522: d0f0 beq.n 8003506 <HAL_RCCEx_PeriphCLKConfig+0x102>
/*----------------------- SAI/LTDC Configuration (PLLSAI) ------------------*/
/*----------------------- Common configuration SAI/LTDC --------------------*/
/* In Case of SAI or LTDC Clock Configuration through PLLSAI, PLLSAIN division
factor is common parameters for both peripherals */
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) ||
8003524: 687b ldr r3, [r7, #4]
8003526: 681b ldr r3, [r3, #0]
8003528: f003 0304 and.w r3, r3, #4
800352c: 2b00 cmp r3, #0
800352e: d105 bne.n 800353c <HAL_RCCEx_PeriphCLKConfig+0x138>
(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC))
8003530: 687b ldr r3, [r7, #4]
8003532: 681b ldr r3, [r3, #0]
8003534: f003 0308 and.w r3, r3, #8
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) ||
8003538: 2b00 cmp r3, #0
800353a: d079 beq.n 8003630 <HAL_RCCEx_PeriphCLKConfig+0x22c>
{
/* Check the PLLSAI division factors */
assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
/* Disable PLLSAI Clock */
__HAL_RCC_PLLSAI_DISABLE();
800353c: 4b6e ldr r3, [pc, #440] ; (80036f8 <HAL_RCCEx_PeriphCLKConfig+0x2f4>)
800353e: 2200 movs r2, #0
8003540: 601a str r2, [r3, #0]
/* Get tick */
tickstart = HAL_GetTick();
8003542: f7fe f8f5 bl 8001730 <HAL_GetTick>
8003546: 6178 str r0, [r7, #20]
/* Wait till PLLSAI is disabled */
while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
8003548: e008 b.n 800355c <HAL_RCCEx_PeriphCLKConfig+0x158>
{
if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
800354a: f7fe f8f1 bl 8001730 <HAL_GetTick>
800354e: 4602 mov r2, r0
8003550: 697b ldr r3, [r7, #20]
8003552: 1ad3 subs r3, r2, r3
8003554: 2b02 cmp r3, #2
8003556: d901 bls.n 800355c <HAL_RCCEx_PeriphCLKConfig+0x158>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
8003558: 2303 movs r3, #3
800355a: e109 b.n 8003770 <HAL_RCCEx_PeriphCLKConfig+0x36c>
while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
800355c: 4b65 ldr r3, [pc, #404] ; (80036f4 <HAL_RCCEx_PeriphCLKConfig+0x2f0>)
800355e: 681b ldr r3, [r3, #0]
8003560: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
8003564: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
8003568: d0ef beq.n 800354a <HAL_RCCEx_PeriphCLKConfig+0x146>
}
/*---------------------------- SAI configuration -------------------------*/
/* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must
be added only for SAI configuration */
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI))
800356a: 687b ldr r3, [r7, #4]
800356c: 681b ldr r3, [r3, #0]
800356e: f003 0304 and.w r3, r3, #4
8003572: 2b00 cmp r3, #0
8003574: d020 beq.n 80035b8 <HAL_RCCEx_PeriphCLKConfig+0x1b4>
{
assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
/* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
8003576: 4b5f ldr r3, [pc, #380] ; (80036f4 <HAL_RCCEx_PeriphCLKConfig+0x2f0>)
8003578: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
800357c: 0f1b lsrs r3, r3, #28
800357e: f003 0307 and.w r3, r3, #7
8003582: 613b str r3, [r7, #16]
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);
8003584: 687b ldr r3, [r7, #4]
8003586: 691b ldr r3, [r3, #16]
8003588: 019a lsls r2, r3, #6
800358a: 687b ldr r3, [r7, #4]
800358c: 695b ldr r3, [r3, #20]
800358e: 061b lsls r3, r3, #24
8003590: 431a orrs r2, r3
8003592: 693b ldr r3, [r7, #16]
8003594: 071b lsls r3, r3, #28
8003596: 4957 ldr r1, [pc, #348] ; (80036f4 <HAL_RCCEx_PeriphCLKConfig+0x2f0>)
8003598: 4313 orrs r3, r2
800359a: f8c1 3088 str.w r3, [r1, #136] ; 0x88
/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
800359e: 4b55 ldr r3, [pc, #340] ; (80036f4 <HAL_RCCEx_PeriphCLKConfig+0x2f0>)
80035a0: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
80035a4: f423 52f8 bic.w r2, r3, #7936 ; 0x1f00
80035a8: 687b ldr r3, [r7, #4]
80035aa: 6a1b ldr r3, [r3, #32]
80035ac: 3b01 subs r3, #1
80035ae: 021b lsls r3, r3, #8
80035b0: 4950 ldr r1, [pc, #320] ; (80036f4 <HAL_RCCEx_PeriphCLKConfig+0x2f0>)
80035b2: 4313 orrs r3, r2
80035b4: f8c1 308c str.w r3, [r1, #140] ; 0x8c
}
/*---------------------------- LTDC configuration ------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
80035b8: 687b ldr r3, [r7, #4]
80035ba: 681b ldr r3, [r3, #0]
80035bc: f003 0308 and.w r3, r3, #8
80035c0: 2b00 cmp r3, #0
80035c2: d01e beq.n 8003602 <HAL_RCCEx_PeriphCLKConfig+0x1fe>
{
assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
/* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
80035c4: 4b4b ldr r3, [pc, #300] ; (80036f4 <HAL_RCCEx_PeriphCLKConfig+0x2f0>)
80035c6: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
80035ca: 0e1b lsrs r3, r3, #24
80035cc: f003 030f and.w r3, r3, #15
80035d0: 613b str r3, [r7, #16]
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
/* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, PeriphClkInit->PLLSAI.PLLSAIR);
80035d2: 687b ldr r3, [r7, #4]
80035d4: 691b ldr r3, [r3, #16]
80035d6: 019a lsls r2, r3, #6
80035d8: 693b ldr r3, [r7, #16]
80035da: 061b lsls r3, r3, #24
80035dc: 431a orrs r2, r3
80035de: 687b ldr r3, [r7, #4]
80035e0: 699b ldr r3, [r3, #24]
80035e2: 071b lsls r3, r3, #28
80035e4: 4943 ldr r1, [pc, #268] ; (80036f4 <HAL_RCCEx_PeriphCLKConfig+0x2f0>)
80035e6: 4313 orrs r3, r2
80035e8: f8c1 3088 str.w r3, [r1, #136] ; 0x88
/* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
__HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
80035ec: 4b41 ldr r3, [pc, #260] ; (80036f4 <HAL_RCCEx_PeriphCLKConfig+0x2f0>)
80035ee: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c
80035f2: f423 3240 bic.w r2, r3, #196608 ; 0x30000
80035f6: 687b ldr r3, [r7, #4]
80035f8: 6a5b ldr r3, [r3, #36] ; 0x24
80035fa: 493e ldr r1, [pc, #248] ; (80036f4 <HAL_RCCEx_PeriphCLKConfig+0x2f0>)
80035fc: 4313 orrs r3, r2
80035fe: f8c1 308c str.w r3, [r1, #140] ; 0x8c
}
/* Enable PLLSAI Clock */
__HAL_RCC_PLLSAI_ENABLE();
8003602: 4b3d ldr r3, [pc, #244] ; (80036f8 <HAL_RCCEx_PeriphCLKConfig+0x2f4>)
8003604: 2201 movs r2, #1
8003606: 601a str r2, [r3, #0]
/* Get tick */
tickstart = HAL_GetTick();
8003608: f7fe f892 bl 8001730 <HAL_GetTick>
800360c: 6178 str r0, [r7, #20]
/* Wait till PLLSAI is ready */
while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
800360e: e008 b.n 8003622 <HAL_RCCEx_PeriphCLKConfig+0x21e>
{
if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
8003610: f7fe f88e bl 8001730 <HAL_GetTick>
8003614: 4602 mov r2, r0
8003616: 697b ldr r3, [r7, #20]
8003618: 1ad3 subs r3, r2, r3
800361a: 2b02 cmp r3, #2
800361c: d901 bls.n 8003622 <HAL_RCCEx_PeriphCLKConfig+0x21e>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
800361e: 2303 movs r3, #3
8003620: e0a6 b.n 8003770 <HAL_RCCEx_PeriphCLKConfig+0x36c>
while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
8003622: 4b34 ldr r3, [pc, #208] ; (80036f4 <HAL_RCCEx_PeriphCLKConfig+0x2f0>)
8003624: 681b ldr r3, [r3, #0]
8003626: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
800362a: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000
800362e: d1ef bne.n 8003610 <HAL_RCCEx_PeriphCLKConfig+0x20c>
}
}
/*--------------------------------------------------------------------------*/
/*---------------------------- RTC configuration ---------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
8003630: 687b ldr r3, [r7, #4]
8003632: 681b ldr r3, [r3, #0]
8003634: f003 0320 and.w r3, r3, #32
8003638: 2b00 cmp r3, #0
800363a: f000 808d beq.w 8003758 <HAL_RCCEx_PeriphCLKConfig+0x354>
{
/* Check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
/* Enable Power Clock*/
__HAL_RCC_PWR_CLK_ENABLE();
800363e: 2300 movs r3, #0
8003640: 60fb str r3, [r7, #12]
8003642: 4b2c ldr r3, [pc, #176] ; (80036f4 <HAL_RCCEx_PeriphCLKConfig+0x2f0>)
8003644: 6c1b ldr r3, [r3, #64] ; 0x40
8003646: 4a2b ldr r2, [pc, #172] ; (80036f4 <HAL_RCCEx_PeriphCLKConfig+0x2f0>)
8003648: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
800364c: 6413 str r3, [r2, #64] ; 0x40
800364e: 4b29 ldr r3, [pc, #164] ; (80036f4 <HAL_RCCEx_PeriphCLKConfig+0x2f0>)
8003650: 6c1b ldr r3, [r3, #64] ; 0x40
8003652: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8003656: 60fb str r3, [r7, #12]
8003658: 68fb ldr r3, [r7, #12]
/* Enable write access to Backup domain */
PWR->CR |= PWR_CR_DBP;
800365a: 4b28 ldr r3, [pc, #160] ; (80036fc <HAL_RCCEx_PeriphCLKConfig+0x2f8>)
800365c: 681b ldr r3, [r3, #0]
800365e: 4a27 ldr r2, [pc, #156] ; (80036fc <HAL_RCCEx_PeriphCLKConfig+0x2f8>)
8003660: f443 7380 orr.w r3, r3, #256 ; 0x100
8003664: 6013 str r3, [r2, #0]
/* Get tick */
tickstart = HAL_GetTick();
8003666: f7fe f863 bl 8001730 <HAL_GetTick>
800366a: 6178 str r0, [r7, #20]
while((PWR->CR & PWR_CR_DBP) == RESET)
800366c: e008 b.n 8003680 <HAL_RCCEx_PeriphCLKConfig+0x27c>
{
if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
800366e: f7fe f85f bl 8001730 <HAL_GetTick>
8003672: 4602 mov r2, r0
8003674: 697b ldr r3, [r7, #20]
8003676: 1ad3 subs r3, r2, r3
8003678: 2b02 cmp r3, #2
800367a: d901 bls.n 8003680 <HAL_RCCEx_PeriphCLKConfig+0x27c>
{
return HAL_TIMEOUT;
800367c: 2303 movs r3, #3
800367e: e077 b.n 8003770 <HAL_RCCEx_PeriphCLKConfig+0x36c>
while((PWR->CR & PWR_CR_DBP) == RESET)
8003680: 4b1e ldr r3, [pc, #120] ; (80036fc <HAL_RCCEx_PeriphCLKConfig+0x2f8>)
8003682: 681b ldr r3, [r3, #0]
8003684: f403 7380 and.w r3, r3, #256 ; 0x100
8003688: 2b00 cmp r3, #0
800368a: d0f0 beq.n 800366e <HAL_RCCEx_PeriphCLKConfig+0x26a>
}
}
/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
800368c: 4b19 ldr r3, [pc, #100] ; (80036f4 <HAL_RCCEx_PeriphCLKConfig+0x2f0>)
800368e: 6f1b ldr r3, [r3, #112] ; 0x70
8003690: f403 7340 and.w r3, r3, #768 ; 0x300
8003694: 613b str r3, [r7, #16]
if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
8003696: 693b ldr r3, [r7, #16]
8003698: 2b00 cmp r3, #0
800369a: d039 beq.n 8003710 <HAL_RCCEx_PeriphCLKConfig+0x30c>
800369c: 687b ldr r3, [r7, #4]
800369e: 6a9b ldr r3, [r3, #40] ; 0x28
80036a0: f403 7340 and.w r3, r3, #768 ; 0x300
80036a4: 693a ldr r2, [r7, #16]
80036a6: 429a cmp r2, r3
80036a8: d032 beq.n 8003710 <HAL_RCCEx_PeriphCLKConfig+0x30c>
{
/* Store the content of BDCR register before the reset of Backup Domain */
tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
80036aa: 4b12 ldr r3, [pc, #72] ; (80036f4 <HAL_RCCEx_PeriphCLKConfig+0x2f0>)
80036ac: 6f1b ldr r3, [r3, #112] ; 0x70
80036ae: f423 7340 bic.w r3, r3, #768 ; 0x300
80036b2: 613b str r3, [r7, #16]
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
80036b4: 4b12 ldr r3, [pc, #72] ; (8003700 <HAL_RCCEx_PeriphCLKConfig+0x2fc>)
80036b6: 2201 movs r2, #1
80036b8: 601a str r2, [r3, #0]
__HAL_RCC_BACKUPRESET_RELEASE();
80036ba: 4b11 ldr r3, [pc, #68] ; (8003700 <HAL_RCCEx_PeriphCLKConfig+0x2fc>)
80036bc: 2200 movs r2, #0
80036be: 601a str r2, [r3, #0]
/* Restore the Content of BDCR register */
RCC->BDCR = tmpreg1;
80036c0: 4a0c ldr r2, [pc, #48] ; (80036f4 <HAL_RCCEx_PeriphCLKConfig+0x2f0>)
80036c2: 693b ldr r3, [r7, #16]
80036c4: 6713 str r3, [r2, #112] ; 0x70
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
80036c6: 4b0b ldr r3, [pc, #44] ; (80036f4 <HAL_RCCEx_PeriphCLKConfig+0x2f0>)
80036c8: 6f1b ldr r3, [r3, #112] ; 0x70
80036ca: f003 0301 and.w r3, r3, #1
80036ce: 2b01 cmp r3, #1
80036d0: d11e bne.n 8003710 <HAL_RCCEx_PeriphCLKConfig+0x30c>
{
/* Get tick */
tickstart = HAL_GetTick();
80036d2: f7fe f82d bl 8001730 <HAL_GetTick>
80036d6: 6178 str r0, [r7, #20]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
80036d8: e014 b.n 8003704 <HAL_RCCEx_PeriphCLKConfig+0x300>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
80036da: f7fe f829 bl 8001730 <HAL_GetTick>
80036de: 4602 mov r2, r0
80036e0: 697b ldr r3, [r7, #20]
80036e2: 1ad3 subs r3, r2, r3
80036e4: f241 3288 movw r2, #5000 ; 0x1388
80036e8: 4293 cmp r3, r2
80036ea: d90b bls.n 8003704 <HAL_RCCEx_PeriphCLKConfig+0x300>
{
return HAL_TIMEOUT;
80036ec: 2303 movs r3, #3
80036ee: e03f b.n 8003770 <HAL_RCCEx_PeriphCLKConfig+0x36c>
80036f0: 42470068 .word 0x42470068
80036f4: 40023800 .word 0x40023800
80036f8: 42470070 .word 0x42470070
80036fc: 40007000 .word 0x40007000
8003700: 42470e40 .word 0x42470e40
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8003704: 4b1c ldr r3, [pc, #112] ; (8003778 <HAL_RCCEx_PeriphCLKConfig+0x374>)
8003706: 6f1b ldr r3, [r3, #112] ; 0x70
8003708: f003 0302 and.w r3, r3, #2
800370c: 2b00 cmp r3, #0
800370e: d0e4 beq.n 80036da <HAL_RCCEx_PeriphCLKConfig+0x2d6>
}
}
}
}
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
8003710: 687b ldr r3, [r7, #4]
8003712: 6a9b ldr r3, [r3, #40] ; 0x28
8003714: f403 7340 and.w r3, r3, #768 ; 0x300
8003718: f5b3 7f40 cmp.w r3, #768 ; 0x300
800371c: d10d bne.n 800373a <HAL_RCCEx_PeriphCLKConfig+0x336>
800371e: 4b16 ldr r3, [pc, #88] ; (8003778 <HAL_RCCEx_PeriphCLKConfig+0x374>)
8003720: 689b ldr r3, [r3, #8]
8003722: f423 12f8 bic.w r2, r3, #2031616 ; 0x1f0000
8003726: 687b ldr r3, [r7, #4]
8003728: 6a9b ldr r3, [r3, #40] ; 0x28
800372a: f023 4370 bic.w r3, r3, #4026531840 ; 0xf0000000
800372e: f423 7340 bic.w r3, r3, #768 ; 0x300
8003732: 4911 ldr r1, [pc, #68] ; (8003778 <HAL_RCCEx_PeriphCLKConfig+0x374>)
8003734: 4313 orrs r3, r2
8003736: 608b str r3, [r1, #8]
8003738: e005 b.n 8003746 <HAL_RCCEx_PeriphCLKConfig+0x342>
800373a: 4b0f ldr r3, [pc, #60] ; (8003778 <HAL_RCCEx_PeriphCLKConfig+0x374>)
800373c: 689b ldr r3, [r3, #8]
800373e: 4a0e ldr r2, [pc, #56] ; (8003778 <HAL_RCCEx_PeriphCLKConfig+0x374>)
8003740: f423 13f8 bic.w r3, r3, #2031616 ; 0x1f0000
8003744: 6093 str r3, [r2, #8]
8003746: 4b0c ldr r3, [pc, #48] ; (8003778 <HAL_RCCEx_PeriphCLKConfig+0x374>)
8003748: 6f1a ldr r2, [r3, #112] ; 0x70
800374a: 687b ldr r3, [r7, #4]
800374c: 6a9b ldr r3, [r3, #40] ; 0x28
800374e: f3c3 030b ubfx r3, r3, #0, #12
8003752: 4909 ldr r1, [pc, #36] ; (8003778 <HAL_RCCEx_PeriphCLKConfig+0x374>)
8003754: 4313 orrs r3, r2
8003756: 670b str r3, [r1, #112] ; 0x70
}
/*--------------------------------------------------------------------------*/
/*---------------------------- TIM configuration ---------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
8003758: 687b ldr r3, [r7, #4]
800375a: 681b ldr r3, [r3, #0]
800375c: f003 0310 and.w r3, r3, #16
8003760: 2b00 cmp r3, #0
8003762: d004 beq.n 800376e <HAL_RCCEx_PeriphCLKConfig+0x36a>
{
__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
8003764: 687b ldr r3, [r7, #4]
8003766: f893 202c ldrb.w r2, [r3, #44] ; 0x2c
800376a: 4b04 ldr r3, [pc, #16] ; (800377c <HAL_RCCEx_PeriphCLKConfig+0x378>)
800376c: 601a str r2, [r3, #0]
}
return HAL_OK;
800376e: 2300 movs r3, #0
}
8003770: 4618 mov r0, r3
8003772: 3718 adds r7, #24
8003774: 46bd mov sp, r7
8003776: bd80 pop {r7, pc}
8003778: 40023800 .word 0x40023800
800377c: 424711e0 .word 0x424711e0
08003780 <HAL_RNG_Init>:
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
{
8003780: b580 push {r7, lr}
8003782: b082 sub sp, #8
8003784: af00 add r7, sp, #0
8003786: 6078 str r0, [r7, #4]
/* Check the RNG handle allocation */
if (hrng == NULL)
8003788: 687b ldr r3, [r7, #4]
800378a: 2b00 cmp r3, #0
800378c: d101 bne.n 8003792 <HAL_RNG_Init+0x12>
{
return HAL_ERROR;
800378e: 2301 movs r3, #1
8003790: e01c b.n 80037cc <HAL_RNG_Init+0x4c>
/* Init the low level hardware */
hrng->MspInitCallback(hrng);
}
#else
if (hrng->State == HAL_RNG_STATE_RESET)
8003792: 687b ldr r3, [r7, #4]
8003794: 795b ldrb r3, [r3, #5]
8003796: b2db uxtb r3, r3
8003798: 2b00 cmp r3, #0
800379a: d105 bne.n 80037a8 <HAL_RNG_Init+0x28>
{
/* Allocate lock resource and initialize it */
hrng->Lock = HAL_UNLOCKED;
800379c: 687b ldr r3, [r7, #4]
800379e: 2200 movs r2, #0
80037a0: 711a strb r2, [r3, #4]
/* Init the low level hardware */
HAL_RNG_MspInit(hrng);
80037a2: 6878 ldr r0, [r7, #4]
80037a4: f7fd fcf0 bl 8001188 <HAL_RNG_MspInit>
}
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
/* Change RNG peripheral state */
hrng->State = HAL_RNG_STATE_BUSY;
80037a8: 687b ldr r3, [r7, #4]
80037aa: 2202 movs r2, #2
80037ac: 715a strb r2, [r3, #5]
/* Enable the RNG Peripheral */
__HAL_RNG_ENABLE(hrng);
80037ae: 687b ldr r3, [r7, #4]
80037b0: 681b ldr r3, [r3, #0]
80037b2: 681a ldr r2, [r3, #0]
80037b4: 687b ldr r3, [r7, #4]
80037b6: 681b ldr r3, [r3, #0]
80037b8: f042 0204 orr.w r2, r2, #4
80037bc: 601a str r2, [r3, #0]
/* Initialize the RNG state */
hrng->State = HAL_RNG_STATE_READY;
80037be: 687b ldr r3, [r7, #4]
80037c0: 2201 movs r2, #1
80037c2: 715a strb r2, [r3, #5]
/* Initialise the error code */
hrng->ErrorCode = HAL_RNG_ERROR_NONE;
80037c4: 687b ldr r3, [r7, #4]
80037c6: 2200 movs r2, #0
80037c8: 609a str r2, [r3, #8]
/* Return function status */
return HAL_OK;
80037ca: 2300 movs r3, #0
}
80037cc: 4618 mov r0, r3
80037ce: 3708 adds r7, #8
80037d0: 46bd mov sp, r7
80037d2: bd80 pop {r7, pc}
080037d4 <HAL_RNG_IRQHandler>:
* the configuration information for RNG.
* @retval None
*/
void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
{
80037d4: b580 push {r7, lr}
80037d6: b084 sub sp, #16
80037d8: af00 add r7, sp, #0
80037da: 6078 str r0, [r7, #4]
uint32_t rngclockerror = 0U;
80037dc: 2300 movs r3, #0
80037de: 60fb str r3, [r7, #12]
/* RNG clock error interrupt occurred */
if (__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET)
80037e0: 687b ldr r3, [r7, #4]
80037e2: 681b ldr r3, [r3, #0]
80037e4: 685b ldr r3, [r3, #4]
80037e6: f003 0320 and.w r3, r3, #32
80037ea: 2b20 cmp r3, #32
80037ec: d105 bne.n 80037fa <HAL_RNG_IRQHandler+0x26>
{
/* Update the error code */
hrng->ErrorCode = HAL_RNG_ERROR_CLOCK;
80037ee: 687b ldr r3, [r7, #4]
80037f0: 2210 movs r2, #16
80037f2: 609a str r2, [r3, #8]
rngclockerror = 1U;
80037f4: 2301 movs r3, #1
80037f6: 60fb str r3, [r7, #12]
80037f8: e00b b.n 8003812 <HAL_RNG_IRQHandler+0x3e>
}
else if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)
80037fa: 687b ldr r3, [r7, #4]
80037fc: 681b ldr r3, [r3, #0]
80037fe: 685b ldr r3, [r3, #4]
8003800: f003 0340 and.w r3, r3, #64 ; 0x40
8003804: 2b40 cmp r3, #64 ; 0x40
8003806: d104 bne.n 8003812 <HAL_RNG_IRQHandler+0x3e>
{
/* Update the error code */
hrng->ErrorCode = HAL_RNG_ERROR_SEED;
8003808: 687b ldr r3, [r7, #4]
800380a: 2208 movs r2, #8
800380c: 609a str r2, [r3, #8]
rngclockerror = 1U;
800380e: 2301 movs r3, #1
8003810: 60fb str r3, [r7, #12]
else
{
/* Nothing to do */
}
if (rngclockerror == 1U)
8003812: 68fb ldr r3, [r7, #12]
8003814: 2b01 cmp r3, #1
8003816: d10a bne.n 800382e <HAL_RNG_IRQHandler+0x5a>
{
/* Change RNG peripheral state */
hrng->State = HAL_RNG_STATE_ERROR;
8003818: 687b ldr r3, [r7, #4]
800381a: 2204 movs r2, #4
800381c: 715a strb r2, [r3, #5]
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
/* Call registered Error callback */
hrng->ErrorCallback(hrng);
#else
/* Call legacy weak Error callback */
HAL_RNG_ErrorCallback(hrng);
800381e: 6878 ldr r0, [r7, #4]
8003820: f000 f839 bl 8003896 <HAL_RNG_ErrorCallback>
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
/* Clear the clock error flag */
__HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI | RNG_IT_SEI);
8003824: 687b ldr r3, [r7, #4]
8003826: 681b ldr r3, [r3, #0]
8003828: f06f 0260 mvn.w r2, #96 ; 0x60
800382c: 605a str r2, [r3, #4]
}
/* Check RNG data ready interrupt occurred */
if (__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET)
800382e: 687b ldr r3, [r7, #4]
8003830: 681b ldr r3, [r3, #0]
8003832: 685b ldr r3, [r3, #4]
8003834: f003 0301 and.w r3, r3, #1
8003838: 2b01 cmp r3, #1
800383a: d11d bne.n 8003878 <HAL_RNG_IRQHandler+0xa4>
{
/* Generate random number once, so disable the IT */
__HAL_RNG_DISABLE_IT(hrng);
800383c: 687b ldr r3, [r7, #4]
800383e: 681b ldr r3, [r3, #0]
8003840: 681a ldr r2, [r3, #0]
8003842: 687b ldr r3, [r7, #4]
8003844: 681b ldr r3, [r3, #0]
8003846: f022 0208 bic.w r2, r2, #8
800384a: 601a str r2, [r3, #0]
/* Get the 32bit Random number (DRDY flag automatically cleared) */
hrng->RandomNumber = hrng->Instance->DR;
800384c: 687b ldr r3, [r7, #4]
800384e: 681b ldr r3, [r3, #0]
8003850: 689a ldr r2, [r3, #8]
8003852: 687b ldr r3, [r7, #4]
8003854: 60da str r2, [r3, #12]
if (hrng->State != HAL_RNG_STATE_ERROR)
8003856: 687b ldr r3, [r7, #4]
8003858: 795b ldrb r3, [r3, #5]
800385a: b2db uxtb r3, r3
800385c: 2b04 cmp r3, #4
800385e: d00b beq.n 8003878 <HAL_RNG_IRQHandler+0xa4>
{
/* Change RNG peripheral state */
hrng->State = HAL_RNG_STATE_READY;
8003860: 687b ldr r3, [r7, #4]
8003862: 2201 movs r2, #1
8003864: 715a strb r2, [r3, #5]
/* Process Unlocked */
__HAL_UNLOCK(hrng);
8003866: 687b ldr r3, [r7, #4]
8003868: 2200 movs r2, #0
800386a: 711a strb r2, [r3, #4]
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
/* Call registered Data Ready callback */
hrng->ReadyDataCallback(hrng, hrng->RandomNumber);
#else
/* Call legacy weak Data Ready callback */
HAL_RNG_ReadyDataCallback(hrng, hrng->RandomNumber);
800386c: 687b ldr r3, [r7, #4]
800386e: 68db ldr r3, [r3, #12]
8003870: 4619 mov r1, r3
8003872: 6878 ldr r0, [r7, #4]
8003874: f000 f804 bl 8003880 <HAL_RNG_ReadyDataCallback>
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
}
}
}
8003878: bf00 nop
800387a: 3710 adds r7, #16
800387c: 46bd mov sp, r7
800387e: bd80 pop {r7, pc}
08003880 <HAL_RNG_ReadyDataCallback>:
* the configuration information for RNG.
* @param random32bit generated random number.
* @retval None
*/
__weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit)
{
8003880: b480 push {r7}
8003882: b083 sub sp, #12
8003884: af00 add r7, sp, #0
8003886: 6078 str r0, [r7, #4]
8003888: 6039 str r1, [r7, #0]
UNUSED(hrng);
UNUSED(random32bit);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_RNG_ReadyDataCallback must be implemented in the user file.
*/
}
800388a: bf00 nop
800388c: 370c adds r7, #12
800388e: 46bd mov sp, r7
8003890: f85d 7b04 ldr.w r7, [sp], #4
8003894: 4770 bx lr
08003896 <HAL_RNG_ErrorCallback>:
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval None
*/
__weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng)
{
8003896: b480 push {r7}
8003898: b083 sub sp, #12
800389a: af00 add r7, sp, #0
800389c: 6078 str r0, [r7, #4]
/* Prevent unused argument(s) compilation warning */
UNUSED(hrng);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_RNG_ErrorCallback must be implemented in the user file.
*/
}
800389e: bf00 nop
80038a0: 370c adds r7, #12
80038a2: 46bd mov sp, r7
80038a4: f85d 7b04 ldr.w r7, [sp], #4
80038a8: 4770 bx lr
080038aa <HAL_SDRAM_Init>:
* the configuration information for SDRAM module.
* @param Timing Pointer to SDRAM control timing structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
{
80038aa: b580 push {r7, lr}
80038ac: b082 sub sp, #8
80038ae: af00 add r7, sp, #0
80038b0: 6078 str r0, [r7, #4]
80038b2: 6039 str r1, [r7, #0]
/* Check the SDRAM handle parameter */
if(hsdram == NULL)
80038b4: 687b ldr r3, [r7, #4]
80038b6: 2b00 cmp r3, #0
80038b8: d101 bne.n 80038be <HAL_SDRAM_Init+0x14>
{
return HAL_ERROR;
80038ba: 2301 movs r3, #1
80038bc: e025 b.n 800390a <HAL_SDRAM_Init+0x60>
}
if(hsdram->State == HAL_SDRAM_STATE_RESET)
80038be: 687b ldr r3, [r7, #4]
80038c0: f893 302c ldrb.w r3, [r3, #44] ; 0x2c
80038c4: b2db uxtb r3, r3
80038c6: 2b00 cmp r3, #0
80038c8: d106 bne.n 80038d8 <HAL_SDRAM_Init+0x2e>
{
/* Allocate lock resource and initialize it */
hsdram->Lock = HAL_UNLOCKED;
80038ca: 687b ldr r3, [r7, #4]
80038cc: 2200 movs r2, #0
80038ce: f883 202d strb.w r2, [r3, #45] ; 0x2d
/* Init the low level hardware */
hsdram->MspInitCallback(hsdram);
#else
/* Initialize the low level hardware (MSP) */
HAL_SDRAM_MspInit(hsdram);
80038d2: 6878 ldr r0, [r7, #4]
80038d4: f7fd fdfa bl 80014cc <HAL_SDRAM_MspInit>
#endif
}
/* Initialize the SDRAM controller state */
hsdram->State = HAL_SDRAM_STATE_BUSY;
80038d8: 687b ldr r3, [r7, #4]
80038da: 2202 movs r2, #2
80038dc: f883 202c strb.w r2, [r3, #44] ; 0x2c
/* Initialize SDRAM control Interface */
FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));
80038e0: 687b ldr r3, [r7, #4]
80038e2: 681a ldr r2, [r3, #0]
80038e4: 687b ldr r3, [r7, #4]
80038e6: 3304 adds r3, #4
80038e8: 4619 mov r1, r3
80038ea: 4610 mov r0, r2
80038ec: f001 f840 bl 8004970 <FMC_SDRAM_Init>
/* Initialize SDRAM timing Interface */
FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank);
80038f0: 687b ldr r3, [r7, #4]
80038f2: 6818 ldr r0, [r3, #0]
80038f4: 687b ldr r3, [r7, #4]
80038f6: 685b ldr r3, [r3, #4]
80038f8: 461a mov r2, r3
80038fa: 6839 ldr r1, [r7, #0]
80038fc: f001 f8ab bl 8004a56 <FMC_SDRAM_Timing_Init>
/* Update the SDRAM controller state */
hsdram->State = HAL_SDRAM_STATE_READY;
8003900: 687b ldr r3, [r7, #4]
8003902: 2201 movs r2, #1
8003904: f883 202c strb.w r2, [r3, #44] ; 0x2c
return HAL_OK;
8003908: 2300 movs r3, #0
}
800390a: 4618 mov r0, r3
800390c: 3708 adds r7, #8
800390e: 46bd mov sp, r7
8003910: bd80 pop {r7, pc}
08003912 <HAL_SPI_Init>:
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
{
8003912: b580 push {r7, lr}
8003914: b082 sub sp, #8
8003916: af00 add r7, sp, #0
8003918: 6078 str r0, [r7, #4]
/* Check the SPI handle allocation */
if (hspi == NULL)
800391a: 687b ldr r3, [r7, #4]
800391c: 2b00 cmp r3, #0
800391e: d101 bne.n 8003924 <HAL_SPI_Init+0x12>
{
return HAL_ERROR;
8003920: 2301 movs r3, #1
8003922: e056 b.n 80039d2 <HAL_SPI_Init+0xc0>
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
}
#else
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
8003924: 687b ldr r3, [r7, #4]
8003926: 2200 movs r2, #0
8003928: 629a str r2, [r3, #40] ; 0x28
#endif /* USE_SPI_CRC */
if (hspi->State == HAL_SPI_STATE_RESET)
800392a: 687b ldr r3, [r7, #4]
800392c: f893 3051 ldrb.w r3, [r3, #81] ; 0x51
8003930: b2db uxtb r3, r3
8003932: 2b00 cmp r3, #0
8003934: d106 bne.n 8003944 <HAL_SPI_Init+0x32>
{
/* Allocate lock resource and initialize it */
hspi->Lock = HAL_UNLOCKED;
8003936: 687b ldr r3, [r7, #4]
8003938: 2200 movs r2, #0
800393a: f883 2050 strb.w r2, [r3, #80] ; 0x50
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
hspi->MspInitCallback(hspi);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_SPI_MspInit(hspi);
800393e: 6878 ldr r0, [r7, #4]
8003940: f7fd fc4a bl 80011d8 <HAL_SPI_MspInit>
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
hspi->State = HAL_SPI_STATE_BUSY;
8003944: 687b ldr r3, [r7, #4]
8003946: 2202 movs r2, #2
8003948: f883 2051 strb.w r2, [r3, #81] ; 0x51
/* Disable the selected SPI peripheral */
__HAL_SPI_DISABLE(hspi);
800394c: 687b ldr r3, [r7, #4]
800394e: 681b ldr r3, [r3, #0]
8003950: 681a ldr r2, [r3, #0]
8003952: 687b ldr r3, [r7, #4]
8003954: 681b ldr r3, [r3, #0]
8003956: f022 0240 bic.w r2, r2, #64 ; 0x40
800395a: 601a str r2, [r3, #0]
/*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
/* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
Communication speed, First bit and CRC calculation state */
WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize |
800395c: 687b ldr r3, [r7, #4]
800395e: 685a ldr r2, [r3, #4]
8003960: 687b ldr r3, [r7, #4]
8003962: 689b ldr r3, [r3, #8]
8003964: 431a orrs r2, r3
8003966: 687b ldr r3, [r7, #4]
8003968: 68db ldr r3, [r3, #12]
800396a: 431a orrs r2, r3
800396c: 687b ldr r3, [r7, #4]
800396e: 691b ldr r3, [r3, #16]
8003970: 431a orrs r2, r3
8003972: 687b ldr r3, [r7, #4]
8003974: 695b ldr r3, [r3, #20]
8003976: 431a orrs r2, r3
8003978: 687b ldr r3, [r7, #4]
800397a: 699b ldr r3, [r3, #24]
800397c: f403 7300 and.w r3, r3, #512 ; 0x200
8003980: 431a orrs r2, r3
8003982: 687b ldr r3, [r7, #4]
8003984: 69db ldr r3, [r3, #28]
8003986: 431a orrs r2, r3
8003988: 687b ldr r3, [r7, #4]
800398a: 6a1b ldr r3, [r3, #32]
800398c: ea42 0103 orr.w r1, r2, r3
8003990: 687b ldr r3, [r7, #4]
8003992: 6a9a ldr r2, [r3, #40] ; 0x28
8003994: 687b ldr r3, [r7, #4]
8003996: 681b ldr r3, [r3, #0]
8003998: 430a orrs r2, r1
800399a: 601a str r2, [r3, #0]
hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation));
/* Configure : NSS management, TI Mode */
WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode));
800399c: 687b ldr r3, [r7, #4]
800399e: 699b ldr r3, [r3, #24]
80039a0: 0c1b lsrs r3, r3, #16
80039a2: f003 0104 and.w r1, r3, #4
80039a6: 687b ldr r3, [r7, #4]
80039a8: 6a5a ldr r2, [r3, #36] ; 0x24
80039aa: 687b ldr r3, [r7, #4]
80039ac: 681b ldr r3, [r3, #0]
80039ae: 430a orrs r2, r1
80039b0: 605a str r2, [r3, #4]
}
#endif /* USE_SPI_CRC */
#if defined(SPI_I2SCFGR_I2SMOD)
/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
80039b2: 687b ldr r3, [r7, #4]
80039b4: 681b ldr r3, [r3, #0]
80039b6: 69da ldr r2, [r3, #28]
80039b8: 687b ldr r3, [r7, #4]
80039ba: 681b ldr r3, [r3, #0]
80039bc: f422 6200 bic.w r2, r2, #2048 ; 0x800
80039c0: 61da str r2, [r3, #28]
#endif /* SPI_I2SCFGR_I2SMOD */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
80039c2: 687b ldr r3, [r7, #4]
80039c4: 2200 movs r2, #0
80039c6: 655a str r2, [r3, #84] ; 0x54
hspi->State = HAL_SPI_STATE_READY;
80039c8: 687b ldr r3, [r7, #4]
80039ca: 2201 movs r2, #1
80039cc: f883 2051 strb.w r2, [r3, #81] ; 0x51
return HAL_OK;
80039d0: 2300 movs r3, #0
}
80039d2: 4618 mov r0, r3
80039d4: 3708 adds r7, #8
80039d6: 46bd mov sp, r7
80039d8: bd80 pop {r7, pc}
080039da <HAL_TIM_Base_Init>:
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
80039da: b580 push {r7, lr}
80039dc: b082 sub sp, #8
80039de: af00 add r7, sp, #0
80039e0: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
80039e2: 687b ldr r3, [r7, #4]
80039e4: 2b00 cmp r3, #0
80039e6: d101 bne.n 80039ec <HAL_TIM_Base_Init+0x12>
{
return HAL_ERROR;
80039e8: 2301 movs r3, #1
80039ea: e01d b.n 8003a28 <HAL_TIM_Base_Init+0x4e>
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
80039ec: 687b ldr r3, [r7, #4]
80039ee: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
80039f2: b2db uxtb r3, r3
80039f4: 2b00 cmp r3, #0
80039f6: d106 bne.n 8003a06 <HAL_TIM_Base_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
80039f8: 687b ldr r3, [r7, #4]
80039fa: 2200 movs r2, #0
80039fc: f883 203c strb.w r2, [r3, #60] ; 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->Base_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
8003a00: 6878 ldr r0, [r7, #4]
8003a02: f7fd fc67 bl 80012d4 <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8003a06: 687b ldr r3, [r7, #4]
8003a08: 2202 movs r2, #2
8003a0a: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8003a0e: 687b ldr r3, [r7, #4]
8003a10: 681a ldr r2, [r3, #0]
8003a12: 687b ldr r3, [r7, #4]
8003a14: 3304 adds r3, #4
8003a16: 4619 mov r1, r3
8003a18: 4610 mov r0, r2
8003a1a: f000 fa15 bl 8003e48 <TIM_Base_SetConfig>
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8003a1e: 687b ldr r3, [r7, #4]
8003a20: 2201 movs r2, #1
8003a22: f883 203d strb.w r2, [r3, #61] ; 0x3d
return HAL_OK;
8003a26: 2300 movs r3, #0
}
8003a28: 4618 mov r0, r3
8003a2a: 3708 adds r7, #8
8003a2c: 46bd mov sp, r7
8003a2e: bd80 pop {r7, pc}
08003a30 <HAL_TIM_Base_Start_IT>:
* @brief Starts the TIM Base generation in interrupt mode.
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
{
8003a30: b480 push {r7}
8003a32: b085 sub sp, #20
8003a34: af00 add r7, sp, #0
8003a36: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
/* Enable the TIM Update interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
8003a38: 687b ldr r3, [r7, #4]
8003a3a: 681b ldr r3, [r3, #0]
8003a3c: 68da ldr r2, [r3, #12]
8003a3e: 687b ldr r3, [r7, #4]
8003a40: 681b ldr r3, [r3, #0]
8003a42: f042 0201 orr.w r2, r2, #1
8003a46: 60da str r2, [r3, #12]
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
8003a48: 687b ldr r3, [r7, #4]
8003a4a: 681b ldr r3, [r3, #0]
8003a4c: 689b ldr r3, [r3, #8]
8003a4e: f003 0307 and.w r3, r3, #7
8003a52: 60fb str r3, [r7, #12]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8003a54: 68fb ldr r3, [r7, #12]
8003a56: 2b06 cmp r3, #6
8003a58: d007 beq.n 8003a6a <HAL_TIM_Base_Start_IT+0x3a>
{
__HAL_TIM_ENABLE(htim);
8003a5a: 687b ldr r3, [r7, #4]
8003a5c: 681b ldr r3, [r3, #0]
8003a5e: 681a ldr r2, [r3, #0]
8003a60: 687b ldr r3, [r7, #4]
8003a62: 681b ldr r3, [r3, #0]
8003a64: f042 0201 orr.w r2, r2, #1
8003a68: 601a str r2, [r3, #0]
}
/* Return function status */
return HAL_OK;
8003a6a: 2300 movs r3, #0
}
8003a6c: 4618 mov r0, r3
8003a6e: 3714 adds r7, #20
8003a70: 46bd mov sp, r7
8003a72: f85d 7b04 ldr.w r7, [sp], #4
8003a76: 4770 bx lr
08003a78 <HAL_TIM_IRQHandler>:
* @brief This function handles TIM interrupts requests.
* @param htim TIM handle
* @retval None
*/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
8003a78: b580 push {r7, lr}
8003a7a: b082 sub sp, #8
8003a7c: af00 add r7, sp, #0
8003a7e: 6078 str r0, [r7, #4]
/* Capture compare 1 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
8003a80: 687b ldr r3, [r7, #4]
8003a82: 681b ldr r3, [r3, #0]
8003a84: 691b ldr r3, [r3, #16]
8003a86: f003 0302 and.w r3, r3, #2
8003a8a: 2b02 cmp r3, #2
8003a8c: d122 bne.n 8003ad4 <HAL_TIM_IRQHandler+0x5c>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
8003a8e: 687b ldr r3, [r7, #4]
8003a90: 681b ldr r3, [r3, #0]
8003a92: 68db ldr r3, [r3, #12]
8003a94: f003 0302 and.w r3, r3, #2
8003a98: 2b02 cmp r3, #2
8003a9a: d11b bne.n 8003ad4 <HAL_TIM_IRQHandler+0x5c>
{
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
8003a9c: 687b ldr r3, [r7, #4]
8003a9e: 681b ldr r3, [r3, #0]
8003aa0: f06f 0202 mvn.w r2, #2
8003aa4: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
8003aa6: 687b ldr r3, [r7, #4]
8003aa8: 2201 movs r2, #1
8003aaa: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
8003aac: 687b ldr r3, [r7, #4]
8003aae: 681b ldr r3, [r3, #0]
8003ab0: 699b ldr r3, [r3, #24]
8003ab2: f003 0303 and.w r3, r3, #3
8003ab6: 2b00 cmp r3, #0
8003ab8: d003 beq.n 8003ac2 <HAL_TIM_IRQHandler+0x4a>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8003aba: 6878 ldr r0, [r7, #4]
8003abc: f000 f9a5 bl 8003e0a <HAL_TIM_IC_CaptureCallback>
8003ac0: e005 b.n 8003ace <HAL_TIM_IRQHandler+0x56>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8003ac2: 6878 ldr r0, [r7, #4]
8003ac4: f000 f997 bl 8003df6 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8003ac8: 6878 ldr r0, [r7, #4]
8003aca: f000 f9a8 bl 8003e1e <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8003ace: 687b ldr r3, [r7, #4]
8003ad0: 2200 movs r2, #0
8003ad2: 771a strb r2, [r3, #28]
}
}
}
/* Capture compare 2 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
8003ad4: 687b ldr r3, [r7, #4]
8003ad6: 681b ldr r3, [r3, #0]
8003ad8: 691b ldr r3, [r3, #16]
8003ada: f003 0304 and.w r3, r3, #4
8003ade: 2b04 cmp r3, #4
8003ae0: d122 bne.n 8003b28 <HAL_TIM_IRQHandler+0xb0>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
8003ae2: 687b ldr r3, [r7, #4]
8003ae4: 681b ldr r3, [r3, #0]
8003ae6: 68db ldr r3, [r3, #12]
8003ae8: f003 0304 and.w r3, r3, #4
8003aec: 2b04 cmp r3, #4
8003aee: d11b bne.n 8003b28 <HAL_TIM_IRQHandler+0xb0>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
8003af0: 687b ldr r3, [r7, #4]
8003af2: 681b ldr r3, [r3, #0]
8003af4: f06f 0204 mvn.w r2, #4
8003af8: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
8003afa: 687b ldr r3, [r7, #4]
8003afc: 2202 movs r2, #2
8003afe: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
8003b00: 687b ldr r3, [r7, #4]
8003b02: 681b ldr r3, [r3, #0]
8003b04: 699b ldr r3, [r3, #24]
8003b06: f403 7340 and.w r3, r3, #768 ; 0x300
8003b0a: 2b00 cmp r3, #0
8003b0c: d003 beq.n 8003b16 <HAL_TIM_IRQHandler+0x9e>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8003b0e: 6878 ldr r0, [r7, #4]
8003b10: f000 f97b bl 8003e0a <HAL_TIM_IC_CaptureCallback>
8003b14: e005 b.n 8003b22 <HAL_TIM_IRQHandler+0xaa>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8003b16: 6878 ldr r0, [r7, #4]
8003b18: f000 f96d bl 8003df6 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8003b1c: 6878 ldr r0, [r7, #4]
8003b1e: f000 f97e bl 8003e1e <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8003b22: 687b ldr r3, [r7, #4]
8003b24: 2200 movs r2, #0
8003b26: 771a strb r2, [r3, #28]
}
}
/* Capture compare 3 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
8003b28: 687b ldr r3, [r7, #4]
8003b2a: 681b ldr r3, [r3, #0]
8003b2c: 691b ldr r3, [r3, #16]
8003b2e: f003 0308 and.w r3, r3, #8
8003b32: 2b08 cmp r3, #8
8003b34: d122 bne.n 8003b7c <HAL_TIM_IRQHandler+0x104>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
8003b36: 687b ldr r3, [r7, #4]
8003b38: 681b ldr r3, [r3, #0]
8003b3a: 68db ldr r3, [r3, #12]
8003b3c: f003 0308 and.w r3, r3, #8
8003b40: 2b08 cmp r3, #8
8003b42: d11b bne.n 8003b7c <HAL_TIM_IRQHandler+0x104>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
8003b44: 687b ldr r3, [r7, #4]
8003b46: 681b ldr r3, [r3, #0]
8003b48: f06f 0208 mvn.w r2, #8
8003b4c: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
8003b4e: 687b ldr r3, [r7, #4]
8003b50: 2204 movs r2, #4
8003b52: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
8003b54: 687b ldr r3, [r7, #4]
8003b56: 681b ldr r3, [r3, #0]
8003b58: 69db ldr r3, [r3, #28]
8003b5a: f003 0303 and.w r3, r3, #3
8003b5e: 2b00 cmp r3, #0
8003b60: d003 beq.n 8003b6a <HAL_TIM_IRQHandler+0xf2>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8003b62: 6878 ldr r0, [r7, #4]
8003b64: f000 f951 bl 8003e0a <HAL_TIM_IC_CaptureCallback>
8003b68: e005 b.n 8003b76 <HAL_TIM_IRQHandler+0xfe>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8003b6a: 6878 ldr r0, [r7, #4]
8003b6c: f000 f943 bl 8003df6 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8003b70: 6878 ldr r0, [r7, #4]
8003b72: f000 f954 bl 8003e1e <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8003b76: 687b ldr r3, [r7, #4]
8003b78: 2200 movs r2, #0
8003b7a: 771a strb r2, [r3, #28]
}
}
/* Capture compare 4 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
8003b7c: 687b ldr r3, [r7, #4]
8003b7e: 681b ldr r3, [r3, #0]
8003b80: 691b ldr r3, [r3, #16]
8003b82: f003 0310 and.w r3, r3, #16
8003b86: 2b10 cmp r3, #16
8003b88: d122 bne.n 8003bd0 <HAL_TIM_IRQHandler+0x158>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
8003b8a: 687b ldr r3, [r7, #4]
8003b8c: 681b ldr r3, [r3, #0]
8003b8e: 68db ldr r3, [r3, #12]
8003b90: f003 0310 and.w r3, r3, #16
8003b94: 2b10 cmp r3, #16
8003b96: d11b bne.n 8003bd0 <HAL_TIM_IRQHandler+0x158>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
8003b98: 687b ldr r3, [r7, #4]
8003b9a: 681b ldr r3, [r3, #0]
8003b9c: f06f 0210 mvn.w r2, #16
8003ba0: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
8003ba2: 687b ldr r3, [r7, #4]
8003ba4: 2208 movs r2, #8
8003ba6: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
8003ba8: 687b ldr r3, [r7, #4]
8003baa: 681b ldr r3, [r3, #0]
8003bac: 69db ldr r3, [r3, #28]
8003bae: f403 7340 and.w r3, r3, #768 ; 0x300
8003bb2: 2b00 cmp r3, #0
8003bb4: d003 beq.n 8003bbe <HAL_TIM_IRQHandler+0x146>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8003bb6: 6878 ldr r0, [r7, #4]
8003bb8: f000 f927 bl 8003e0a <HAL_TIM_IC_CaptureCallback>
8003bbc: e005 b.n 8003bca <HAL_TIM_IRQHandler+0x152>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8003bbe: 6878 ldr r0, [r7, #4]
8003bc0: f000 f919 bl 8003df6 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8003bc4: 6878 ldr r0, [r7, #4]
8003bc6: f000 f92a bl 8003e1e <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8003bca: 687b ldr r3, [r7, #4]
8003bcc: 2200 movs r2, #0
8003bce: 771a strb r2, [r3, #28]
}
}
/* TIM Update event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
8003bd0: 687b ldr r3, [r7, #4]
8003bd2: 681b ldr r3, [r3, #0]
8003bd4: 691b ldr r3, [r3, #16]
8003bd6: f003 0301 and.w r3, r3, #1
8003bda: 2b01 cmp r3, #1
8003bdc: d10e bne.n 8003bfc <HAL_TIM_IRQHandler+0x184>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
8003bde: 687b ldr r3, [r7, #4]
8003be0: 681b ldr r3, [r3, #0]
8003be2: 68db ldr r3, [r3, #12]
8003be4: f003 0301 and.w r3, r3, #1
8003be8: 2b01 cmp r3, #1
8003bea: d107 bne.n 8003bfc <HAL_TIM_IRQHandler+0x184>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
8003bec: 687b ldr r3, [r7, #4]
8003bee: 681b ldr r3, [r3, #0]
8003bf0: f06f 0201 mvn.w r2, #1
8003bf4: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PeriodElapsedCallback(htim);
#else
HAL_TIM_PeriodElapsedCallback(htim);
8003bf6: 6878 ldr r0, [r7, #4]
8003bf8: f7fd f8b6 bl 8000d68 <HAL_TIM_PeriodElapsedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break input event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
8003bfc: 687b ldr r3, [r7, #4]
8003bfe: 681b ldr r3, [r3, #0]
8003c00: 691b ldr r3, [r3, #16]
8003c02: f003 0380 and.w r3, r3, #128 ; 0x80
8003c06: 2b80 cmp r3, #128 ; 0x80
8003c08: d10e bne.n 8003c28 <HAL_TIM_IRQHandler+0x1b0>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
8003c0a: 687b ldr r3, [r7, #4]
8003c0c: 681b ldr r3, [r3, #0]
8003c0e: 68db ldr r3, [r3, #12]
8003c10: f003 0380 and.w r3, r3, #128 ; 0x80
8003c14: 2b80 cmp r3, #128 ; 0x80
8003c16: d107 bne.n 8003c28 <HAL_TIM_IRQHandler+0x1b0>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
8003c18: 687b ldr r3, [r7, #4]
8003c1a: 681b ldr r3, [r3, #0]
8003c1c: f06f 0280 mvn.w r2, #128 ; 0x80
8003c20: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->BreakCallback(htim);
#else
HAL_TIMEx_BreakCallback(htim);
8003c22: 6878 ldr r0, [r7, #4]
8003c24: f000 fad0 bl 80041c8 <HAL_TIMEx_BreakCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Trigger detection event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
8003c28: 687b ldr r3, [r7, #4]
8003c2a: 681b ldr r3, [r3, #0]
8003c2c: 691b ldr r3, [r3, #16]
8003c2e: f003 0340 and.w r3, r3, #64 ; 0x40
8003c32: 2b40 cmp r3, #64 ; 0x40
8003c34: d10e bne.n 8003c54 <HAL_TIM_IRQHandler+0x1dc>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
8003c36: 687b ldr r3, [r7, #4]
8003c38: 681b ldr r3, [r3, #0]
8003c3a: 68db ldr r3, [r3, #12]
8003c3c: f003 0340 and.w r3, r3, #64 ; 0x40
8003c40: 2b40 cmp r3, #64 ; 0x40
8003c42: d107 bne.n 8003c54 <HAL_TIM_IRQHandler+0x1dc>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
8003c44: 687b ldr r3, [r7, #4]
8003c46: 681b ldr r3, [r3, #0]
8003c48: f06f 0240 mvn.w r2, #64 ; 0x40
8003c4c: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TriggerCallback(htim);
#else
HAL_TIM_TriggerCallback(htim);
8003c4e: 6878 ldr r0, [r7, #4]
8003c50: f000 f8ef bl 8003e32 <HAL_TIM_TriggerCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM commutation event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
8003c54: 687b ldr r3, [r7, #4]
8003c56: 681b ldr r3, [r3, #0]
8003c58: 691b ldr r3, [r3, #16]
8003c5a: f003 0320 and.w r3, r3, #32
8003c5e: 2b20 cmp r3, #32
8003c60: d10e bne.n 8003c80 <HAL_TIM_IRQHandler+0x208>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
8003c62: 687b ldr r3, [r7, #4]
8003c64: 681b ldr r3, [r3, #0]
8003c66: 68db ldr r3, [r3, #12]
8003c68: f003 0320 and.w r3, r3, #32
8003c6c: 2b20 cmp r3, #32
8003c6e: d107 bne.n 8003c80 <HAL_TIM_IRQHandler+0x208>
{
__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
8003c70: 687b ldr r3, [r7, #4]
8003c72: 681b ldr r3, [r3, #0]
8003c74: f06f 0220 mvn.w r2, #32
8003c78: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->CommutationCallback(htim);
#else
HAL_TIMEx_CommutCallback(htim);
8003c7a: 6878 ldr r0, [r7, #4]
8003c7c: f000 fa9a bl 80041b4 <HAL_TIMEx_CommutCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
}
8003c80: bf00 nop
8003c82: 3708 adds r7, #8
8003c84: 46bd mov sp, r7
8003c86: bd80 pop {r7, pc}
08003c88 <HAL_TIM_ConfigClockSource>:
* @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
* contains the clock source information for the TIM peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
{
8003c88: b580 push {r7, lr}
8003c8a: b084 sub sp, #16
8003c8c: af00 add r7, sp, #0
8003c8e: 6078 str r0, [r7, #4]
8003c90: 6039 str r1, [r7, #0]
uint32_t tmpsmcr;
/* Process Locked */
__HAL_LOCK(htim);
8003c92: 687b ldr r3, [r7, #4]
8003c94: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
8003c98: 2b01 cmp r3, #1
8003c9a: d101 bne.n 8003ca0 <HAL_TIM_ConfigClockSource+0x18>
8003c9c: 2302 movs r3, #2
8003c9e: e0a6 b.n 8003dee <HAL_TIM_ConfigClockSource+0x166>
8003ca0: 687b ldr r3, [r7, #4]
8003ca2: 2201 movs r2, #1
8003ca4: f883 203c strb.w r2, [r3, #60] ; 0x3c
htim->State = HAL_TIM_STATE_BUSY;
8003ca8: 687b ldr r3, [r7, #4]
8003caa: 2202 movs r2, #2
8003cac: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Check the parameters */
assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
tmpsmcr = htim->Instance->SMCR;
8003cb0: 687b ldr r3, [r7, #4]
8003cb2: 681b ldr r3, [r3, #0]
8003cb4: 689b ldr r3, [r3, #8]
8003cb6: 60fb str r3, [r7, #12]
tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
8003cb8: 68fb ldr r3, [r7, #12]
8003cba: f023 0377 bic.w r3, r3, #119 ; 0x77
8003cbe: 60fb str r3, [r7, #12]
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
8003cc0: 68fb ldr r3, [r7, #12]
8003cc2: f423 437f bic.w r3, r3, #65280 ; 0xff00
8003cc6: 60fb str r3, [r7, #12]
htim->Instance->SMCR = tmpsmcr;
8003cc8: 687b ldr r3, [r7, #4]
8003cca: 681b ldr r3, [r3, #0]
8003ccc: 68fa ldr r2, [r7, #12]
8003cce: 609a str r2, [r3, #8]
switch (sClockSourceConfig->ClockSource)
8003cd0: 683b ldr r3, [r7, #0]
8003cd2: 681b ldr r3, [r3, #0]
8003cd4: 2b40 cmp r3, #64 ; 0x40
8003cd6: d067 beq.n 8003da8 <HAL_TIM_ConfigClockSource+0x120>
8003cd8: 2b40 cmp r3, #64 ; 0x40
8003cda: d80b bhi.n 8003cf4 <HAL_TIM_ConfigClockSource+0x6c>
8003cdc: 2b10 cmp r3, #16
8003cde: d073 beq.n 8003dc8 <HAL_TIM_ConfigClockSource+0x140>
8003ce0: 2b10 cmp r3, #16
8003ce2: d802 bhi.n 8003cea <HAL_TIM_ConfigClockSource+0x62>
8003ce4: 2b00 cmp r3, #0
8003ce6: d06f beq.n 8003dc8 <HAL_TIM_ConfigClockSource+0x140>
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
break;
}
default:
break;
8003ce8: e078 b.n 8003ddc <HAL_TIM_ConfigClockSource+0x154>
switch (sClockSourceConfig->ClockSource)
8003cea: 2b20 cmp r3, #32
8003cec: d06c beq.n 8003dc8 <HAL_TIM_ConfigClockSource+0x140>
8003cee: 2b30 cmp r3, #48 ; 0x30
8003cf0: d06a beq.n 8003dc8 <HAL_TIM_ConfigClockSource+0x140>
break;
8003cf2: e073 b.n 8003ddc <HAL_TIM_ConfigClockSource+0x154>
switch (sClockSourceConfig->ClockSource)
8003cf4: 2b70 cmp r3, #112 ; 0x70
8003cf6: d00d beq.n 8003d14 <HAL_TIM_ConfigClockSource+0x8c>
8003cf8: 2b70 cmp r3, #112 ; 0x70
8003cfa: d804 bhi.n 8003d06 <HAL_TIM_ConfigClockSource+0x7e>
8003cfc: 2b50 cmp r3, #80 ; 0x50
8003cfe: d033 beq.n 8003d68 <HAL_TIM_ConfigClockSource+0xe0>
8003d00: 2b60 cmp r3, #96 ; 0x60
8003d02: d041 beq.n 8003d88 <HAL_TIM_ConfigClockSource+0x100>
break;
8003d04: e06a b.n 8003ddc <HAL_TIM_ConfigClockSource+0x154>
switch (sClockSourceConfig->ClockSource)
8003d06: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
8003d0a: d066 beq.n 8003dda <HAL_TIM_ConfigClockSource+0x152>
8003d0c: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
8003d10: d017 beq.n 8003d42 <HAL_TIM_ConfigClockSource+0xba>
break;
8003d12: e063 b.n 8003ddc <HAL_TIM_ConfigClockSource+0x154>
TIM_ETR_SetConfig(htim->Instance,
8003d14: 687b ldr r3, [r7, #4]
8003d16: 6818 ldr r0, [r3, #0]
8003d18: 683b ldr r3, [r7, #0]
8003d1a: 6899 ldr r1, [r3, #8]
8003d1c: 683b ldr r3, [r7, #0]
8003d1e: 685a ldr r2, [r3, #4]
8003d20: 683b ldr r3, [r7, #0]
8003d22: 68db ldr r3, [r3, #12]
8003d24: f000 f9aa bl 800407c <TIM_ETR_SetConfig>
tmpsmcr = htim->Instance->SMCR;
8003d28: 687b ldr r3, [r7, #4]
8003d2a: 681b ldr r3, [r3, #0]
8003d2c: 689b ldr r3, [r3, #8]
8003d2e: 60fb str r3, [r7, #12]
tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
8003d30: 68fb ldr r3, [r7, #12]
8003d32: f043 0377 orr.w r3, r3, #119 ; 0x77
8003d36: 60fb str r3, [r7, #12]
htim->Instance->SMCR = tmpsmcr;
8003d38: 687b ldr r3, [r7, #4]
8003d3a: 681b ldr r3, [r3, #0]
8003d3c: 68fa ldr r2, [r7, #12]
8003d3e: 609a str r2, [r3, #8]
break;
8003d40: e04c b.n 8003ddc <HAL_TIM_ConfigClockSource+0x154>
TIM_ETR_SetConfig(htim->Instance,
8003d42: 687b ldr r3, [r7, #4]
8003d44: 6818 ldr r0, [r3, #0]
8003d46: 683b ldr r3, [r7, #0]
8003d48: 6899 ldr r1, [r3, #8]
8003d4a: 683b ldr r3, [r7, #0]
8003d4c: 685a ldr r2, [r3, #4]
8003d4e: 683b ldr r3, [r7, #0]
8003d50: 68db ldr r3, [r3, #12]
8003d52: f000 f993 bl 800407c <TIM_ETR_SetConfig>
htim->Instance->SMCR |= TIM_SMCR_ECE;
8003d56: 687b ldr r3, [r7, #4]
8003d58: 681b ldr r3, [r3, #0]
8003d5a: 689a ldr r2, [r3, #8]
8003d5c: 687b ldr r3, [r7, #4]
8003d5e: 681b ldr r3, [r3, #0]
8003d60: f442 4280 orr.w r2, r2, #16384 ; 0x4000
8003d64: 609a str r2, [r3, #8]
break;
8003d66: e039 b.n 8003ddc <HAL_TIM_ConfigClockSource+0x154>
TIM_TI1_ConfigInputStage(htim->Instance,
8003d68: 687b ldr r3, [r7, #4]
8003d6a: 6818 ldr r0, [r3, #0]
8003d6c: 683b ldr r3, [r7, #0]
8003d6e: 6859 ldr r1, [r3, #4]
8003d70: 683b ldr r3, [r7, #0]
8003d72: 68db ldr r3, [r3, #12]
8003d74: 461a mov r2, r3
8003d76: f000 f907 bl 8003f88 <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
8003d7a: 687b ldr r3, [r7, #4]
8003d7c: 681b ldr r3, [r3, #0]
8003d7e: 2150 movs r1, #80 ; 0x50
8003d80: 4618 mov r0, r3
8003d82: f000 f960 bl 8004046 <TIM_ITRx_SetConfig>
break;
8003d86: e029 b.n 8003ddc <HAL_TIM_ConfigClockSource+0x154>
TIM_TI2_ConfigInputStage(htim->Instance,
8003d88: 687b ldr r3, [r7, #4]
8003d8a: 6818 ldr r0, [r3, #0]
8003d8c: 683b ldr r3, [r7, #0]
8003d8e: 6859 ldr r1, [r3, #4]
8003d90: 683b ldr r3, [r7, #0]
8003d92: 68db ldr r3, [r3, #12]
8003d94: 461a mov r2, r3
8003d96: f000 f926 bl 8003fe6 <TIM_TI2_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
8003d9a: 687b ldr r3, [r7, #4]
8003d9c: 681b ldr r3, [r3, #0]
8003d9e: 2160 movs r1, #96 ; 0x60
8003da0: 4618 mov r0, r3
8003da2: f000 f950 bl 8004046 <TIM_ITRx_SetConfig>
break;
8003da6: e019 b.n 8003ddc <HAL_TIM_ConfigClockSource+0x154>
TIM_TI1_ConfigInputStage(htim->Instance,
8003da8: 687b ldr r3, [r7, #4]
8003daa: 6818 ldr r0, [r3, #0]
8003dac: 683b ldr r3, [r7, #0]
8003dae: 6859 ldr r1, [r3, #4]
8003db0: 683b ldr r3, [r7, #0]
8003db2: 68db ldr r3, [r3, #12]
8003db4: 461a mov r2, r3
8003db6: f000 f8e7 bl 8003f88 <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
8003dba: 687b ldr r3, [r7, #4]
8003dbc: 681b ldr r3, [r3, #0]
8003dbe: 2140 movs r1, #64 ; 0x40
8003dc0: 4618 mov r0, r3
8003dc2: f000 f940 bl 8004046 <TIM_ITRx_SetConfig>
break;
8003dc6: e009 b.n 8003ddc <HAL_TIM_ConfigClockSource+0x154>
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
8003dc8: 687b ldr r3, [r7, #4]
8003dca: 681a ldr r2, [r3, #0]
8003dcc: 683b ldr r3, [r7, #0]
8003dce: 681b ldr r3, [r3, #0]
8003dd0: 4619 mov r1, r3
8003dd2: 4610 mov r0, r2
8003dd4: f000 f937 bl 8004046 <TIM_ITRx_SetConfig>
break;
8003dd8: e000 b.n 8003ddc <HAL_TIM_ConfigClockSource+0x154>
break;
8003dda: bf00 nop
}
htim->State = HAL_TIM_STATE_READY;
8003ddc: 687b ldr r3, [r7, #4]
8003dde: 2201 movs r2, #1
8003de0: f883 203d strb.w r2, [r3, #61] ; 0x3d
__HAL_UNLOCK(htim);
8003de4: 687b ldr r3, [r7, #4]
8003de6: 2200 movs r2, #0
8003de8: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_OK;
8003dec: 2300 movs r3, #0
}
8003dee: 4618 mov r0, r3
8003df0: 3710 adds r7, #16
8003df2: 46bd mov sp, r7
8003df4: bd80 pop {r7, pc}
08003df6 <HAL_TIM_OC_DelayElapsedCallback>:
* @brief Output Compare callback in non-blocking mode
* @param htim TIM OC handle
* @retval None
*/
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
{
8003df6: b480 push {r7}
8003df8: b083 sub sp, #12
8003dfa: af00 add r7, sp, #0
8003dfc: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
*/
}
8003dfe: bf00 nop
8003e00: 370c adds r7, #12
8003e02: 46bd mov sp, r7
8003e04: f85d 7b04 ldr.w r7, [sp], #4
8003e08: 4770 bx lr
08003e0a <HAL_TIM_IC_CaptureCallback>:
* @brief Input Capture callback in non-blocking mode
* @param htim TIM IC handle
* @retval None
*/
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
{
8003e0a: b480 push {r7}
8003e0c: b083 sub sp, #12
8003e0e: af00 add r7, sp, #0
8003e10: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_IC_CaptureCallback could be implemented in the user file
*/
}
8003e12: bf00 nop
8003e14: 370c adds r7, #12
8003e16: 46bd mov sp, r7
8003e18: f85d 7b04 ldr.w r7, [sp], #4
8003e1c: 4770 bx lr
08003e1e <HAL_TIM_PWM_PulseFinishedCallback>:
* @brief PWM Pulse finished callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
{
8003e1e: b480 push {r7}
8003e20: b083 sub sp, #12
8003e22: af00 add r7, sp, #0
8003e24: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
*/
}
8003e26: bf00 nop
8003e28: 370c adds r7, #12
8003e2a: 46bd mov sp, r7
8003e2c: f85d 7b04 ldr.w r7, [sp], #4
8003e30: 4770 bx lr
08003e32 <HAL_TIM_TriggerCallback>:
* @brief Hall Trigger detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
{
8003e32: b480 push {r7}
8003e34: b083 sub sp, #12
8003e36: af00 add r7, sp, #0
8003e38: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_TriggerCallback could be implemented in the user file
*/
}
8003e3a: bf00 nop
8003e3c: 370c adds r7, #12
8003e3e: 46bd mov sp, r7
8003e40: f85d 7b04 ldr.w r7, [sp], #4
8003e44: 4770 bx lr
...
08003e48 <TIM_Base_SetConfig>:
* @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
{
8003e48: b480 push {r7}
8003e4a: b085 sub sp, #20
8003e4c: af00 add r7, sp, #0
8003e4e: 6078 str r0, [r7, #4]
8003e50: 6039 str r1, [r7, #0]
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
8003e52: 687b ldr r3, [r7, #4]
8003e54: 681b ldr r3, [r3, #0]
8003e56: 60fb str r3, [r7, #12]
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
8003e58: 687b ldr r3, [r7, #4]
8003e5a: 4a40 ldr r2, [pc, #256] ; (8003f5c <TIM_Base_SetConfig+0x114>)
8003e5c: 4293 cmp r3, r2
8003e5e: d013 beq.n 8003e88 <TIM_Base_SetConfig+0x40>
8003e60: 687b ldr r3, [r7, #4]
8003e62: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8003e66: d00f beq.n 8003e88 <TIM_Base_SetConfig+0x40>
8003e68: 687b ldr r3, [r7, #4]
8003e6a: 4a3d ldr r2, [pc, #244] ; (8003f60 <TIM_Base_SetConfig+0x118>)
8003e6c: 4293 cmp r3, r2
8003e6e: d00b beq.n 8003e88 <TIM_Base_SetConfig+0x40>
8003e70: 687b ldr r3, [r7, #4]
8003e72: 4a3c ldr r2, [pc, #240] ; (8003f64 <TIM_Base_SetConfig+0x11c>)
8003e74: 4293 cmp r3, r2
8003e76: d007 beq.n 8003e88 <TIM_Base_SetConfig+0x40>
8003e78: 687b ldr r3, [r7, #4]
8003e7a: 4a3b ldr r2, [pc, #236] ; (8003f68 <TIM_Base_SetConfig+0x120>)
8003e7c: 4293 cmp r3, r2
8003e7e: d003 beq.n 8003e88 <TIM_Base_SetConfig+0x40>
8003e80: 687b ldr r3, [r7, #4]
8003e82: 4a3a ldr r2, [pc, #232] ; (8003f6c <TIM_Base_SetConfig+0x124>)
8003e84: 4293 cmp r3, r2
8003e86: d108 bne.n 8003e9a <TIM_Base_SetConfig+0x52>
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
8003e88: 68fb ldr r3, [r7, #12]
8003e8a: f023 0370 bic.w r3, r3, #112 ; 0x70
8003e8e: 60fb str r3, [r7, #12]
tmpcr1 |= Structure->CounterMode;
8003e90: 683b ldr r3, [r7, #0]
8003e92: 685b ldr r3, [r3, #4]
8003e94: 68fa ldr r2, [r7, #12]
8003e96: 4313 orrs r3, r2
8003e98: 60fb str r3, [r7, #12]
}
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
8003e9a: 687b ldr r3, [r7, #4]
8003e9c: 4a2f ldr r2, [pc, #188] ; (8003f5c <TIM_Base_SetConfig+0x114>)
8003e9e: 4293 cmp r3, r2
8003ea0: d02b beq.n 8003efa <TIM_Base_SetConfig+0xb2>
8003ea2: 687b ldr r3, [r7, #4]
8003ea4: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8003ea8: d027 beq.n 8003efa <TIM_Base_SetConfig+0xb2>
8003eaa: 687b ldr r3, [r7, #4]
8003eac: 4a2c ldr r2, [pc, #176] ; (8003f60 <TIM_Base_SetConfig+0x118>)
8003eae: 4293 cmp r3, r2
8003eb0: d023 beq.n 8003efa <TIM_Base_SetConfig+0xb2>
8003eb2: 687b ldr r3, [r7, #4]
8003eb4: 4a2b ldr r2, [pc, #172] ; (8003f64 <TIM_Base_SetConfig+0x11c>)
8003eb6: 4293 cmp r3, r2
8003eb8: d01f beq.n 8003efa <TIM_Base_SetConfig+0xb2>
8003eba: 687b ldr r3, [r7, #4]
8003ebc: 4a2a ldr r2, [pc, #168] ; (8003f68 <TIM_Base_SetConfig+0x120>)
8003ebe: 4293 cmp r3, r2
8003ec0: d01b beq.n 8003efa <TIM_Base_SetConfig+0xb2>
8003ec2: 687b ldr r3, [r7, #4]
8003ec4: 4a29 ldr r2, [pc, #164] ; (8003f6c <TIM_Base_SetConfig+0x124>)
8003ec6: 4293 cmp r3, r2
8003ec8: d017 beq.n 8003efa <TIM_Base_SetConfig+0xb2>
8003eca: 687b ldr r3, [r7, #4]
8003ecc: 4a28 ldr r2, [pc, #160] ; (8003f70 <TIM_Base_SetConfig+0x128>)
8003ece: 4293 cmp r3, r2
8003ed0: d013 beq.n 8003efa <TIM_Base_SetConfig+0xb2>
8003ed2: 687b ldr r3, [r7, #4]
8003ed4: 4a27 ldr r2, [pc, #156] ; (8003f74 <TIM_Base_SetConfig+0x12c>)
8003ed6: 4293 cmp r3, r2
8003ed8: d00f beq.n 8003efa <TIM_Base_SetConfig+0xb2>
8003eda: 687b ldr r3, [r7, #4]
8003edc: 4a26 ldr r2, [pc, #152] ; (8003f78 <TIM_Base_SetConfig+0x130>)
8003ede: 4293 cmp r3, r2
8003ee0: d00b beq.n 8003efa <TIM_Base_SetConfig+0xb2>
8003ee2: 687b ldr r3, [r7, #4]
8003ee4: 4a25 ldr r2, [pc, #148] ; (8003f7c <TIM_Base_SetConfig+0x134>)
8003ee6: 4293 cmp r3, r2
8003ee8: d007 beq.n 8003efa <TIM_Base_SetConfig+0xb2>
8003eea: 687b ldr r3, [r7, #4]
8003eec: 4a24 ldr r2, [pc, #144] ; (8003f80 <TIM_Base_SetConfig+0x138>)
8003eee: 4293 cmp r3, r2
8003ef0: d003 beq.n 8003efa <TIM_Base_SetConfig+0xb2>
8003ef2: 687b ldr r3, [r7, #4]
8003ef4: 4a23 ldr r2, [pc, #140] ; (8003f84 <TIM_Base_SetConfig+0x13c>)
8003ef6: 4293 cmp r3, r2
8003ef8: d108 bne.n 8003f0c <TIM_Base_SetConfig+0xc4>
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
8003efa: 68fb ldr r3, [r7, #12]
8003efc: f423 7340 bic.w r3, r3, #768 ; 0x300
8003f00: 60fb str r3, [r7, #12]
tmpcr1 |= (uint32_t)Structure->ClockDivision;
8003f02: 683b ldr r3, [r7, #0]
8003f04: 68db ldr r3, [r3, #12]
8003f06: 68fa ldr r2, [r7, #12]
8003f08: 4313 orrs r3, r2
8003f0a: 60fb str r3, [r7, #12]
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
8003f0c: 68fb ldr r3, [r7, #12]
8003f0e: f023 0280 bic.w r2, r3, #128 ; 0x80
8003f12: 683b ldr r3, [r7, #0]
8003f14: 695b ldr r3, [r3, #20]
8003f16: 4313 orrs r3, r2
8003f18: 60fb str r3, [r7, #12]
TIMx->CR1 = tmpcr1;
8003f1a: 687b ldr r3, [r7, #4]
8003f1c: 68fa ldr r2, [r7, #12]
8003f1e: 601a str r2, [r3, #0]
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
8003f20: 683b ldr r3, [r7, #0]
8003f22: 689a ldr r2, [r3, #8]
8003f24: 687b ldr r3, [r7, #4]
8003f26: 62da str r2, [r3, #44] ; 0x2c
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
8003f28: 683b ldr r3, [r7, #0]
8003f2a: 681a ldr r2, [r3, #0]
8003f2c: 687b ldr r3, [r7, #4]
8003f2e: 629a str r2, [r3, #40] ; 0x28
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
8003f30: 687b ldr r3, [r7, #4]
8003f32: 4a0a ldr r2, [pc, #40] ; (8003f5c <TIM_Base_SetConfig+0x114>)
8003f34: 4293 cmp r3, r2
8003f36: d003 beq.n 8003f40 <TIM_Base_SetConfig+0xf8>
8003f38: 687b ldr r3, [r7, #4]
8003f3a: 4a0c ldr r2, [pc, #48] ; (8003f6c <TIM_Base_SetConfig+0x124>)
8003f3c: 4293 cmp r3, r2
8003f3e: d103 bne.n 8003f48 <TIM_Base_SetConfig+0x100>
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
8003f40: 683b ldr r3, [r7, #0]
8003f42: 691a ldr r2, [r3, #16]
8003f44: 687b ldr r3, [r7, #4]
8003f46: 631a str r2, [r3, #48] ; 0x30
}
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
8003f48: 687b ldr r3, [r7, #4]
8003f4a: 2201 movs r2, #1
8003f4c: 615a str r2, [r3, #20]
}
8003f4e: bf00 nop
8003f50: 3714 adds r7, #20
8003f52: 46bd mov sp, r7
8003f54: f85d 7b04 ldr.w r7, [sp], #4
8003f58: 4770 bx lr
8003f5a: bf00 nop
8003f5c: 40010000 .word 0x40010000
8003f60: 40000400 .word 0x40000400
8003f64: 40000800 .word 0x40000800
8003f68: 40000c00 .word 0x40000c00
8003f6c: 40010400 .word 0x40010400
8003f70: 40014000 .word 0x40014000
8003f74: 40014400 .word 0x40014400
8003f78: 40014800 .word 0x40014800
8003f7c: 40001800 .word 0x40001800
8003f80: 40001c00 .word 0x40001c00
8003f84: 40002000 .word 0x40002000
08003f88 <TIM_TI1_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
8003f88: b480 push {r7}
8003f8a: b087 sub sp, #28
8003f8c: af00 add r7, sp, #0
8003f8e: 60f8 str r0, [r7, #12]
8003f90: 60b9 str r1, [r7, #8]
8003f92: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 1: Reset the CC1E Bit */
tmpccer = TIMx->CCER;
8003f94: 68fb ldr r3, [r7, #12]
8003f96: 6a1b ldr r3, [r3, #32]
8003f98: 617b str r3, [r7, #20]
TIMx->CCER &= ~TIM_CCER_CC1E;
8003f9a: 68fb ldr r3, [r7, #12]
8003f9c: 6a1b ldr r3, [r3, #32]
8003f9e: f023 0201 bic.w r2, r3, #1
8003fa2: 68fb ldr r3, [r7, #12]
8003fa4: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
8003fa6: 68fb ldr r3, [r7, #12]
8003fa8: 699b ldr r3, [r3, #24]
8003faa: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC1F;
8003fac: 693b ldr r3, [r7, #16]
8003fae: f023 03f0 bic.w r3, r3, #240 ; 0xf0
8003fb2: 613b str r3, [r7, #16]
tmpccmr1 |= (TIM_ICFilter << 4U);
8003fb4: 687b ldr r3, [r7, #4]
8003fb6: 011b lsls r3, r3, #4
8003fb8: 693a ldr r2, [r7, #16]
8003fba: 4313 orrs r3, r2
8003fbc: 613b str r3, [r7, #16]
/* Select the Polarity and set the CC1E Bit */
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
8003fbe: 697b ldr r3, [r7, #20]
8003fc0: f023 030a bic.w r3, r3, #10
8003fc4: 617b str r3, [r7, #20]
tmpccer |= TIM_ICPolarity;
8003fc6: 697a ldr r2, [r7, #20]
8003fc8: 68bb ldr r3, [r7, #8]
8003fca: 4313 orrs r3, r2
8003fcc: 617b str r3, [r7, #20]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1;
8003fce: 68fb ldr r3, [r7, #12]
8003fd0: 693a ldr r2, [r7, #16]
8003fd2: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
8003fd4: 68fb ldr r3, [r7, #12]
8003fd6: 697a ldr r2, [r7, #20]
8003fd8: 621a str r2, [r3, #32]
}
8003fda: bf00 nop
8003fdc: 371c adds r7, #28
8003fde: 46bd mov sp, r7
8003fe0: f85d 7b04 ldr.w r7, [sp], #4
8003fe4: 4770 bx lr
08003fe6 <TIM_TI2_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
8003fe6: b480 push {r7}
8003fe8: b087 sub sp, #28
8003fea: af00 add r7, sp, #0
8003fec: 60f8 str r0, [r7, #12]
8003fee: 60b9 str r1, [r7, #8]
8003ff0: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
8003ff2: 68fb ldr r3, [r7, #12]
8003ff4: 6a1b ldr r3, [r3, #32]
8003ff6: f023 0210 bic.w r2, r3, #16
8003ffa: 68fb ldr r3, [r7, #12]
8003ffc: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
8003ffe: 68fb ldr r3, [r7, #12]
8004000: 699b ldr r3, [r3, #24]
8004002: 617b str r3, [r7, #20]
tmpccer = TIMx->CCER;
8004004: 68fb ldr r3, [r7, #12]
8004006: 6a1b ldr r3, [r3, #32]
8004008: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC2F;
800400a: 697b ldr r3, [r7, #20]
800400c: f423 4370 bic.w r3, r3, #61440 ; 0xf000
8004010: 617b str r3, [r7, #20]
tmpccmr1 |= (TIM_ICFilter << 12U);
8004012: 687b ldr r3, [r7, #4]
8004014: 031b lsls r3, r3, #12
8004016: 697a ldr r2, [r7, #20]
8004018: 4313 orrs r3, r2
800401a: 617b str r3, [r7, #20]
/* Select the Polarity and set the CC2E Bit */
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
800401c: 693b ldr r3, [r7, #16]
800401e: f023 03a0 bic.w r3, r3, #160 ; 0xa0
8004022: 613b str r3, [r7, #16]
tmpccer |= (TIM_ICPolarity << 4U);
8004024: 68bb ldr r3, [r7, #8]
8004026: 011b lsls r3, r3, #4
8004028: 693a ldr r2, [r7, #16]
800402a: 4313 orrs r3, r2
800402c: 613b str r3, [r7, #16]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1 ;
800402e: 68fb ldr r3, [r7, #12]
8004030: 697a ldr r2, [r7, #20]
8004032: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
8004034: 68fb ldr r3, [r7, #12]
8004036: 693a ldr r2, [r7, #16]
8004038: 621a str r2, [r3, #32]
}
800403a: bf00 nop
800403c: 371c adds r7, #28
800403e: 46bd mov sp, r7
8004040: f85d 7b04 ldr.w r7, [sp], #4
8004044: 4770 bx lr
08004046 <TIM_ITRx_SetConfig>:
* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
* @arg TIM_TS_ETRF: External Trigger input
* @retval None
*/
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
{
8004046: b480 push {r7}
8004048: b085 sub sp, #20
800404a: af00 add r7, sp, #0
800404c: 6078 str r0, [r7, #4]
800404e: 6039 str r1, [r7, #0]
uint32_t tmpsmcr;
/* Get the TIMx SMCR register value */
tmpsmcr = TIMx->SMCR;
8004050: 687b ldr r3, [r7, #4]
8004052: 689b ldr r3, [r3, #8]
8004054: 60fb str r3, [r7, #12]
/* Reset the TS Bits */
tmpsmcr &= ~TIM_SMCR_TS;
8004056: 68fb ldr r3, [r7, #12]
8004058: f023 0370 bic.w r3, r3, #112 ; 0x70
800405c: 60fb str r3, [r7, #12]
/* Set the Input Trigger source and the slave mode*/
tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
800405e: 683a ldr r2, [r7, #0]
8004060: 68fb ldr r3, [r7, #12]
8004062: 4313 orrs r3, r2
8004064: f043 0307 orr.w r3, r3, #7
8004068: 60fb str r3, [r7, #12]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
800406a: 687b ldr r3, [r7, #4]
800406c: 68fa ldr r2, [r7, #12]
800406e: 609a str r2, [r3, #8]
}
8004070: bf00 nop
8004072: 3714 adds r7, #20
8004074: 46bd mov sp, r7
8004076: f85d 7b04 ldr.w r7, [sp], #4
800407a: 4770 bx lr
0800407c <TIM_ETR_SetConfig>:
* This parameter must be a value between 0x00 and 0x0F
* @retval None
*/
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
{
800407c: b480 push {r7}
800407e: b087 sub sp, #28
8004080: af00 add r7, sp, #0
8004082: 60f8 str r0, [r7, #12]
8004084: 60b9 str r1, [r7, #8]
8004086: 607a str r2, [r7, #4]
8004088: 603b str r3, [r7, #0]
uint32_t tmpsmcr;
tmpsmcr = TIMx->SMCR;
800408a: 68fb ldr r3, [r7, #12]
800408c: 689b ldr r3, [r3, #8]
800408e: 617b str r3, [r7, #20]
/* Reset the ETR Bits */
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
8004090: 697b ldr r3, [r7, #20]
8004092: f423 437f bic.w r3, r3, #65280 ; 0xff00
8004096: 617b str r3, [r7, #20]
/* Set the Prescaler, the Filter value and the Polarity */
tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
8004098: 683b ldr r3, [r7, #0]
800409a: 021a lsls r2, r3, #8
800409c: 687b ldr r3, [r7, #4]
800409e: 431a orrs r2, r3
80040a0: 68bb ldr r3, [r7, #8]
80040a2: 4313 orrs r3, r2
80040a4: 697a ldr r2, [r7, #20]
80040a6: 4313 orrs r3, r2
80040a8: 617b str r3, [r7, #20]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
80040aa: 68fb ldr r3, [r7, #12]
80040ac: 697a ldr r2, [r7, #20]
80040ae: 609a str r2, [r3, #8]
}
80040b0: bf00 nop
80040b2: 371c adds r7, #28
80040b4: 46bd mov sp, r7
80040b6: f85d 7b04 ldr.w r7, [sp], #4
80040ba: 4770 bx lr
080040bc <HAL_TIMEx_MasterConfigSynchronization>:
* mode.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
TIM_MasterConfigTypeDef *sMasterConfig)
{
80040bc: b480 push {r7}
80040be: b085 sub sp, #20
80040c0: af00 add r7, sp, #0
80040c2: 6078 str r0, [r7, #4]
80040c4: 6039 str r1, [r7, #0]
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
/* Check input state */
__HAL_LOCK(htim);
80040c6: 687b ldr r3, [r7, #4]
80040c8: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
80040cc: 2b01 cmp r3, #1
80040ce: d101 bne.n 80040d4 <HAL_TIMEx_MasterConfigSynchronization+0x18>
80040d0: 2302 movs r3, #2
80040d2: e05a b.n 800418a <HAL_TIMEx_MasterConfigSynchronization+0xce>
80040d4: 687b ldr r3, [r7, #4]
80040d6: 2201 movs r2, #1
80040d8: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Change the handler state */
htim->State = HAL_TIM_STATE_BUSY;
80040dc: 687b ldr r3, [r7, #4]
80040de: 2202 movs r2, #2
80040e0: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Get the TIMx CR2 register value */
tmpcr2 = htim->Instance->CR2;
80040e4: 687b ldr r3, [r7, #4]
80040e6: 681b ldr r3, [r3, #0]
80040e8: 685b ldr r3, [r3, #4]
80040ea: 60fb str r3, [r7, #12]
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
80040ec: 687b ldr r3, [r7, #4]
80040ee: 681b ldr r3, [r3, #0]
80040f0: 689b ldr r3, [r3, #8]
80040f2: 60bb str r3, [r7, #8]
/* Reset the MMS Bits */
tmpcr2 &= ~TIM_CR2_MMS;
80040f4: 68fb ldr r3, [r7, #12]
80040f6: f023 0370 bic.w r3, r3, #112 ; 0x70
80040fa: 60fb str r3, [r7, #12]
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
80040fc: 683b ldr r3, [r7, #0]
80040fe: 681b ldr r3, [r3, #0]
8004100: 68fa ldr r2, [r7, #12]
8004102: 4313 orrs r3, r2
8004104: 60fb str r3, [r7, #12]
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
8004106: 687b ldr r3, [r7, #4]
8004108: 681b ldr r3, [r3, #0]
800410a: 68fa ldr r2, [r7, #12]
800410c: 605a str r2, [r3, #4]
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
800410e: 687b ldr r3, [r7, #4]
8004110: 681b ldr r3, [r3, #0]
8004112: 4a21 ldr r2, [pc, #132] ; (8004198 <HAL_TIMEx_MasterConfigSynchronization+0xdc>)
8004114: 4293 cmp r3, r2
8004116: d022 beq.n 800415e <HAL_TIMEx_MasterConfigSynchronization+0xa2>
8004118: 687b ldr r3, [r7, #4]
800411a: 681b ldr r3, [r3, #0]
800411c: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8004120: d01d beq.n 800415e <HAL_TIMEx_MasterConfigSynchronization+0xa2>
8004122: 687b ldr r3, [r7, #4]
8004124: 681b ldr r3, [r3, #0]
8004126: 4a1d ldr r2, [pc, #116] ; (800419c <HAL_TIMEx_MasterConfigSynchronization+0xe0>)
8004128: 4293 cmp r3, r2
800412a: d018 beq.n 800415e <HAL_TIMEx_MasterConfigSynchronization+0xa2>
800412c: 687b ldr r3, [r7, #4]
800412e: 681b ldr r3, [r3, #0]
8004130: 4a1b ldr r2, [pc, #108] ; (80041a0 <HAL_TIMEx_MasterConfigSynchronization+0xe4>)
8004132: 4293 cmp r3, r2
8004134: d013 beq.n 800415e <HAL_TIMEx_MasterConfigSynchronization+0xa2>
8004136: 687b ldr r3, [r7, #4]
8004138: 681b ldr r3, [r3, #0]
800413a: 4a1a ldr r2, [pc, #104] ; (80041a4 <HAL_TIMEx_MasterConfigSynchronization+0xe8>)
800413c: 4293 cmp r3, r2
800413e: d00e beq.n 800415e <HAL_TIMEx_MasterConfigSynchronization+0xa2>
8004140: 687b ldr r3, [r7, #4]
8004142: 681b ldr r3, [r3, #0]
8004144: 4a18 ldr r2, [pc, #96] ; (80041a8 <HAL_TIMEx_MasterConfigSynchronization+0xec>)
8004146: 4293 cmp r3, r2
8004148: d009 beq.n 800415e <HAL_TIMEx_MasterConfigSynchronization+0xa2>
800414a: 687b ldr r3, [r7, #4]
800414c: 681b ldr r3, [r3, #0]
800414e: 4a17 ldr r2, [pc, #92] ; (80041ac <HAL_TIMEx_MasterConfigSynchronization+0xf0>)
8004150: 4293 cmp r3, r2
8004152: d004 beq.n 800415e <HAL_TIMEx_MasterConfigSynchronization+0xa2>
8004154: 687b ldr r3, [r7, #4]
8004156: 681b ldr r3, [r3, #0]
8004158: 4a15 ldr r2, [pc, #84] ; (80041b0 <HAL_TIMEx_MasterConfigSynchronization+0xf4>)
800415a: 4293 cmp r3, r2
800415c: d10c bne.n 8004178 <HAL_TIMEx_MasterConfigSynchronization+0xbc>
{
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
800415e: 68bb ldr r3, [r7, #8]
8004160: f023 0380 bic.w r3, r3, #128 ; 0x80
8004164: 60bb str r3, [r7, #8]
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
8004166: 683b ldr r3, [r7, #0]
8004168: 685b ldr r3, [r3, #4]
800416a: 68ba ldr r2, [r7, #8]
800416c: 4313 orrs r3, r2
800416e: 60bb str r3, [r7, #8]
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
8004170: 687b ldr r3, [r7, #4]
8004172: 681b ldr r3, [r3, #0]
8004174: 68ba ldr r2, [r7, #8]
8004176: 609a str r2, [r3, #8]
}
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
8004178: 687b ldr r3, [r7, #4]
800417a: 2201 movs r2, #1
800417c: f883 203d strb.w r2, [r3, #61] ; 0x3d
__HAL_UNLOCK(htim);
8004180: 687b ldr r3, [r7, #4]
8004182: 2200 movs r2, #0
8004184: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_OK;
8004188: 2300 movs r3, #0
}
800418a: 4618 mov r0, r3
800418c: 3714 adds r7, #20
800418e: 46bd mov sp, r7
8004190: f85d 7b04 ldr.w r7, [sp], #4
8004194: 4770 bx lr
8004196: bf00 nop
8004198: 40010000 .word 0x40010000
800419c: 40000400 .word 0x40000400
80041a0: 40000800 .word 0x40000800
80041a4: 40000c00 .word 0x40000c00
80041a8: 40010400 .word 0x40010400
80041ac: 40014000 .word 0x40014000
80041b0: 40001800 .word 0x40001800
080041b4 <HAL_TIMEx_CommutCallback>:
* @brief Hall commutation changed callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
{
80041b4: b480 push {r7}
80041b6: b083 sub sp, #12
80041b8: af00 add r7, sp, #0
80041ba: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_CommutCallback could be implemented in the user file
*/
}
80041bc: bf00 nop
80041be: 370c adds r7, #12
80041c0: 46bd mov sp, r7
80041c2: f85d 7b04 ldr.w r7, [sp], #4
80041c6: 4770 bx lr
080041c8 <HAL_TIMEx_BreakCallback>:
* @brief Hall Break detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
{
80041c8: b480 push {r7}
80041ca: b083 sub sp, #12
80041cc: af00 add r7, sp, #0
80041ce: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_BreakCallback could be implemented in the user file
*/
}
80041d0: bf00 nop
80041d2: 370c adds r7, #12
80041d4: 46bd mov sp, r7
80041d6: f85d 7b04 ldr.w r7, [sp], #4
80041da: 4770 bx lr
080041dc <HAL_UART_Init>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
80041dc: b580 push {r7, lr}
80041de: b082 sub sp, #8
80041e0: af00 add r7, sp, #0
80041e2: 6078 str r0, [r7, #4]
/* Check the UART handle allocation */
if (huart == NULL)
80041e4: 687b ldr r3, [r7, #4]
80041e6: 2b00 cmp r3, #0
80041e8: d101 bne.n 80041ee <HAL_UART_Init+0x12>
{
return HAL_ERROR;
80041ea: 2301 movs r3, #1
80041ec: e03f b.n 800426e <HAL_UART_Init+0x92>
assert_param(IS_UART_INSTANCE(huart->Instance));
}
assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
if (huart->gState == HAL_UART_STATE_RESET)
80041ee: 687b ldr r3, [r7, #4]
80041f0: f893 3039 ldrb.w r3, [r3, #57] ; 0x39
80041f4: b2db uxtb r3, r3
80041f6: 2b00 cmp r3, #0
80041f8: d106 bne.n 8004208 <HAL_UART_Init+0x2c>
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
80041fa: 687b ldr r3, [r7, #4]
80041fc: 2200 movs r2, #0
80041fe: f883 2038 strb.w r2, [r3, #56] ; 0x38
/* Init the low level hardware */
huart->MspInitCallback(huart);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
8004202: 6878 ldr r0, [r7, #4]
8004204: f7fd f888 bl 8001318 <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
8004208: 687b ldr r3, [r7, #4]
800420a: 2224 movs r2, #36 ; 0x24
800420c: f883 2039 strb.w r2, [r3, #57] ; 0x39
/* Disable the peripheral */
__HAL_UART_DISABLE(huart);
8004210: 687b ldr r3, [r7, #4]
8004212: 681b ldr r3, [r3, #0]
8004214: 68da ldr r2, [r3, #12]
8004216: 687b ldr r3, [r7, #4]
8004218: 681b ldr r3, [r3, #0]
800421a: f422 5200 bic.w r2, r2, #8192 ; 0x2000
800421e: 60da str r2, [r3, #12]
/* Set the UART Communication parameters */
UART_SetConfig(huart);
8004220: 6878 ldr r0, [r7, #4]
8004222: f000 f829 bl 8004278 <UART_SetConfig>
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
8004226: 687b ldr r3, [r7, #4]
8004228: 681b ldr r3, [r3, #0]
800422a: 691a ldr r2, [r3, #16]
800422c: 687b ldr r3, [r7, #4]
800422e: 681b ldr r3, [r3, #0]
8004230: f422 4290 bic.w r2, r2, #18432 ; 0x4800
8004234: 611a str r2, [r3, #16]
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
8004236: 687b ldr r3, [r7, #4]
8004238: 681b ldr r3, [r3, #0]
800423a: 695a ldr r2, [r3, #20]
800423c: 687b ldr r3, [r7, #4]
800423e: 681b ldr r3, [r3, #0]
8004240: f022 022a bic.w r2, r2, #42 ; 0x2a
8004244: 615a str r2, [r3, #20]
/* Enable the peripheral */
__HAL_UART_ENABLE(huart);
8004246: 687b ldr r3, [r7, #4]
8004248: 681b ldr r3, [r3, #0]
800424a: 68da ldr r2, [r3, #12]
800424c: 687b ldr r3, [r7, #4]
800424e: 681b ldr r3, [r3, #0]
8004250: f442 5200 orr.w r2, r2, #8192 ; 0x2000
8004254: 60da str r2, [r3, #12]
/* Initialize the UART state */
huart->ErrorCode = HAL_UART_ERROR_NONE;
8004256: 687b ldr r3, [r7, #4]
8004258: 2200 movs r2, #0
800425a: 63da str r2, [r3, #60] ; 0x3c
huart->gState = HAL_UART_STATE_READY;
800425c: 687b ldr r3, [r7, #4]
800425e: 2220 movs r2, #32
8004260: f883 2039 strb.w r2, [r3, #57] ; 0x39
huart->RxState = HAL_UART_STATE_READY;
8004264: 687b ldr r3, [r7, #4]
8004266: 2220 movs r2, #32
8004268: f883 203a strb.w r2, [r3, #58] ; 0x3a
return HAL_OK;
800426c: 2300 movs r3, #0
}
800426e: 4618 mov r0, r3
8004270: 3708 adds r7, #8
8004272: 46bd mov sp, r7
8004274: bd80 pop {r7, pc}
...
08004278 <UART_SetConfig>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
static void UART_SetConfig(UART_HandleTypeDef *huart)
{
8004278: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
800427c: b085 sub sp, #20
800427e: af00 add r7, sp, #0
8004280: 6078 str r0, [r7, #4]
assert_param(IS_UART_MODE(huart->Init.Mode));
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Configure the UART Stop Bits: Set STOP[13:12] bits
according to huart->Init.StopBits value */
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
8004282: 687b ldr r3, [r7, #4]
8004284: 681b ldr r3, [r3, #0]
8004286: 691b ldr r3, [r3, #16]
8004288: f423 5140 bic.w r1, r3, #12288 ; 0x3000
800428c: 687b ldr r3, [r7, #4]
800428e: 68da ldr r2, [r3, #12]
8004290: 687b ldr r3, [r7, #4]
8004292: 681b ldr r3, [r3, #0]
8004294: 430a orrs r2, r1
8004296: 611a str r2, [r3, #16]
Set the M bits according to huart->Init.WordLength value
Set PCE and PS bits according to huart->Init.Parity value
Set TE and RE bits according to huart->Init.Mode value
Set OVER8 bit according to huart->Init.OverSampling value */
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
8004298: 687b ldr r3, [r7, #4]
800429a: 689a ldr r2, [r3, #8]
800429c: 687b ldr r3, [r7, #4]
800429e: 691b ldr r3, [r3, #16]
80042a0: 431a orrs r2, r3
80042a2: 687b ldr r3, [r7, #4]
80042a4: 695b ldr r3, [r3, #20]
80042a6: 431a orrs r2, r3
80042a8: 687b ldr r3, [r7, #4]
80042aa: 69db ldr r3, [r3, #28]
80042ac: 4313 orrs r3, r2
80042ae: 60fb str r3, [r7, #12]
MODIFY_REG(huart->Instance->CR1,
80042b0: 687b ldr r3, [r7, #4]
80042b2: 681b ldr r3, [r3, #0]
80042b4: 68db ldr r3, [r3, #12]
80042b6: f423 4316 bic.w r3, r3, #38400 ; 0x9600
80042ba: f023 030c bic.w r3, r3, #12
80042be: 687a ldr r2, [r7, #4]
80042c0: 6812 ldr r2, [r2, #0]
80042c2: 68f9 ldr r1, [r7, #12]
80042c4: 430b orrs r3, r1
80042c6: 60d3 str r3, [r2, #12]
(uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
tmpreg);
/*-------------------------- USART CR3 Configuration -----------------------*/
/* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
80042c8: 687b ldr r3, [r7, #4]
80042ca: 681b ldr r3, [r3, #0]
80042cc: 695b ldr r3, [r3, #20]
80042ce: f423 7140 bic.w r1, r3, #768 ; 0x300
80042d2: 687b ldr r3, [r7, #4]
80042d4: 699a ldr r2, [r3, #24]
80042d6: 687b ldr r3, [r7, #4]
80042d8: 681b ldr r3, [r3, #0]
80042da: 430a orrs r2, r1
80042dc: 615a str r2, [r3, #20]
/* Check the Over Sampling */
if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
80042de: 687b ldr r3, [r7, #4]
80042e0: 69db ldr r3, [r3, #28]
80042e2: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
80042e6: f040 818b bne.w 8004600 <UART_SetConfig+0x388>
{
pclk = HAL_RCC_GetPCLK2Freq();
huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
}
#elif defined(USART6)
if ((huart->Instance == USART1) || (huart->Instance == USART6))
80042ea: 687b ldr r3, [r7, #4]
80042ec: 681b ldr r3, [r3, #0]
80042ee: 4ac1 ldr r2, [pc, #772] ; (80045f4 <UART_SetConfig+0x37c>)
80042f0: 4293 cmp r3, r2
80042f2: d005 beq.n 8004300 <UART_SetConfig+0x88>
80042f4: 687b ldr r3, [r7, #4]
80042f6: 681b ldr r3, [r3, #0]
80042f8: 4abf ldr r2, [pc, #764] ; (80045f8 <UART_SetConfig+0x380>)
80042fa: 4293 cmp r3, r2
80042fc: f040 80bd bne.w 800447a <UART_SetConfig+0x202>
{
pclk = HAL_RCC_GetPCLK2Freq();
8004300: f7ff f83a bl 8003378 <HAL_RCC_GetPCLK2Freq>
8004304: 60b8 str r0, [r7, #8]
huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
8004306: 68bb ldr r3, [r7, #8]
8004308: 461d mov r5, r3
800430a: f04f 0600 mov.w r6, #0
800430e: 46a8 mov r8, r5
8004310: 46b1 mov r9, r6
8004312: eb18 0308 adds.w r3, r8, r8
8004316: eb49 0409 adc.w r4, r9, r9
800431a: 4698 mov r8, r3
800431c: 46a1 mov r9, r4
800431e: eb18 0805 adds.w r8, r8, r5
8004322: eb49 0906 adc.w r9, r9, r6
8004326: f04f 0100 mov.w r1, #0
800432a: f04f 0200 mov.w r2, #0
800432e: ea4f 02c9 mov.w r2, r9, lsl #3
8004332: ea42 7258 orr.w r2, r2, r8, lsr #29
8004336: ea4f 01c8 mov.w r1, r8, lsl #3
800433a: 4688 mov r8, r1
800433c: 4691 mov r9, r2
800433e: eb18 0005 adds.w r0, r8, r5
8004342: eb49 0106 adc.w r1, r9, r6
8004346: 687b ldr r3, [r7, #4]
8004348: 685b ldr r3, [r3, #4]
800434a: 461d mov r5, r3
800434c: f04f 0600 mov.w r6, #0
8004350: 196b adds r3, r5, r5
8004352: eb46 0406 adc.w r4, r6, r6
8004356: 461a mov r2, r3
8004358: 4623 mov r3, r4
800435a: f7fb ff47 bl 80001ec <__aeabi_uldivmod>
800435e: 4603 mov r3, r0
8004360: 460c mov r4, r1
8004362: 461a mov r2, r3
8004364: 4ba5 ldr r3, [pc, #660] ; (80045fc <UART_SetConfig+0x384>)
8004366: fba3 2302 umull r2, r3, r3, r2
800436a: 095b lsrs r3, r3, #5
800436c: ea4f 1803 mov.w r8, r3, lsl #4
8004370: 68bb ldr r3, [r7, #8]
8004372: 461d mov r5, r3
8004374: f04f 0600 mov.w r6, #0
8004378: 46a9 mov r9, r5
800437a: 46b2 mov sl, r6
800437c: eb19 0309 adds.w r3, r9, r9
8004380: eb4a 040a adc.w r4, sl, sl
8004384: 4699 mov r9, r3
8004386: 46a2 mov sl, r4
8004388: eb19 0905 adds.w r9, r9, r5
800438c: eb4a 0a06 adc.w sl, sl, r6
8004390: f04f 0100 mov.w r1, #0
8004394: f04f 0200 mov.w r2, #0
8004398: ea4f 02ca mov.w r2, sl, lsl #3
800439c: ea42 7259 orr.w r2, r2, r9, lsr #29
80043a0: ea4f 01c9 mov.w r1, r9, lsl #3
80043a4: 4689 mov r9, r1
80043a6: 4692 mov sl, r2
80043a8: eb19 0005 adds.w r0, r9, r5
80043ac: eb4a 0106 adc.w r1, sl, r6
80043b0: 687b ldr r3, [r7, #4]
80043b2: 685b ldr r3, [r3, #4]
80043b4: 461d mov r5, r3
80043b6: f04f 0600 mov.w r6, #0
80043ba: 196b adds r3, r5, r5
80043bc: eb46 0406 adc.w r4, r6, r6
80043c0: 461a mov r2, r3
80043c2: 4623 mov r3, r4
80043c4: f7fb ff12 bl 80001ec <__aeabi_uldivmod>
80043c8: 4603 mov r3, r0
80043ca: 460c mov r4, r1
80043cc: 461a mov r2, r3
80043ce: 4b8b ldr r3, [pc, #556] ; (80045fc <UART_SetConfig+0x384>)
80043d0: fba3 1302 umull r1, r3, r3, r2
80043d4: 095b lsrs r3, r3, #5
80043d6: 2164 movs r1, #100 ; 0x64
80043d8: fb01 f303 mul.w r3, r1, r3
80043dc: 1ad3 subs r3, r2, r3
80043de: 00db lsls r3, r3, #3
80043e0: 3332 adds r3, #50 ; 0x32
80043e2: 4a86 ldr r2, [pc, #536] ; (80045fc <UART_SetConfig+0x384>)
80043e4: fba2 2303 umull r2, r3, r2, r3
80043e8: 095b lsrs r3, r3, #5
80043ea: 005b lsls r3, r3, #1
80043ec: f403 73f8 and.w r3, r3, #496 ; 0x1f0
80043f0: 4498 add r8, r3
80043f2: 68bb ldr r3, [r7, #8]
80043f4: 461d mov r5, r3
80043f6: f04f 0600 mov.w r6, #0
80043fa: 46a9 mov r9, r5
80043fc: 46b2 mov sl, r6
80043fe: eb19 0309 adds.w r3, r9, r9
8004402: eb4a 040a adc.w r4, sl, sl
8004406: 4699 mov r9, r3
8004408: 46a2 mov sl, r4
800440a: eb19 0905 adds.w r9, r9, r5
800440e: eb4a 0a06 adc.w sl, sl, r6
8004412: f04f 0100 mov.w r1, #0
8004416: f04f 0200 mov.w r2, #0
800441a: ea4f 02ca mov.w r2, sl, lsl #3
800441e: ea42 7259 orr.w r2, r2, r9, lsr #29
8004422: ea4f 01c9 mov.w r1, r9, lsl #3
8004426: 4689 mov r9, r1
8004428: 4692 mov sl, r2
800442a: eb19 0005 adds.w r0, r9, r5
800442e: eb4a 0106 adc.w r1, sl, r6
8004432: 687b ldr r3, [r7, #4]
8004434: 685b ldr r3, [r3, #4]
8004436: 461d mov r5, r3
8004438: f04f 0600 mov.w r6, #0
800443c: 196b adds r3, r5, r5
800443e: eb46 0406 adc.w r4, r6, r6
8004442: 461a mov r2, r3
8004444: 4623 mov r3, r4
8004446: f7fb fed1 bl 80001ec <__aeabi_uldivmod>
800444a: 4603 mov r3, r0
800444c: 460c mov r4, r1
800444e: 461a mov r2, r3
8004450: 4b6a ldr r3, [pc, #424] ; (80045fc <UART_SetConfig+0x384>)
8004452: fba3 1302 umull r1, r3, r3, r2
8004456: 095b lsrs r3, r3, #5
8004458: 2164 movs r1, #100 ; 0x64
800445a: fb01 f303 mul.w r3, r1, r3
800445e: 1ad3 subs r3, r2, r3
8004460: 00db lsls r3, r3, #3
8004462: 3332 adds r3, #50 ; 0x32
8004464: 4a65 ldr r2, [pc, #404] ; (80045fc <UART_SetConfig+0x384>)
8004466: fba2 2303 umull r2, r3, r2, r3
800446a: 095b lsrs r3, r3, #5
800446c: f003 0207 and.w r2, r3, #7
8004470: 687b ldr r3, [r7, #4]
8004472: 681b ldr r3, [r3, #0]
8004474: 4442 add r2, r8
8004476: 609a str r2, [r3, #8]
8004478: e26f b.n 800495a <UART_SetConfig+0x6e2>
huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
}
#endif /* USART6 */
else
{
pclk = HAL_RCC_GetPCLK1Freq();
800447a: f7fe ff69 bl 8003350 <HAL_RCC_GetPCLK1Freq>
800447e: 60b8 str r0, [r7, #8]
huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
8004480: 68bb ldr r3, [r7, #8]
8004482: 461d mov r5, r3
8004484: f04f 0600 mov.w r6, #0
8004488: 46a8 mov r8, r5
800448a: 46b1 mov r9, r6
800448c: eb18 0308 adds.w r3, r8, r8
8004490: eb49 0409 adc.w r4, r9, r9
8004494: 4698 mov r8, r3
8004496: 46a1 mov r9, r4
8004498: eb18 0805 adds.w r8, r8, r5
800449c: eb49 0906 adc.w r9, r9, r6
80044a0: f04f 0100 mov.w r1, #0
80044a4: f04f 0200 mov.w r2, #0
80044a8: ea4f 02c9 mov.w r2, r9, lsl #3
80044ac: ea42 7258 orr.w r2, r2, r8, lsr #29
80044b0: ea4f 01c8 mov.w r1, r8, lsl #3
80044b4: 4688 mov r8, r1
80044b6: 4691 mov r9, r2
80044b8: eb18 0005 adds.w r0, r8, r5
80044bc: eb49 0106 adc.w r1, r9, r6
80044c0: 687b ldr r3, [r7, #4]
80044c2: 685b ldr r3, [r3, #4]
80044c4: 461d mov r5, r3
80044c6: f04f 0600 mov.w r6, #0
80044ca: 196b adds r3, r5, r5
80044cc: eb46 0406 adc.w r4, r6, r6
80044d0: 461a mov r2, r3
80044d2: 4623 mov r3, r4
80044d4: f7fb fe8a bl 80001ec <__aeabi_uldivmod>
80044d8: 4603 mov r3, r0
80044da: 460c mov r4, r1
80044dc: 461a mov r2, r3
80044de: 4b47 ldr r3, [pc, #284] ; (80045fc <UART_SetConfig+0x384>)
80044e0: fba3 2302 umull r2, r3, r3, r2
80044e4: 095b lsrs r3, r3, #5
80044e6: ea4f 1803 mov.w r8, r3, lsl #4
80044ea: 68bb ldr r3, [r7, #8]
80044ec: 461d mov r5, r3
80044ee: f04f 0600 mov.w r6, #0
80044f2: 46a9 mov r9, r5
80044f4: 46b2 mov sl, r6
80044f6: eb19 0309 adds.w r3, r9, r9
80044fa: eb4a 040a adc.w r4, sl, sl
80044fe: 4699 mov r9, r3
8004500: 46a2 mov sl, r4
8004502: eb19 0905 adds.w r9, r9, r5
8004506: eb4a 0a06 adc.w sl, sl, r6
800450a: f04f 0100 mov.w r1, #0
800450e: f04f 0200 mov.w r2, #0
8004512: ea4f 02ca mov.w r2, sl, lsl #3
8004516: ea42 7259 orr.w r2, r2, r9, lsr #29
800451a: ea4f 01c9 mov.w r1, r9, lsl #3
800451e: 4689 mov r9, r1
8004520: 4692 mov sl, r2
8004522: eb19 0005 adds.w r0, r9, r5
8004526: eb4a 0106 adc.w r1, sl, r6
800452a: 687b ldr r3, [r7, #4]
800452c: 685b ldr r3, [r3, #4]
800452e: 461d mov r5, r3
8004530: f04f 0600 mov.w r6, #0
8004534: 196b adds r3, r5, r5
8004536: eb46 0406 adc.w r4, r6, r6
800453a: 461a mov r2, r3
800453c: 4623 mov r3, r4
800453e: f7fb fe55 bl 80001ec <__aeabi_uldivmod>
8004542: 4603 mov r3, r0
8004544: 460c mov r4, r1
8004546: 461a mov r2, r3
8004548: 4b2c ldr r3, [pc, #176] ; (80045fc <UART_SetConfig+0x384>)
800454a: fba3 1302 umull r1, r3, r3, r2
800454e: 095b lsrs r3, r3, #5
8004550: 2164 movs r1, #100 ; 0x64
8004552: fb01 f303 mul.w r3, r1, r3
8004556: 1ad3 subs r3, r2, r3
8004558: 00db lsls r3, r3, #3
800455a: 3332 adds r3, #50 ; 0x32
800455c: 4a27 ldr r2, [pc, #156] ; (80045fc <UART_SetConfig+0x384>)
800455e: fba2 2303 umull r2, r3, r2, r3
8004562: 095b lsrs r3, r3, #5
8004564: 005b lsls r3, r3, #1
8004566: f403 73f8 and.w r3, r3, #496 ; 0x1f0
800456a: 4498 add r8, r3
800456c: 68bb ldr r3, [r7, #8]
800456e: 461d mov r5, r3
8004570: f04f 0600 mov.w r6, #0
8004574: 46a9 mov r9, r5
8004576: 46b2 mov sl, r6
8004578: eb19 0309 adds.w r3, r9, r9
800457c: eb4a 040a adc.w r4, sl, sl
8004580: 4699 mov r9, r3
8004582: 46a2 mov sl, r4
8004584: eb19 0905 adds.w r9, r9, r5
8004588: eb4a 0a06 adc.w sl, sl, r6
800458c: f04f 0100 mov.w r1, #0
8004590: f04f 0200 mov.w r2, #0
8004594: ea4f 02ca mov.w r2, sl, lsl #3
8004598: ea42 7259 orr.w r2, r2, r9, lsr #29
800459c: ea4f 01c9 mov.w r1, r9, lsl #3
80045a0: 4689 mov r9, r1
80045a2: 4692 mov sl, r2
80045a4: eb19 0005 adds.w r0, r9, r5
80045a8: eb4a 0106 adc.w r1, sl, r6
80045ac: 687b ldr r3, [r7, #4]
80045ae: 685b ldr r3, [r3, #4]
80045b0: 461d mov r5, r3
80045b2: f04f 0600 mov.w r6, #0
80045b6: 196b adds r3, r5, r5
80045b8: eb46 0406 adc.w r4, r6, r6
80045bc: 461a mov r2, r3
80045be: 4623 mov r3, r4
80045c0: f7fb fe14 bl 80001ec <__aeabi_uldivmod>
80045c4: 4603 mov r3, r0
80045c6: 460c mov r4, r1
80045c8: 461a mov r2, r3
80045ca: 4b0c ldr r3, [pc, #48] ; (80045fc <UART_SetConfig+0x384>)
80045cc: fba3 1302 umull r1, r3, r3, r2
80045d0: 095b lsrs r3, r3, #5
80045d2: 2164 movs r1, #100 ; 0x64
80045d4: fb01 f303 mul.w r3, r1, r3
80045d8: 1ad3 subs r3, r2, r3
80045da: 00db lsls r3, r3, #3
80045dc: 3332 adds r3, #50 ; 0x32
80045de: 4a07 ldr r2, [pc, #28] ; (80045fc <UART_SetConfig+0x384>)
80045e0: fba2 2303 umull r2, r3, r2, r3
80045e4: 095b lsrs r3, r3, #5
80045e6: f003 0207 and.w r2, r3, #7
80045ea: 687b ldr r3, [r7, #4]
80045ec: 681b ldr r3, [r3, #0]
80045ee: 4442 add r2, r8
80045f0: 609a str r2, [r3, #8]
{
pclk = HAL_RCC_GetPCLK1Freq();
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
}
}
}
80045f2: e1b2 b.n 800495a <UART_SetConfig+0x6e2>
80045f4: 40011000 .word 0x40011000
80045f8: 40011400 .word 0x40011400
80045fc: 51eb851f .word 0x51eb851f
if ((huart->Instance == USART1) || (huart->Instance == USART6))
8004600: 687b ldr r3, [r7, #4]
8004602: 681b ldr r3, [r3, #0]
8004604: 4ad7 ldr r2, [pc, #860] ; (8004964 <UART_SetConfig+0x6ec>)
8004606: 4293 cmp r3, r2
8004608: d005 beq.n 8004616 <UART_SetConfig+0x39e>
800460a: 687b ldr r3, [r7, #4]
800460c: 681b ldr r3, [r3, #0]
800460e: 4ad6 ldr r2, [pc, #856] ; (8004968 <UART_SetConfig+0x6f0>)
8004610: 4293 cmp r3, r2
8004612: f040 80d1 bne.w 80047b8 <UART_SetConfig+0x540>
pclk = HAL_RCC_GetPCLK2Freq();
8004616: f7fe feaf bl 8003378 <HAL_RCC_GetPCLK2Freq>
800461a: 60b8 str r0, [r7, #8]
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
800461c: 68bb ldr r3, [r7, #8]
800461e: 469a mov sl, r3
8004620: f04f 0b00 mov.w fp, #0
8004624: 46d0 mov r8, sl
8004626: 46d9 mov r9, fp
8004628: eb18 0308 adds.w r3, r8, r8
800462c: eb49 0409 adc.w r4, r9, r9
8004630: 4698 mov r8, r3
8004632: 46a1 mov r9, r4
8004634: eb18 080a adds.w r8, r8, sl
8004638: eb49 090b adc.w r9, r9, fp
800463c: f04f 0100 mov.w r1, #0
8004640: f04f 0200 mov.w r2, #0
8004644: ea4f 02c9 mov.w r2, r9, lsl #3
8004648: ea42 7258 orr.w r2, r2, r8, lsr #29
800464c: ea4f 01c8 mov.w r1, r8, lsl #3
8004650: 4688 mov r8, r1
8004652: 4691 mov r9, r2
8004654: eb1a 0508 adds.w r5, sl, r8
8004658: eb4b 0609 adc.w r6, fp, r9
800465c: 687b ldr r3, [r7, #4]
800465e: 685b ldr r3, [r3, #4]
8004660: 4619 mov r1, r3
8004662: f04f 0200 mov.w r2, #0
8004666: f04f 0300 mov.w r3, #0
800466a: f04f 0400 mov.w r4, #0
800466e: 0094 lsls r4, r2, #2
8004670: ea44 7491 orr.w r4, r4, r1, lsr #30
8004674: 008b lsls r3, r1, #2
8004676: 461a mov r2, r3
8004678: 4623 mov r3, r4
800467a: 4628 mov r0, r5
800467c: 4631 mov r1, r6
800467e: f7fb fdb5 bl 80001ec <__aeabi_uldivmod>
8004682: 4603 mov r3, r0
8004684: 460c mov r4, r1
8004686: 461a mov r2, r3
8004688: 4bb8 ldr r3, [pc, #736] ; (800496c <UART_SetConfig+0x6f4>)
800468a: fba3 2302 umull r2, r3, r3, r2
800468e: 095b lsrs r3, r3, #5
8004690: ea4f 1803 mov.w r8, r3, lsl #4
8004694: 68bb ldr r3, [r7, #8]
8004696: 469b mov fp, r3
8004698: f04f 0c00 mov.w ip, #0
800469c: 46d9 mov r9, fp
800469e: 46e2 mov sl, ip
80046a0: eb19 0309 adds.w r3, r9, r9
80046a4: eb4a 040a adc.w r4, sl, sl
80046a8: 4699 mov r9, r3
80046aa: 46a2 mov sl, r4
80046ac: eb19 090b adds.w r9, r9, fp
80046b0: eb4a 0a0c adc.w sl, sl, ip
80046b4: f04f 0100 mov.w r1, #0
80046b8: f04f 0200 mov.w r2, #0
80046bc: ea4f 02ca mov.w r2, sl, lsl #3
80046c0: ea42 7259 orr.w r2, r2, r9, lsr #29
80046c4: ea4f 01c9 mov.w r1, r9, lsl #3
80046c8: 4689 mov r9, r1
80046ca: 4692 mov sl, r2
80046cc: eb1b 0509 adds.w r5, fp, r9
80046d0: eb4c 060a adc.w r6, ip, sl
80046d4: 687b ldr r3, [r7, #4]
80046d6: 685b ldr r3, [r3, #4]
80046d8: 4619 mov r1, r3
80046da: f04f 0200 mov.w r2, #0
80046de: f04f 0300 mov.w r3, #0
80046e2: f04f 0400 mov.w r4, #0
80046e6: 0094 lsls r4, r2, #2
80046e8: ea44 7491 orr.w r4, r4, r1, lsr #30
80046ec: 008b lsls r3, r1, #2
80046ee: 461a mov r2, r3
80046f0: 4623 mov r3, r4
80046f2: 4628 mov r0, r5
80046f4: 4631 mov r1, r6
80046f6: f7fb fd79 bl 80001ec <__aeabi_uldivmod>
80046fa: 4603 mov r3, r0
80046fc: 460c mov r4, r1
80046fe: 461a mov r2, r3
8004700: 4b9a ldr r3, [pc, #616] ; (800496c <UART_SetConfig+0x6f4>)
8004702: fba3 1302 umull r1, r3, r3, r2
8004706: 095b lsrs r3, r3, #5
8004708: 2164 movs r1, #100 ; 0x64
800470a: fb01 f303 mul.w r3, r1, r3
800470e: 1ad3 subs r3, r2, r3
8004710: 011b lsls r3, r3, #4
8004712: 3332 adds r3, #50 ; 0x32
8004714: 4a95 ldr r2, [pc, #596] ; (800496c <UART_SetConfig+0x6f4>)
8004716: fba2 2303 umull r2, r3, r2, r3
800471a: 095b lsrs r3, r3, #5
800471c: f003 03f0 and.w r3, r3, #240 ; 0xf0
8004720: 4498 add r8, r3
8004722: 68bb ldr r3, [r7, #8]
8004724: 469b mov fp, r3
8004726: f04f 0c00 mov.w ip, #0
800472a: 46d9 mov r9, fp
800472c: 46e2 mov sl, ip
800472e: eb19 0309 adds.w r3, r9, r9
8004732: eb4a 040a adc.w r4, sl, sl
8004736: 4699 mov r9, r3
8004738: 46a2 mov sl, r4
800473a: eb19 090b adds.w r9, r9, fp
800473e: eb4a 0a0c adc.w sl, sl, ip
8004742: f04f 0100 mov.w r1, #0
8004746: f04f 0200 mov.w r2, #0
800474a: ea4f 02ca mov.w r2, sl, lsl #3
800474e: ea42 7259 orr.w r2, r2, r9, lsr #29
8004752: ea4f 01c9 mov.w r1, r9, lsl #3
8004756: 4689 mov r9, r1
8004758: 4692 mov sl, r2
800475a: eb1b 0509 adds.w r5, fp, r9
800475e: eb4c 060a adc.w r6, ip, sl
8004762: 687b ldr r3, [r7, #4]
8004764: 685b ldr r3, [r3, #4]
8004766: 4619 mov r1, r3
8004768: f04f 0200 mov.w r2, #0
800476c: f04f 0300 mov.w r3, #0
8004770: f04f 0400 mov.w r4, #0
8004774: 0094 lsls r4, r2, #2
8004776: ea44 7491 orr.w r4, r4, r1, lsr #30
800477a: 008b lsls r3, r1, #2
800477c: 461a mov r2, r3
800477e: 4623 mov r3, r4
8004780: 4628 mov r0, r5
8004782: 4631 mov r1, r6
8004784: f7fb fd32 bl 80001ec <__aeabi_uldivmod>
8004788: 4603 mov r3, r0
800478a: 460c mov r4, r1
800478c: 461a mov r2, r3
800478e: 4b77 ldr r3, [pc, #476] ; (800496c <UART_SetConfig+0x6f4>)
8004790: fba3 1302 umull r1, r3, r3, r2
8004794: 095b lsrs r3, r3, #5
8004796: 2164 movs r1, #100 ; 0x64
8004798: fb01 f303 mul.w r3, r1, r3
800479c: 1ad3 subs r3, r2, r3
800479e: 011b lsls r3, r3, #4
80047a0: 3332 adds r3, #50 ; 0x32
80047a2: 4a72 ldr r2, [pc, #456] ; (800496c <UART_SetConfig+0x6f4>)
80047a4: fba2 2303 umull r2, r3, r2, r3
80047a8: 095b lsrs r3, r3, #5
80047aa: f003 020f and.w r2, r3, #15
80047ae: 687b ldr r3, [r7, #4]
80047b0: 681b ldr r3, [r3, #0]
80047b2: 4442 add r2, r8
80047b4: 609a str r2, [r3, #8]
80047b6: e0d0 b.n 800495a <UART_SetConfig+0x6e2>
pclk = HAL_RCC_GetPCLK1Freq();
80047b8: f7fe fdca bl 8003350 <HAL_RCC_GetPCLK1Freq>
80047bc: 60b8 str r0, [r7, #8]
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
80047be: 68bb ldr r3, [r7, #8]
80047c0: 469a mov sl, r3
80047c2: f04f 0b00 mov.w fp, #0
80047c6: 46d0 mov r8, sl
80047c8: 46d9 mov r9, fp
80047ca: eb18 0308 adds.w r3, r8, r8
80047ce: eb49 0409 adc.w r4, r9, r9
80047d2: 4698 mov r8, r3
80047d4: 46a1 mov r9, r4
80047d6: eb18 080a adds.w r8, r8, sl
80047da: eb49 090b adc.w r9, r9, fp
80047de: f04f 0100 mov.w r1, #0
80047e2: f04f 0200 mov.w r2, #0
80047e6: ea4f 02c9 mov.w r2, r9, lsl #3
80047ea: ea42 7258 orr.w r2, r2, r8, lsr #29
80047ee: ea4f 01c8 mov.w r1, r8, lsl #3
80047f2: 4688 mov r8, r1
80047f4: 4691 mov r9, r2
80047f6: eb1a 0508 adds.w r5, sl, r8
80047fa: eb4b 0609 adc.w r6, fp, r9
80047fe: 687b ldr r3, [r7, #4]
8004800: 685b ldr r3, [r3, #4]
8004802: 4619 mov r1, r3
8004804: f04f 0200 mov.w r2, #0
8004808: f04f 0300 mov.w r3, #0
800480c: f04f 0400 mov.w r4, #0
8004810: 0094 lsls r4, r2, #2
8004812: ea44 7491 orr.w r4, r4, r1, lsr #30
8004816: 008b lsls r3, r1, #2
8004818: 461a mov r2, r3
800481a: 4623 mov r3, r4
800481c: 4628 mov r0, r5
800481e: 4631 mov r1, r6
8004820: f7fb fce4 bl 80001ec <__aeabi_uldivmod>
8004824: 4603 mov r3, r0
8004826: 460c mov r4, r1
8004828: 461a mov r2, r3
800482a: 4b50 ldr r3, [pc, #320] ; (800496c <UART_SetConfig+0x6f4>)
800482c: fba3 2302 umull r2, r3, r3, r2
8004830: 095b lsrs r3, r3, #5
8004832: ea4f 1803 mov.w r8, r3, lsl #4
8004836: 68bb ldr r3, [r7, #8]
8004838: 469b mov fp, r3
800483a: f04f 0c00 mov.w ip, #0
800483e: 46d9 mov r9, fp
8004840: 46e2 mov sl, ip
8004842: eb19 0309 adds.w r3, r9, r9
8004846: eb4a 040a adc.w r4, sl, sl
800484a: 4699 mov r9, r3
800484c: 46a2 mov sl, r4
800484e: eb19 090b adds.w r9, r9, fp
8004852: eb4a 0a0c adc.w sl, sl, ip
8004856: f04f 0100 mov.w r1, #0
800485a: f04f 0200 mov.w r2, #0
800485e: ea4f 02ca mov.w r2, sl, lsl #3
8004862: ea42 7259 orr.w r2, r2, r9, lsr #29
8004866: ea4f 01c9 mov.w r1, r9, lsl #3
800486a: 4689 mov r9, r1
800486c: 4692 mov sl, r2
800486e: eb1b 0509 adds.w r5, fp, r9
8004872: eb4c 060a adc.w r6, ip, sl
8004876: 687b ldr r3, [r7, #4]
8004878: 685b ldr r3, [r3, #4]
800487a: 4619 mov r1, r3
800487c: f04f 0200 mov.w r2, #0
8004880: f04f 0300 mov.w r3, #0
8004884: f04f 0400 mov.w r4, #0
8004888: 0094 lsls r4, r2, #2
800488a: ea44 7491 orr.w r4, r4, r1, lsr #30
800488e: 008b lsls r3, r1, #2
8004890: 461a mov r2, r3
8004892: 4623 mov r3, r4
8004894: 4628 mov r0, r5
8004896: 4631 mov r1, r6
8004898: f7fb fca8 bl 80001ec <__aeabi_uldivmod>
800489c: 4603 mov r3, r0
800489e: 460c mov r4, r1
80048a0: 461a mov r2, r3
80048a2: 4b32 ldr r3, [pc, #200] ; (800496c <UART_SetConfig+0x6f4>)
80048a4: fba3 1302 umull r1, r3, r3, r2
80048a8: 095b lsrs r3, r3, #5
80048aa: 2164 movs r1, #100 ; 0x64
80048ac: fb01 f303 mul.w r3, r1, r3
80048b0: 1ad3 subs r3, r2, r3
80048b2: 011b lsls r3, r3, #4
80048b4: 3332 adds r3, #50 ; 0x32
80048b6: 4a2d ldr r2, [pc, #180] ; (800496c <UART_SetConfig+0x6f4>)
80048b8: fba2 2303 umull r2, r3, r2, r3
80048bc: 095b lsrs r3, r3, #5
80048be: f003 03f0 and.w r3, r3, #240 ; 0xf0
80048c2: 4498 add r8, r3
80048c4: 68bb ldr r3, [r7, #8]
80048c6: 469b mov fp, r3
80048c8: f04f 0c00 mov.w ip, #0
80048cc: 46d9 mov r9, fp
80048ce: 46e2 mov sl, ip
80048d0: eb19 0309 adds.w r3, r9, r9
80048d4: eb4a 040a adc.w r4, sl, sl
80048d8: 4699 mov r9, r3
80048da: 46a2 mov sl, r4
80048dc: eb19 090b adds.w r9, r9, fp
80048e0: eb4a 0a0c adc.w sl, sl, ip
80048e4: f04f 0100 mov.w r1, #0
80048e8: f04f 0200 mov.w r2, #0
80048ec: ea4f 02ca mov.w r2, sl, lsl #3
80048f0: ea42 7259 orr.w r2, r2, r9, lsr #29
80048f4: ea4f 01c9 mov.w r1, r9, lsl #3
80048f8: 4689 mov r9, r1
80048fa: 4692 mov sl, r2
80048fc: eb1b 0509 adds.w r5, fp, r9
8004900: eb4c 060a adc.w r6, ip, sl
8004904: 687b ldr r3, [r7, #4]
8004906: 685b ldr r3, [r3, #4]
8004908: 4619 mov r1, r3
800490a: f04f 0200 mov.w r2, #0
800490e: f04f 0300 mov.w r3, #0
8004912: f04f 0400 mov.w r4, #0
8004916: 0094 lsls r4, r2, #2
8004918: ea44 7491 orr.w r4, r4, r1, lsr #30
800491c: 008b lsls r3, r1, #2
800491e: 461a mov r2, r3
8004920: 4623 mov r3, r4
8004922: 4628 mov r0, r5
8004924: 4631 mov r1, r6
8004926: f7fb fc61 bl 80001ec <__aeabi_uldivmod>
800492a: 4603 mov r3, r0
800492c: 460c mov r4, r1
800492e: 461a mov r2, r3
8004930: 4b0e ldr r3, [pc, #56] ; (800496c <UART_SetConfig+0x6f4>)
8004932: fba3 1302 umull r1, r3, r3, r2
8004936: 095b lsrs r3, r3, #5
8004938: 2164 movs r1, #100 ; 0x64
800493a: fb01 f303 mul.w r3, r1, r3
800493e: 1ad3 subs r3, r2, r3
8004940: 011b lsls r3, r3, #4
8004942: 3332 adds r3, #50 ; 0x32
8004944: 4a09 ldr r2, [pc, #36] ; (800496c <UART_SetConfig+0x6f4>)
8004946: fba2 2303 umull r2, r3, r2, r3
800494a: 095b lsrs r3, r3, #5
800494c: f003 020f and.w r2, r3, #15
8004950: 687b ldr r3, [r7, #4]
8004952: 681b ldr r3, [r3, #0]
8004954: 4442 add r2, r8
8004956: 609a str r2, [r3, #8]
}
8004958: e7ff b.n 800495a <UART_SetConfig+0x6e2>
800495a: bf00 nop
800495c: 3714 adds r7, #20
800495e: 46bd mov sp, r7
8004960: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
8004964: 40011000 .word 0x40011000
8004968: 40011400 .word 0x40011400
800496c: 51eb851f .word 0x51eb851f
08004970 <FMC_SDRAM_Init>:
* @param Device Pointer to SDRAM device instance
* @param Init Pointer to SDRAM Initialization structure
* @retval HAL status
*/
HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init)
{
8004970: b480 push {r7}
8004972: b085 sub sp, #20
8004974: af00 add r7, sp, #0
8004976: 6078 str r0, [r7, #4]
8004978: 6039 str r1, [r7, #0]
uint32_t tmpr1 = 0U;
800497a: 2300 movs r3, #0
800497c: 60fb str r3, [r7, #12]
uint32_t tmpr2 = 0U;
800497e: 2300 movs r3, #0
8004980: 60bb str r3, [r7, #8]
assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));
assert_param(IS_FMC_READ_BURST(Init->ReadBurst));
assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay));
/* Set SDRAM bank configuration parameters */
if (Init->SDBank != FMC_SDRAM_BANK2)
8004982: 683b ldr r3, [r7, #0]
8004984: 681b ldr r3, [r3, #0]
8004986: 2b01 cmp r3, #1
8004988: d029 beq.n 80049de <FMC_SDRAM_Init+0x6e>
{
tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
800498a: 687b ldr r3, [r7, #4]
800498c: 681b ldr r3, [r3, #0]
800498e: 60fb str r3, [r7, #12]
/* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
8004990: 68fb ldr r3, [r7, #12]
8004992: f423 43ff bic.w r3, r3, #32640 ; 0x7f80
8004996: f023 037f bic.w r3, r3, #127 ; 0x7f
800499a: 60fb str r3, [r7, #12]
FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\
800499c: 683b ldr r3, [r7, #0]
800499e: 685a ldr r2, [r3, #4]
Init->RowBitsNumber |\
80049a0: 683b ldr r3, [r7, #0]
80049a2: 689b ldr r3, [r3, #8]
tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\
80049a4: 431a orrs r2, r3
Init->MemoryDataWidth |\
80049a6: 683b ldr r3, [r7, #0]
80049a8: 68db ldr r3, [r3, #12]
Init->RowBitsNumber |\
80049aa: 431a orrs r2, r3
Init->InternalBankNumber |\
80049ac: 683b ldr r3, [r7, #0]
80049ae: 691b ldr r3, [r3, #16]
Init->MemoryDataWidth |\
80049b0: 431a orrs r2, r3
Init->CASLatency |\
80049b2: 683b ldr r3, [r7, #0]
80049b4: 695b ldr r3, [r3, #20]
Init->InternalBankNumber |\
80049b6: 431a orrs r2, r3
Init->WriteProtection |\
80049b8: 683b ldr r3, [r7, #0]
80049ba: 699b ldr r3, [r3, #24]
Init->CASLatency |\
80049bc: 431a orrs r2, r3
Init->SDClockPeriod |\
80049be: 683b ldr r3, [r7, #0]
80049c0: 69db ldr r3, [r3, #28]
Init->WriteProtection |\
80049c2: 431a orrs r2, r3
Init->ReadBurst |\
80049c4: 683b ldr r3, [r7, #0]
80049c6: 6a1b ldr r3, [r3, #32]
Init->SDClockPeriod |\
80049c8: 431a orrs r2, r3
Init->ReadPipeDelay
80049ca: 683b ldr r3, [r7, #0]
80049cc: 6a5b ldr r3, [r3, #36] ; 0x24
Init->ReadBurst |\
80049ce: 4313 orrs r3, r2
tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\
80049d0: 68fa ldr r2, [r7, #12]
80049d2: 4313 orrs r3, r2
80049d4: 60fb str r3, [r7, #12]
);
Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
80049d6: 687b ldr r3, [r7, #4]
80049d8: 68fa ldr r2, [r7, #12]
80049da: 601a str r2, [r3, #0]
80049dc: e034 b.n 8004a48 <FMC_SDRAM_Init+0xd8>
}
else /* FMC_Bank2_SDRAM */
{
tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
80049de: 687b ldr r3, [r7, #4]
80049e0: 681b ldr r3, [r3, #0]
80049e2: 60fb str r3, [r7, #12]
/* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
tmpr1 &= ((uint32_t)~(FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
80049e4: 68fb ldr r3, [r7, #12]
80049e6: f423 43f8 bic.w r3, r3, #31744 ; 0x7c00
80049ea: 60fb str r3, [r7, #12]
tmpr1 |= (uint32_t)(Init->SDClockPeriod |\
80049ec: 683b ldr r3, [r7, #0]
80049ee: 69da ldr r2, [r3, #28]
Init->ReadBurst |\
80049f0: 683b ldr r3, [r7, #0]
80049f2: 6a1b ldr r3, [r3, #32]
tmpr1 |= (uint32_t)(Init->SDClockPeriod |\
80049f4: 431a orrs r2, r3
Init->ReadPipeDelay);
80049f6: 683b ldr r3, [r7, #0]
80049f8: 6a5b ldr r3, [r3, #36] ; 0x24
Init->ReadBurst |\
80049fa: 4313 orrs r3, r2
tmpr1 |= (uint32_t)(Init->SDClockPeriod |\
80049fc: 68fa ldr r2, [r7, #12]
80049fe: 4313 orrs r3, r2
8004a00: 60fb str r3, [r7, #12]
tmpr2 = Device->SDCR[FMC_SDRAM_BANK2];
8004a02: 687b ldr r3, [r7, #4]
8004a04: 685b ldr r3, [r3, #4]
8004a06: 60bb str r3, [r7, #8]
/* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
tmpr2 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
8004a08: 68bb ldr r3, [r7, #8]
8004a0a: f423 43ff bic.w r3, r3, #32640 ; 0x7f80
8004a0e: f023 037f bic.w r3, r3, #127 ; 0x7f
8004a12: 60bb str r3, [r7, #8]
FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\
8004a14: 683b ldr r3, [r7, #0]
8004a16: 685a ldr r2, [r3, #4]
Init->RowBitsNumber |\
8004a18: 683b ldr r3, [r7, #0]
8004a1a: 689b ldr r3, [r3, #8]
tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\
8004a1c: 431a orrs r2, r3
Init->MemoryDataWidth |\
8004a1e: 683b ldr r3, [r7, #0]
8004a20: 68db ldr r3, [r3, #12]
Init->RowBitsNumber |\
8004a22: 431a orrs r2, r3
Init->InternalBankNumber |\
8004a24: 683b ldr r3, [r7, #0]
8004a26: 691b ldr r3, [r3, #16]
Init->MemoryDataWidth |\
8004a28: 431a orrs r2, r3
Init->CASLatency |\
8004a2a: 683b ldr r3, [r7, #0]
8004a2c: 695b ldr r3, [r3, #20]
Init->InternalBankNumber |\
8004a2e: 431a orrs r2, r3
Init->WriteProtection);
8004a30: 683b ldr r3, [r7, #0]
8004a32: 699b ldr r3, [r3, #24]
Init->CASLatency |\
8004a34: 4313 orrs r3, r2
tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\
8004a36: 68ba ldr r2, [r7, #8]
8004a38: 4313 orrs r3, r2
8004a3a: 60bb str r3, [r7, #8]
Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
8004a3c: 687b ldr r3, [r7, #4]
8004a3e: 68fa ldr r2, [r7, #12]
8004a40: 601a str r2, [r3, #0]
Device->SDCR[FMC_SDRAM_BANK2] = tmpr2;
8004a42: 687b ldr r3, [r7, #4]
8004a44: 68ba ldr r2, [r7, #8]
8004a46: 605a str r2, [r3, #4]
}
return HAL_OK;
8004a48: 2300 movs r3, #0
}
8004a4a: 4618 mov r0, r3
8004a4c: 3714 adds r7, #20
8004a4e: 46bd mov sp, r7
8004a50: f85d 7b04 ldr.w r7, [sp], #4
8004a54: 4770 bx lr
08004a56 <FMC_SDRAM_Timing_Init>:
* @param Timing Pointer to SDRAM Timing structure
* @param Bank SDRAM bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
{
8004a56: b480 push {r7}
8004a58: b087 sub sp, #28
8004a5a: af00 add r7, sp, #0
8004a5c: 60f8 str r0, [r7, #12]
8004a5e: 60b9 str r1, [r7, #8]
8004a60: 607a str r2, [r7, #4]
uint32_t tmpr1 = 0U;
8004a62: 2300 movs r3, #0
8004a64: 617b str r3, [r7, #20]
uint32_t tmpr2 = 0U;
8004a66: 2300 movs r3, #0
8004a68: 613b str r3, [r7, #16]
assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));
assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));
assert_param(IS_FMC_SDRAM_BANK(Bank));
/* Set SDRAM device timing parameters */
if (Bank != FMC_SDRAM_BANK2)
8004a6a: 687b ldr r3, [r7, #4]
8004a6c: 2b01 cmp r3, #1
8004a6e: d02e beq.n 8004ace <FMC_SDRAM_Timing_Init+0x78>
{
tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];
8004a70: 68fb ldr r3, [r7, #12]
8004a72: 689b ldr r3, [r3, #8]
8004a74: 617b str r3, [r7, #20]
/* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
8004a76: 697b ldr r3, [r7, #20]
8004a78: f003 4370 and.w r3, r3, #4026531840 ; 0xf0000000
8004a7c: 617b str r3, [r7, #20]
FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
FMC_SDTR1_TRCD));
tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1U) |\
8004a7e: 68bb ldr r3, [r7, #8]
8004a80: 681b ldr r3, [r3, #0]
8004a82: 1e5a subs r2, r3, #1
(((Timing->ExitSelfRefreshDelay)-1U) << 4U) |\
8004a84: 68bb ldr r3, [r7, #8]
8004a86: 685b ldr r3, [r3, #4]
8004a88: 3b01 subs r3, #1
8004a8a: 011b lsls r3, r3, #4
tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1U) |\
8004a8c: 431a orrs r2, r3
(((Timing->SelfRefreshTime)-1U) << 8U) |\
8004a8e: 68bb ldr r3, [r7, #8]
8004a90: 689b ldr r3, [r3, #8]
8004a92: 3b01 subs r3, #1
8004a94: 021b lsls r3, r3, #8
(((Timing->ExitSelfRefreshDelay)-1U) << 4U) |\
8004a96: 431a orrs r2, r3
(((Timing->RowCycleDelay)-1U) << 12U) |\
8004a98: 68bb ldr r3, [r7, #8]
8004a9a: 68db ldr r3, [r3, #12]
8004a9c: 3b01 subs r3, #1
8004a9e: 031b lsls r3, r3, #12
(((Timing->SelfRefreshTime)-1U) << 8U) |\
8004aa0: 431a orrs r2, r3
(((Timing->WriteRecoveryTime)-1U) <<16U) |\
8004aa2: 68bb ldr r3, [r7, #8]
8004aa4: 691b ldr r3, [r3, #16]
8004aa6: 3b01 subs r3, #1
8004aa8: 041b lsls r3, r3, #16
(((Timing->RowCycleDelay)-1U) << 12U) |\
8004aaa: 431a orrs r2, r3
(((Timing->RPDelay)-1U) << 20U) |\
8004aac: 68bb ldr r3, [r7, #8]
8004aae: 695b ldr r3, [r3, #20]
8004ab0: 3b01 subs r3, #1
8004ab2: 051b lsls r3, r3, #20
(((Timing->WriteRecoveryTime)-1U) <<16U) |\
8004ab4: 431a orrs r2, r3
(((Timing->RCDDelay)-1U) << 24U));
8004ab6: 68bb ldr r3, [r7, #8]
8004ab8: 699b ldr r3, [r3, #24]
8004aba: 3b01 subs r3, #1
8004abc: 061b lsls r3, r3, #24
tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1U) |\
8004abe: 4313 orrs r3, r2
8004ac0: 697a ldr r2, [r7, #20]
8004ac2: 4313 orrs r3, r2
8004ac4: 617b str r3, [r7, #20]
Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;
8004ac6: 68fb ldr r3, [r7, #12]
8004ac8: 697a ldr r2, [r7, #20]
8004aca: 609a str r2, [r3, #8]
8004acc: e03b b.n 8004b46 <FMC_SDRAM_Timing_Init+0xf0>
}
else /* FMC_Bank2_SDRAM */
{
tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];
8004ace: 68fb ldr r3, [r7, #12]
8004ad0: 689b ldr r3, [r3, #8]
8004ad2: 617b str r3, [r7, #20]
/* Clear TRC and TRP bits */
tmpr1 &= ((uint32_t)~(FMC_SDTR1_TRC | FMC_SDTR1_TRP));
8004ad4: 697b ldr r3, [r7, #20]
8004ad6: f423 0370 bic.w r3, r3, #15728640 ; 0xf00000
8004ada: f423 4370 bic.w r3, r3, #61440 ; 0xf000
8004ade: 617b str r3, [r7, #20]
tmpr1 |= (uint32_t)((((Timing->RowCycleDelay)-1U) << 12U) |\
8004ae0: 68bb ldr r3, [r7, #8]
8004ae2: 68db ldr r3, [r3, #12]
8004ae4: 3b01 subs r3, #1
8004ae6: 031a lsls r2, r3, #12
(((Timing->RPDelay)-1U) << 20U));
8004ae8: 68bb ldr r3, [r7, #8]
8004aea: 695b ldr r3, [r3, #20]
8004aec: 3b01 subs r3, #1
8004aee: 051b lsls r3, r3, #20
tmpr1 |= (uint32_t)((((Timing->RowCycleDelay)-1U) << 12U) |\
8004af0: 4313 orrs r3, r2
8004af2: 697a ldr r2, [r7, #20]
8004af4: 4313 orrs r3, r2
8004af6: 617b str r3, [r7, #20]
tmpr2 = Device->SDTR[FMC_SDRAM_BANK2];
8004af8: 68fb ldr r3, [r7, #12]
8004afa: 68db ldr r3, [r3, #12]
8004afc: 613b str r3, [r7, #16]
/* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
8004afe: 693b ldr r3, [r7, #16]
8004b00: f003 4370 and.w r3, r3, #4026531840 ; 0xf0000000
8004b04: 613b str r3, [r7, #16]
FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
FMC_SDTR1_TRCD));
tmpr2 |= (uint32_t)((((Timing->LoadToActiveDelay)-1U) |\
8004b06: 68bb ldr r3, [r7, #8]
8004b08: 681b ldr r3, [r3, #0]
8004b0a: 1e5a subs r2, r3, #1
(((Timing->ExitSelfRefreshDelay)-1U) << 4U) |\
8004b0c: 68bb ldr r3, [r7, #8]
8004b0e: 685b ldr r3, [r3, #4]
8004b10: 3b01 subs r3, #1
8004b12: 011b lsls r3, r3, #4
tmpr2 |= (uint32_t)((((Timing->LoadToActiveDelay)-1U) |\
8004b14: 431a orrs r2, r3
(((Timing->SelfRefreshTime)-1U) << 8U) |\
8004b16: 68bb ldr r3, [r7, #8]
8004b18: 689b ldr r3, [r3, #8]
8004b1a: 3b01 subs r3, #1
8004b1c: 021b lsls r3, r3, #8
(((Timing->ExitSelfRefreshDelay)-1U) << 4U) |\
8004b1e: 431a orrs r2, r3
(((Timing->WriteRecoveryTime)-1U) <<16U) |\
8004b20: 68bb ldr r3, [r7, #8]
8004b22: 691b ldr r3, [r3, #16]
8004b24: 3b01 subs r3, #1
8004b26: 041b lsls r3, r3, #16
(((Timing->SelfRefreshTime)-1U) << 8U) |\
8004b28: 431a orrs r2, r3
(((Timing->RCDDelay)-1U) << 24U)));
8004b2a: 68bb ldr r3, [r7, #8]
8004b2c: 699b ldr r3, [r3, #24]
8004b2e: 3b01 subs r3, #1
8004b30: 061b lsls r3, r3, #24
tmpr2 |= (uint32_t)((((Timing->LoadToActiveDelay)-1U) |\
8004b32: 4313 orrs r3, r2
8004b34: 693a ldr r2, [r7, #16]
8004b36: 4313 orrs r3, r2
8004b38: 613b str r3, [r7, #16]
Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;
8004b3a: 68fb ldr r3, [r7, #12]
8004b3c: 697a ldr r2, [r7, #20]
8004b3e: 609a str r2, [r3, #8]
Device->SDTR[FMC_SDRAM_BANK2] = tmpr2;
8004b40: 68fb ldr r3, [r7, #12]
8004b42: 693a ldr r2, [r7, #16]
8004b44: 60da str r2, [r3, #12]
}
return HAL_OK;
8004b46: 2300 movs r3, #0
}
8004b48: 4618 mov r0, r3
8004b4a: 371c adds r7, #28
8004b4c: 46bd mov sp, r7
8004b4e: f85d 7b04 ldr.w r7, [sp], #4
8004b52: 4770 bx lr
08004b54 <__libc_init_array>:
8004b54: b570 push {r4, r5, r6, lr}
8004b56: 4e0d ldr r6, [pc, #52] ; (8004b8c <__libc_init_array+0x38>)
8004b58: 4c0d ldr r4, [pc, #52] ; (8004b90 <__libc_init_array+0x3c>)
8004b5a: 1ba4 subs r4, r4, r6
8004b5c: 10a4 asrs r4, r4, #2
8004b5e: 2500 movs r5, #0
8004b60: 42a5 cmp r5, r4
8004b62: d109 bne.n 8004b78 <__libc_init_array+0x24>
8004b64: 4e0b ldr r6, [pc, #44] ; (8004b94 <__libc_init_array+0x40>)
8004b66: 4c0c ldr r4, [pc, #48] ; (8004b98 <__libc_init_array+0x44>)
8004b68: f000 f820 bl 8004bac <_init>
8004b6c: 1ba4 subs r4, r4, r6
8004b6e: 10a4 asrs r4, r4, #2
8004b70: 2500 movs r5, #0
8004b72: 42a5 cmp r5, r4
8004b74: d105 bne.n 8004b82 <__libc_init_array+0x2e>
8004b76: bd70 pop {r4, r5, r6, pc}
8004b78: f856 3025 ldr.w r3, [r6, r5, lsl #2]
8004b7c: 4798 blx r3
8004b7e: 3501 adds r5, #1
8004b80: e7ee b.n 8004b60 <__libc_init_array+0xc>
8004b82: f856 3025 ldr.w r3, [r6, r5, lsl #2]
8004b86: 4798 blx r3
8004b88: 3501 adds r5, #1
8004b8a: e7f2 b.n 8004b72 <__libc_init_array+0x1e>
8004b8c: 08004be4 .word 0x08004be4
8004b90: 08004be4 .word 0x08004be4
8004b94: 08004be4 .word 0x08004be4
8004b98: 08004be8 .word 0x08004be8
08004b9c <memset>:
8004b9c: 4402 add r2, r0
8004b9e: 4603 mov r3, r0
8004ba0: 4293 cmp r3, r2
8004ba2: d100 bne.n 8004ba6 <memset+0xa>
8004ba4: 4770 bx lr
8004ba6: f803 1b01 strb.w r1, [r3], #1
8004baa: e7f9 b.n 8004ba0 <memset+0x4>
08004bac <_init>:
8004bac: b5f8 push {r3, r4, r5, r6, r7, lr}
8004bae: bf00 nop
8004bb0: bcf8 pop {r3, r4, r5, r6, r7}
8004bb2: bc08 pop {r3}
8004bb4: 469e mov lr, r3
8004bb6: 4770 bx lr
08004bb8 <_fini>:
8004bb8: b5f8 push {r3, r4, r5, r6, r7, lr}
8004bba: bf00 nop
8004bbc: bcf8 pop {r3, r4, r5, r6, r7}
8004bbe: bc08 pop {r3}
8004bc0: 469e mov lr, r3
8004bc2: 4770 bx lr
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