diff --git a/Hardware/AltiumProject/2020-2021 Telemetry Board/2020-2021 Telemetry Board.PrjPcb b/Hardware/AltiumProject/2020-2021 Telemetry Board/2020-2021 Telemetry Board.PrjPcb index 6351a51..0add60d 100644 --- a/Hardware/AltiumProject/2020-2021 Telemetry Board/2020-2021 Telemetry Board.PrjPcb +++ b/Hardware/AltiumProject/2020-2021 Telemetry Board/2020-2021 Telemetry Board.PrjPcb @@ -567,6 +567,27 @@ DItemRevisionGUID= GenerateClassCluster=0 DocumentUniqueId=ZDGLDIZV +[Document32] +DocumentPath=Stage 2 - Combined.PcbDoc +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 +DocumentUniqueId=EGCHLCSW + +[GeneratedDocument1] +DocumentPath=Project Outputs for 2020-2021 Telemetry Board\Design Rule Check - Stage 2 - Combined.html +DItemRevisionGUID= + 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differ diff --git a/Hardware/AltiumProject/2020-2021 Telemetry Board/History/Stage 2 - Combined.~(8).PcbDoc.Zip b/Hardware/AltiumProject/2020-2021 Telemetry Board/History/Stage 2 - Combined.~(8).PcbDoc.Zip new file mode 100644 index 0000000..17f6321 Binary files /dev/null and b/Hardware/AltiumProject/2020-2021 Telemetry Board/History/Stage 2 - Combined.~(8).PcbDoc.Zip differ diff --git a/Hardware/AltiumProject/2020-2021 Telemetry Board/History/Stage 2 - Combined.~(9).PcbDoc.Zip b/Hardware/AltiumProject/2020-2021 Telemetry Board/History/Stage 2 - Combined.~(9).PcbDoc.Zip new file mode 100644 index 0000000..13f91fd Binary files /dev/null and b/Hardware/AltiumProject/2020-2021 Telemetry Board/History/Stage 2 - Combined.~(9).PcbDoc.Zip differ diff --git a/Hardware/AltiumProject/2020-2021 Telemetry Board/History/Stage 2 - Combined3.~(1).PcbDoc.Zip b/Hardware/AltiumProject/2020-2021 Telemetry Board/History/Stage 2 - Combined3.~(1).PcbDoc.Zip new file mode 100644 index 0000000..daca4d0 Binary files /dev/null and b/Hardware/AltiumProject/2020-2021 Telemetry Board/History/Stage 2 - Combined3.~(1).PcbDoc.Zip differ diff --git a/Hardware/AltiumProject/2020-2021 Telemetry Board/History/Stage 2 - Combined3.~(2).PcbDoc.Zip b/Hardware/AltiumProject/2020-2021 Telemetry Board/History/Stage 2 - Combined3.~(2).PcbDoc.Zip new file mode 100644 index 0000000..ac73e52 Binary files /dev/null and b/Hardware/AltiumProject/2020-2021 Telemetry Board/History/Stage 2 - Combined3.~(2).PcbDoc.Zip differ diff --git a/Hardware/AltiumProject/2020-2021 Telemetry Board/Project Logs for 2020-2021 Telemetry Board/Stage 2 - Combined PCB ECO 2021-04-12 11-38-02 PM.LOG b/Hardware/AltiumProject/2020-2021 Telemetry Board/Project Logs for 2020-2021 Telemetry Board/Stage 2 - Combined PCB ECO 2021-04-12 11-38-02 PM.LOG new file mode 100644 index 0000000..db78cb1 --- /dev/null +++ b/Hardware/AltiumProject/2020-2021 Telemetry Board/Project Logs for 2020-2021 Telemetry Board/Stage 2 - Combined PCB ECO 2021-04-12 11-38-02 PM.LOG @@ -0,0 +1,60 @@ +Added Pin To Net: NetName=GND Pin=C52-1 +Added Pin To Net: NetName=NetC52_2 Pin=C52-2 +Added Pin To Net: NetName=NetC52_2 Pin=C53-1 +Added Pin To Net: NetName=NetC53_2 Pin=C53-2 +Added Pin To Net: NetName=NetC54_1 Pin=C54-1 +Added Pin To Net: NetName=NetC54_2 Pin=C54-2 +Added Pin To Net: NetName=NetC55_1 Pin=C55-1 +Added Pin To Net: NetName=GND Pin=C55-2 +Added Pin To Net: NetName=NetC56_1 Pin=C56-1 +Added Pin To Net: NetName=NetC56_2 Pin=C56-2 +Added Pin To Net: NetName=GND Pin=C57-1 +Added Pin To Net: NetName=NetC57_2 Pin=C57-2 +Added Pin To Net: NetName=GND Pin=C58-1 +Added Pin To Net: NetName=NetC57_2 Pin=C58-2 +Added Pin To Net: NetName=NetC57_2 Pin=D4-1 +Added Pin To Net: NetName=NetC57_2 Pin=D4-3 +Added Pin To Net: NetName=+3.3V Pin=D4-4 +Added Pin To Net: NetName=NetC54_1 Pin=D5-1 +Added Pin To Net: NetName=GND Pin=D5-2 +Added Pin To Net: NetName=CANV Pin=F1-1 +Added Pin To Net: NetName=NetC52_2 Pin=F1-2 +Added Pin To Net: NetName=NetC54_1 Pin=L2-1 +Added Pin To Net: NetName=NetC57_2 Pin=L2-2 +Added Pin To Net: NetName=NetQ6_1 Pin=Q6-1 +Added Pin To Net: NetName=NetC54_1 Pin=Q6-3 +Added Pin To Net: NetName=NetC53_2 Pin=Q6-4 +Added Pin To Net: NetName=NetC55_1 Pin=R29-1 +Added Pin To Net: NetName=NetC57_2 Pin=R29-2 +Added Pin To Net: NetName=GND Pin=R30-1 +Added Pin To Net: NetName=NetC55_1 Pin=R30-2 +Added Pin To Net: NetName=NetC53_2 Pin=R31-1 +Added Pin To Net: NetName=NetC52_2 Pin=R31-2 +Added Pin To Net: NetName=GND Pin=R32-1 +Added Pin To Net: NetName=NetC56_2 Pin=R32-2 +Added Pin To Net: NetName=NetC53_2 Pin=U15-1 +Added Pin To Net: NetName=NetC56_1 Pin=U15-2 +Added Pin To Net: NetName=NetC55_1 Pin=U15-3 +Added Pin To Net: NetName=GND Pin=U15-4 +Added Pin To Net: NetName=NetC54_1 Pin=U15-5 +Added Pin To Net: NetName=NetQ6_1 Pin=U15-6 +Added Pin To Net: NetName=NetC54_2 Pin=U15-7 +Added Pin To Net: NetName=NetC52_2 Pin=U15-8 +Added Member To Class: ClassName=SMPS_DOWN Member=Component C52 GRM32ER61C226KE20L +Added Member To Class: ClassName=SMPS_DOWN Member=Component C53 C1206C102J5RACTU +Added Member To Class: ClassName=SMPS_DOWN Member=Component C54 C1206F104K3RACTU +Added Member To Class: ClassName=SMPS_DOWN Member=Component C55 C1206C101J1GACTU +Added Member To Class: ClassName=SMPS_DOWN Member=Component C56 C1206C103JARACTU +Added Member To Class: ClassName=SMPS_DOWN Member=Component C57 EMK325ABJ107MM-T +Added Member To Class: ClassName=SMPS_DOWN Member=Component C58 EMK325ABJ107MM-T +Added Member To Class: ClassName=SMPS_DOWN Member=Component D4 SM74611KTTR +Added Member To Class: ClassName=SMPS_DOWN Member=Component D5 MBRS340T3 +Added Member To Class: ClassName=SMPS_DOWN Member=Component F1 0154010.DR +Added Member To Class: ClassName=SMPS_DOWN Member=Component L2 MSS1210-103MEB +Added Member To Class: ClassName=SMPS_DOWN Member=Component Q6 NTD3055L104G +Added Member To Class: ClassName=SMPS_DOWN Member=Component R29 ERJ-8ENF3572V +Added Member To Class: ClassName=SMPS_DOWN Member=Component R30 ERJ-8GEYJ203V +Added Member To Class: ClassName=SMPS_DOWN Member=Component R31 ERJ8CWFR050V +Added Member To Class: ClassName=SMPS_DOWN Member=Component R32 ERJ-8GEYJ682V +Added Member To Class: ClassName=SMPS_DOWN Member=Component U15 LTC1624CS8#PBF +Added Room: Name=SMPS_DOWN diff --git a/Hardware/AltiumProject/2020-2021 Telemetry Board/Project Logs for 2020-2021 Telemetry Board/Stage 2 - Combined3 PCB ECO 2021-04-12 11-47-21 PM.LOG b/Hardware/AltiumProject/2020-2021 Telemetry Board/Project Logs for 2020-2021 Telemetry Board/Stage 2 - Combined3 PCB ECO 2021-04-12 11-47-21 PM.LOG new file mode 100644 index 0000000..03045e4 --- /dev/null +++ b/Hardware/AltiumProject/2020-2021 Telemetry Board/Project Logs for 2020-2021 Telemetry Board/Stage 2 - Combined3 PCB ECO 2021-04-12 11-47-21 PM.LOG @@ -0,0 +1,3 @@ +Change Component Comment : Designator=Designator1 Old Comment=Comment New Comment=GRM32ER61C226KE20L +Change Component Designator: OldDesignator=Designator1 NewDesignator=C52 +Added Member To Class: ClassName=SMPS_DOWN Member=Component C52 GRM32ER61C226KE20L diff --git a/Hardware/AltiumProject/2020-2021 Telemetry Board/Project Outputs for 2020-2021 Telemetry Board/Design Rule Check - Stage 2 - Combined.drc b/Hardware/AltiumProject/2020-2021 Telemetry Board/Project Outputs for 2020-2021 Telemetry Board/Design Rule Check - Stage 2 - Combined.drc new file mode 100644 index 0000000..4977db4 --- /dev/null +++ b/Hardware/AltiumProject/2020-2021 Telemetry Board/Project Outputs for 2020-2021 Telemetry Board/Design Rule Check - Stage 2 - Combined.drc @@ -0,0 +1,230 @@ +Protel Design System Design Rule Check +PCB File : C:\SunseekerTelemetry\Hardware\AltiumProject\2020-2021 Telemetry Board\Stage 2 - Combined.PcbDoc +Date : 2021-04-12 +Time : 11:50:53 PM + +WARNING: Zero hole size multi-layer pad(s) detected + Pad U8-38(249.7mm,109.25mm) on Multi-Layer on Net GND + +WARNING: Multilayer Pads with 0 size Hole found + Pad U8-38(249.7mm,109.25mm) on Multi-Layer + +Processing Rule : Clearance Constraint (Gap=0.2mm) (OnLayer('Bottom Layer')),(All) +Rule Violations :0 + +Processing Rule : Clearance Constraint (Gap=0.2mm) (OnLayer('Top Layer')),(All) +Rule Violations :0 + +Processing Rule : Clearance Constraint (Gap=0.2mm) (All),(All) +Rule Violations :0 + +Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All) +Rule Violations :0 + +Processing Rule : Un-Routed Net Constraint ( (All) ) +Rule Violations :0 + +Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No) +Rule Violations :0 + +Processing Rule : Width Constraint (Min=0.127mm) (Max=2.54mm) (Preferred=0.254mm) (All) +Rule Violations :0 + +Processing Rule : Width Constraint (Min=0.09mm) (Max=2.54mm) (Preferred=0.254mm) (OnLayer('Top Layer')) +Rule Violations :0 + +Processing Rule : Width Constraint (Min=0.09mm) (Max=2.54mm) (Preferred=0.254mm) (OnLayer('Bottom Layer')) +Rule Violations :0 + +Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All) +Rule Violations :0 + +Processing Rule : Minimum Annular Ring (Minimum=0.13mm) (All) + Violation between Minimum Annular Ring: (Collision < 0.13mm) Via (248.3mm,108.55mm) from Top Layer to Bottom Layer (Annular Ring=0mm) On (Top Layer) + Violation between Minimum Annular Ring: (Collision < 0.13mm) Via (248.3mm,109.95mm) from Top Layer to Bottom Layer (Annular Ring=0mm) On (Top Layer) + Violation between Minimum Annular Ring: (Collision < 0.13mm) Via (249.7mm,108.55mm) from Top Layer to Bottom Layer (Annular Ring=0mm) On (Top Layer) + Violation between Minimum Annular Ring: (Collision < 0.13mm) Via (249.7mm,109.95mm) from Top Layer to Bottom Layer (Annular Ring=0mm) On (Top Layer) + Violation between Minimum Annular Ring: (Collision < 0.13mm) Via (249mm,107.85mm) from Top Layer to Bottom Layer (Annular Ring=0mm) On (Top Layer) + Violation between Minimum Annular Ring: (Collision < 0.13mm) Via (249mm,109.25mm) from Top Layer to Bottom Layer (Annular Ring=0mm) On (Top Layer) + Violation between Minimum Annular Ring: (Collision < 0.13mm) Via (249mm,110.65mm) from Top Layer to Bottom Layer (Annular Ring=0mm) On (Top Layer) + Violation between Minimum Annular Ring: (Collision < 0.13mm) Via (250.4mm,107.85mm) from Top Layer to Bottom Layer (Annular Ring=0mm) On (Top Layer) + Violation between Minimum Annular Ring: (Collision < 0.13mm) Via (250.4mm,109.25mm) from Top Layer to Bottom Layer (Annular Ring=0mm) On (Top Layer) + Violation between Minimum Annular Ring: (Collision < 0.13mm) Via (250.4mm,110.65mm) from Top Layer to Bottom Layer (Annular Ring=0mm) On (Top Layer) + Violation between Minimum Annular Ring: (Collision < 0.13mm) Via (251.1mm,108.55mm) from Top Layer to Bottom Layer (Annular Ring=0mm) On (Top Layer) + Violation between Minimum Annular Ring: (Collision < 0.13mm) Via (251.1mm,109.95mm) from Top Layer to Bottom Layer (Annular Ring=0mm) On (Top Layer) +Rule Violations :12 + +Processing Rule : Hole Size Constraint (Min=0.2mm) (Max=6.3mm) (All) +Rule Violations :0 + +Processing Rule : Hole To Hole Clearance (Gap=0.254mm) (All),(All) +Rule Violations :0 + +Processing Rule : Minimum Solder Mask Sliver (Gap=0.1mm) (All),(All) + Violation between Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_1-1(228mm,148.5mm) on Top Layer And Pad U9_1-2(228mm,147.865mm) on Top Layer [Top Solder] Mask Sliver [0.054mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_1-10(233.334mm,144.69mm) on Top Layer And Pad U9_1-11(233.334mm,145.325mm) on Top Layer [Top Solder] Mask Sliver [0.054mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_1-10(233.334mm,144.69mm) on Top Layer And Pad U9_1-9(233.334mm,144.055mm) on Top Layer [Top Solder] Mask Sliver [0.054mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_1-11(233.334mm,145.325mm) on Top Layer And Pad U9_1-12(233.334mm,145.96mm) on Top Layer [Top Solder] Mask Sliver [0.054mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_1-12(233.334mm,145.96mm) on Top Layer And Pad U9_1-13(233.334mm,146.595mm) on Top Layer [Top Solder] Mask Sliver [0.054mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_1-13(233.334mm,146.595mm) on Top Layer And Pad U9_1-14(233.334mm,147.23mm) on Top Layer [Top Solder] Mask Sliver [0.054mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_1-14(233.334mm,147.23mm) on Top Layer And Pad U9_1-15(233.334mm,147.865mm) on Top Layer [Top Solder] Mask Sliver [0.054mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_1-15(233.334mm,147.865mm) on Top Layer And Pad U9_1-16(233.334mm,148.5mm) on Top Layer [Top Solder] Mask Sliver [0.054mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_1-2(228mm,147.865mm) on Top Layer And Pad U9_1-3(228mm,147.23mm) on Top Layer [Top Solder] Mask Sliver [0.054mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_1-3(228mm,147.23mm) on Top Layer And Pad U9_1-4(228mm,146.595mm) on Top Layer [Top Solder] Mask Sliver [0.054mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_1-4(228mm,146.595mm) on Top Layer And Pad U9_1-5(228mm,145.96mm) on Top Layer [Top Solder] Mask Sliver [0.054mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_1-5(228mm,145.96mm) on Top Layer And Pad U9_1-6(228mm,145.325mm) on Top Layer [Top Solder] Mask Sliver [0.054mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_1-6(228mm,145.325mm) on Top Layer And Pad U9_1-7(228mm,144.69mm) on Top Layer [Top Solder] Mask Sliver [0.054mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_1-7(228mm,144.69mm) on Top Layer And Pad U9_1-8(228mm,144.055mm) on Top Layer [Top Solder] Mask Sliver [0.054mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_2-1(229mm,38.5mm) on Top Layer And Pad U9_2-2(229mm,37.865mm) on Top Layer [Top Solder] Mask Sliver [0.054mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_2-10(234.334mm,34.69mm) on Top Layer And Pad U9_2-11(234.334mm,35.325mm) on Top Layer [Top Solder] Mask Sliver [0.054mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_2-10(234.334mm,34.69mm) on Top Layer And Pad U9_2-9(234.334mm,34.055mm) on Top Layer [Top Solder] Mask Sliver [0.054mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_2-11(234.334mm,35.325mm) on Top Layer And Pad U9_2-12(234.334mm,35.96mm) on Top Layer [Top Solder] Mask Sliver [0.054mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_2-12(234.334mm,35.96mm) on Top Layer And Pad U9_2-13(234.334mm,36.595mm) on Top Layer [Top Solder] Mask Sliver [0.054mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_2-13(234.334mm,36.595mm) on Top Layer And Pad U9_2-14(234.334mm,37.23mm) on Top Layer [Top Solder] Mask Sliver [0.054mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_2-14(234.334mm,37.23mm) on Top Layer And Pad U9_2-15(234.334mm,37.865mm) on Top Layer [Top Solder] Mask Sliver [0.054mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_2-15(234.334mm,37.865mm) on Top Layer And Pad U9_2-16(234.334mm,38.5mm) on Top Layer [Top Solder] Mask Sliver [0.054mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_2-2(229mm,37.865mm) on Top Layer And Pad U9_2-3(229mm,37.23mm) on Top Layer [Top Solder] Mask Sliver [0.054mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_2-3(229mm,37.23mm) on Top Layer And Pad U9_2-4(229mm,36.595mm) on Top Layer [Top Solder] Mask Sliver [0.054mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_2-4(229mm,36.595mm) on Top Layer And Pad U9_2-5(229mm,35.96mm) on Top Layer [Top Solder] Mask Sliver [0.054mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_2-5(229mm,35.96mm) on Top Layer And Pad U9_2-6(229mm,35.325mm) on Top Layer [Top Solder] Mask Sliver [0.054mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_2-6(229mm,35.325mm) on Top Layer And Pad U9_2-7(229mm,34.69mm) on Top Layer [Top Solder] Mask Sliver [0.054mm] + Violation between Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_2-7(229mm,34.69mm) on Top Layer And Pad U9_2-8(229mm,34.055mm) on Top Layer [Top Solder] Mask Sliver [0.054mm] +Rule Violations :28 + +Processing Rule : Silk To Solder Mask (Clearance=0.15mm) (IsPad),(All) + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.15mm) Between Pad J3_1-5(17.54mm,135.77mm) on Multi-Layer And Track (18.048mm,125.737mm)(18.048mm,145.803mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (Collision < 0.15mm) Between Pad J3_2-5(17.54mm,93.27mm) on Multi-Layer And Track (18.048mm,83.237mm)(18.048mm,103.303mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.131mm < 0.15mm) Between Pad L2-2(57.86mm,152.913mm) on Top Layer And Track (37.508mm,151.008mm)(104.12mm,151.008mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.131mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED1-1(178mm,75.5mm) on Top Layer And Track (173.936mm,73.976mm)(179.016mm,73.976mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED1-1(178mm,75.5mm) on Top Layer And Track (173.936mm,77.024mm)(179.016mm,77.024mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED1-2(175mm,75.5mm) on Top Layer And Track (173.936mm,73.976mm)(179.016mm,73.976mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED1-2(175mm,75.5mm) on Top Layer And Track (173.936mm,77.024mm)(179.016mm,77.024mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED2-1(178mm,83.5mm) on Top Layer And Track (173.936mm,81.976mm)(179.016mm,81.976mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED2-1(178mm,83.5mm) on Top Layer And Track (173.936mm,85.024mm)(179.016mm,85.024mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED2-2(175mm,83.5mm) on Top Layer And Track (173.936mm,81.976mm)(179.016mm,81.976mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED2-2(175mm,83.5mm) on Top Layer And Track (173.936mm,85.024mm)(179.016mm,85.024mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED3-1(178mm,91.5mm) on Top Layer And Track (173.936mm,89.976mm)(179.016mm,89.976mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED3-1(178mm,91.5mm) on Top Layer And Track (173.936mm,93.024mm)(179.016mm,93.024mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED3-2(175mm,91.5mm) on Top Layer And Track (173.936mm,89.976mm)(179.016mm,89.976mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED3-2(175mm,91.5mm) on Top Layer And Track (173.936mm,93.024mm)(179.016mm,93.024mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED4-1(178mm,99.5mm) on Top Layer And Track (173.936mm,101.024mm)(179.016mm,101.024mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED4-1(178mm,99.5mm) on Top Layer And Track (173.936mm,97.976mm)(179.016mm,97.976mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED4-2(175mm,99.5mm) on Top Layer And Track (173.936mm,101.024mm)(179.016mm,101.024mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED4-2(175mm,99.5mm) on Top Layer And Track (173.936mm,97.976mm)(179.016mm,97.976mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED5_1-1(251.5mm,158mm) on Top Layer And Track (247.436mm,156.476mm)(252.516mm,156.476mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED5_1-1(251.5mm,158mm) on Top Layer And Track (247.436mm,159.524mm)(252.516mm,159.524mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED5_1-2(248.5mm,158mm) on Top Layer And Track (247.436mm,156.476mm)(252.516mm,156.476mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED5_1-2(248.5mm,158mm) on Top Layer And Track (247.436mm,159.524mm)(252.516mm,159.524mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED5_2-1(252.5mm,48mm) on Top Layer And Track (248.436mm,46.476mm)(253.516mm,46.476mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED5_2-1(252.5mm,48mm) on Top Layer And Track (248.436mm,49.524mm)(253.516mm,49.524mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED5_2-2(249.5mm,48mm) on Top Layer And Track (248.436mm,46.476mm)(253.516mm,46.476mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED5_2-2(249.5mm,48mm) on Top Layer And Track (248.436mm,49.524mm)(253.516mm,49.524mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED6_1-1(251.5mm,154mm) on Top Layer And Track (247.436mm,152.476mm)(252.516mm,152.476mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED6_1-1(251.5mm,154mm) on Top Layer And Track (247.436mm,155.524mm)(252.516mm,155.524mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED6_1-2(248.5mm,154mm) on Top Layer And Track (247.436mm,152.476mm)(252.516mm,152.476mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED6_1-2(248.5mm,154mm) on Top Layer And Track (247.436mm,155.524mm)(252.516mm,155.524mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED6_2-1(252.5mm,44mm) on Top Layer And Track (248.436mm,42.476mm)(253.516mm,42.476mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED6_2-1(252.5mm,44mm) on Top Layer And Track (248.436mm,45.524mm)(253.516mm,45.524mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED6_2-2(249.5mm,44mm) on Top Layer And Track (248.436mm,42.476mm)(253.516mm,42.476mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED6_2-2(249.5mm,44mm) on Top Layer And Track (248.436mm,45.524mm)(253.516mm,45.524mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED7-1(38mm,65.5mm) on Top Layer And Track (36.476mm,64.484mm)(36.476mm,69.564mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED7-1(38mm,65.5mm) on Top Layer And Track (39.524mm,64.484mm)(39.524mm,69.564mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED7-2(38mm,68.5mm) on Top Layer And Track (36.476mm,64.484mm)(36.476mm,69.564mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED7-2(38mm,68.5mm) on Top Layer And Track (39.524mm,64.484mm)(39.524mm,69.564mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.149mm < 0.15mm) Between Pad U9_1-10(233.334mm,144.69mm) on Top Layer And Track (234.281mm,143.621mm)(234.281mm,148.955mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.149mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.149mm < 0.15mm) Between Pad U9_1-11(233.334mm,145.325mm) on Top Layer And Track (234.281mm,143.621mm)(234.281mm,148.955mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.149mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.149mm < 0.15mm) Between Pad U9_1-12(233.334mm,145.96mm) on Top Layer And Track (234.281mm,143.621mm)(234.281mm,148.955mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.149mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.149mm < 0.15mm) Between Pad U9_1-13(233.334mm,146.595mm) on Top Layer And Track (234.281mm,143.621mm)(234.281mm,148.955mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.149mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.149mm < 0.15mm) Between Pad U9_1-14(233.334mm,147.23mm) on Top Layer And Track (234.281mm,143.621mm)(234.281mm,148.955mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.149mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.149mm < 0.15mm) Between Pad U9_1-15(233.334mm,147.865mm) on Top Layer And Track (234.281mm,143.621mm)(234.281mm,148.955mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.149mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.149mm < 0.15mm) Between Pad U9_1-16(233.334mm,148.5mm) on Top Layer And Track (234.281mm,143.621mm)(234.281mm,148.955mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.149mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.143mm < 0.15mm) Between Pad U9_1-8(228mm,144.055mm) on Top Layer And Track (227.042mm,143.621mm)(234.281mm,143.621mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.143mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.143mm < 0.15mm) Between Pad U9_1-9(233.334mm,144.055mm) on Top Layer And Track (227.042mm,143.621mm)(234.281mm,143.621mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.143mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.149mm < 0.15mm) Between Pad U9_1-9(233.334mm,144.055mm) on Top Layer And Track (234.281mm,143.621mm)(234.281mm,148.955mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.149mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.149mm < 0.15mm) Between Pad U9_2-10(234.334mm,34.69mm) on Top Layer And Track (235.281mm,33.621mm)(235.281mm,38.955mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.149mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.149mm < 0.15mm) Between Pad U9_2-11(234.334mm,35.325mm) on Top Layer And Track (235.281mm,33.621mm)(235.281mm,38.955mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.149mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.149mm < 0.15mm) Between Pad U9_2-12(234.334mm,35.96mm) on Top Layer And Track (235.281mm,33.621mm)(235.281mm,38.955mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.149mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.149mm < 0.15mm) Between Pad U9_2-13(234.334mm,36.595mm) on Top Layer And Track (235.281mm,33.621mm)(235.281mm,38.955mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.149mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.149mm < 0.15mm) Between Pad U9_2-14(234.334mm,37.23mm) on Top Layer And Track (235.281mm,33.621mm)(235.281mm,38.955mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.149mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.149mm < 0.15mm) Between Pad U9_2-15(234.334mm,37.865mm) on Top Layer And Track (235.281mm,33.621mm)(235.281mm,38.955mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.149mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.149mm < 0.15mm) Between Pad U9_2-16(234.334mm,38.5mm) on Top Layer And Track (235.281mm,33.621mm)(235.281mm,38.955mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.149mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.143mm < 0.15mm) Between Pad U9_2-8(229mm,34.055mm) on Top Layer And Track (228.042mm,33.621mm)(235.281mm,33.621mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.143mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.143mm < 0.15mm) Between Pad U9_2-9(234.334mm,34.055mm) on Top Layer And Track (228.042mm,33.621mm)(235.281mm,33.621mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.143mm] + Violation between Silk To Solder Mask Clearance Constraint: (0.149mm < 0.15mm) Between Pad U9_2-9(234.334mm,34.055mm) on Top Layer And Track (235.281mm,33.621mm)(235.281mm,38.955mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.149mm] +Rule Violations :59 + +Processing Rule : Silk to Silk (Clearance=0mm) (All),(All) +Rule Violations :0 + +Processing Rule : Net Antennae (Tolerance=0mm) (All) + Violation between Net Antennae: Via (248.3mm,108.55mm) from Top Layer to Bottom Layer + Violation between Net Antennae: Via (248.3mm,109.95mm) from Top Layer to Bottom Layer + Violation between Net Antennae: Via (249mm,107.85mm) from Top Layer to Bottom Layer + Violation between Net Antennae: Via (249mm,110.65mm) from Top Layer to Bottom Layer + Violation between Net Antennae: Via (250.4mm,107.85mm) from Top Layer to Bottom Layer + Violation between Net Antennae: Via (250.4mm,110.65mm) from Top Layer to Bottom Layer + Violation between Net Antennae: Via (251.1mm,108.55mm) from Top Layer to Bottom Layer + Violation between Net Antennae: Via (251.1mm,109.95mm) from Top Layer to Bottom Layer +Rule Violations :8 + +Processing Rule : Room CANbus_0 (Bounding Region = (893.5mm, 470mm, 973.5mm, 492.5mm) (InComponentClass('CANbus_0')) +Rule Violations :0 + +Processing Rule : Room ESP32_0 (Bounding Region = (1111.5mm, 440.5mm, 1178.5mm, 474.5mm) (InComponentClass('ESP32_0')) +Rule Violations :0 + +Processing Rule : Room MCU JTAG_0 (Bounding Region = (1016.5mm, 480mm, 1043mm, 492.5mm) (InComponentClass('MCU JTAG_0')) +Rule Violations :0 + +Processing Rule : Room CANbus_1 (Bounding Region = (893.5mm, 427.5mm, 973.5mm, 450mm) (InComponentClass('CANbus_1')) +Rule Violations :0 + +Processing Rule : Room RTC_0 (Bounding Region = (1021.5mm, 356.5mm, 1057.5mm, 405.5mm) (InComponentClass('RTC_0')) +Rule Violations :0 + +Processing Rule : Room RS-232_0 (Bounding Region = (1130mm, 402.5mm, 1182mm, 436.5mm) (InComponentClass('RS-232_0')) +Rule Violations :0 + +Processing Rule : Room GPS_0 (Bounding Region = (877.5mm, 365mm, 958mm, 420.5mm) (InComponentClass('GPS_0')) +Rule Violations :0 + +Processing Rule : Room Main (Bounding Region = (1000.5mm, 423.5mm, 1065mm, 476.5mm) (InComponentClass('Main')) +Rule Violations :0 + +Processing Rule : Room IMU_0 (Bounding Region = (1067.5mm, 350.5mm, 1093.5mm, 393mm) (InComponentClass('IMU_0')) +Rule Violations :0 + +Processing Rule : Room SMPS_DOWN (Bounding Region = (940mm, 496mm, 1011.5mm, 523mm) (InComponentClass('SMPS_DOWN')) +Rule Violations :0 + +Processing Rule : Room UART_ESP32 (Bounding Region = (1095mm, 480.5mm, 1179.5mm, 509.5mm) (InComponentClass('UART_ESP32')) +Rule Violations :0 + +Processing Rule : Room SD Card_0 (Bounding Region = (967.5mm, 349.5mm, 1014.5mm, 393.5mm) (InComponentClass('SD Card_0')) +Rule Violations :0 + +Processing Rule : Room Supercapacitor0 (Bounding Region = (989.5mm, 444.5mm, 1030.5mm, 479.5mm) (InComponentClass('Supercapacitor0')) +Rule Violations :0 + +Processing Rule : Room MCU Reset Button_0 (Bounding Region = (899mm, 508.5mm, 922mm, 521mm) (InComponentClass('MCU Reset Button_0')) +Rule Violations :0 + +Processing Rule : Room MCU USB-UART_0 (Bounding Region = (1103mm, 370.5mm, 1179.5mm, 399mm) (InComponentClass('MCU USB-UART_0')) +Rule Violations :0 + +Processing Rule : Room MCU Power_0 (Bounding Region = (1013mm, 408mm, 1062mm, 457mm) (InComponentClass('MCU Power_0')) +Rule Violations :0 + +Processing Rule : Room MCU LEDs_0 (Bounding Region = (1067mm, 418mm, 1085.5mm, 451.5mm) (InComponentClass('MCU LEDs_0')) +Rule Violations :0 + +Processing Rule : Room MCU Button_0 (Bounding Region = (1155.5mm, 355mm, 1179.5mm, 367mm) (InComponentClass('MCU Button_0')) +Rule Violations :0 + +Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All) +Rule Violations :0 + + +Violations Detected : 107 +Waived Violations : 0 +Time Elapsed : 00:00:02 \ No newline at end of file diff --git a/Hardware/AltiumProject/2020-2021 Telemetry Board/Project Outputs for 2020-2021 Telemetry Board/Design Rule Check - Stage 2 - Combined.html b/Hardware/AltiumProject/2020-2021 Telemetry Board/Project Outputs for 2020-2021 Telemetry Board/Design Rule Check - Stage 2 - Combined.html new file mode 100644 index 0000000..c2a36e8 --- /dev/null +++ b/Hardware/AltiumProject/2020-2021 Telemetry Board/Project Outputs for 2020-2021 Telemetry Board/Design Rule Check - Stage 2 - Combined.html @@ -0,0 +1,775 @@ + + + +Design Rule Verification Report + +Altium

Design Rule Verification Report

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Date:2021-04-12
Time:11:50:53 PM
Elapsed Time:00:00:02
Filename:C:\SunseekerTelemetry\Hardware\AltiumProject\2020-2021 Telemetry Board\Stage 2 - Combined.PcbDoc
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Warnings:2
Rule Violations:107
+

Summary

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WarningsCount
Zero hole size multi-layer pad(s) detected1
Multilayer Pads with 0 size Hole found1
Total2

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Rule ViolationsCount
Clearance Constraint (Gap=0.2mm) (OnLayer('Bottom Layer')),(All)0
Clearance Constraint (Gap=0.2mm) (OnLayer('Top Layer')),(All)0
Clearance Constraint (Gap=0.2mm) (All),(All)0
Short-Circuit Constraint (Allowed=No) (All),(All)0
Un-Routed Net Constraint ( (All) )0
Modified Polygon (Allow modified: No), (Allow shelved: No)0
Width Constraint (Min=0.127mm) (Max=2.54mm) (Preferred=0.254mm) (All)0
Width Constraint (Min=0.09mm) (Max=2.54mm) (Preferred=0.254mm) (OnLayer('Top Layer'))0
Width Constraint (Min=0.09mm) (Max=2.54mm) (Preferred=0.254mm) (OnLayer('Bottom Layer'))0
Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)0
Minimum Annular Ring (Minimum=0.13mm) (All)12
Hole Size Constraint (Min=0.2mm) (Max=6.3mm) (All)0
Hole To Hole Clearance (Gap=0.254mm) (All),(All)0
Minimum Solder Mask Sliver (Gap=0.1mm) (All),(All)28
Silk To Solder Mask (Clearance=0.15mm) (IsPad),(All)59
Silk to Silk (Clearance=0mm) (All),(All)0
Net Antennae (Tolerance=0mm) (All)8
Room CANbus_0 (Bounding Region = (893.5mm, 470mm, 973.5mm, 492.5mm) (InComponentClass('CANbus_0'))0
Room ESP32_0 (Bounding Region = (1111.5mm, 440.5mm, 1178.5mm, 474.5mm) (InComponentClass('ESP32_0'))0
Room MCU JTAG_0 (Bounding Region = (1016.5mm, 480mm, 1043mm, 492.5mm) (InComponentClass('MCU JTAG_0'))0
Room CANbus_1 (Bounding Region = (893.5mm, 427.5mm, 973.5mm, 450mm) (InComponentClass('CANbus_1'))0
Room RTC_0 (Bounding Region = (1021.5mm, 356.5mm, 1057.5mm, 405.5mm) (InComponentClass('RTC_0'))0
Room RS-232_0 (Bounding Region = (1130mm, 402.5mm, 1182mm, 436.5mm) (InComponentClass('RS-232_0'))0
Room GPS_0 (Bounding Region = (877.5mm, 365mm, 958mm, 420.5mm) (InComponentClass('GPS_0'))0
Room Main (Bounding Region = (1000.5mm, 423.5mm, 1065mm, 476.5mm) (InComponentClass('Main'))0
Room IMU_0 (Bounding Region = (1067.5mm, 350.5mm, 1093.5mm, 393mm) (InComponentClass('IMU_0'))0
Room SMPS_DOWN (Bounding Region = (940mm, 496mm, 1011.5mm, 523mm) (InComponentClass('SMPS_DOWN'))0
Room UART_ESP32 (Bounding Region = (1095mm, 480.5mm, 1179.5mm, 509.5mm) (InComponentClass('UART_ESP32'))0
Room SD Card_0 (Bounding Region = (967.5mm, 349.5mm, 1014.5mm, 393.5mm) (InComponentClass('SD Card_0'))0
Room Supercapacitor0 (Bounding Region = (989.5mm, 444.5mm, 1030.5mm, 479.5mm) (InComponentClass('Supercapacitor0'))0
Room MCU Reset Button_0 (Bounding Region = (899mm, 508.5mm, 922mm, 521mm) (InComponentClass('MCU Reset Button_0'))0
Room MCU USB-UART_0 (Bounding Region = (1103mm, 370.5mm, 1179.5mm, 399mm) (InComponentClass('MCU USB-UART_0'))0
Room MCU Power_0 (Bounding Region = (1013mm, 408mm, 1062mm, 457mm) (InComponentClass('MCU Power_0'))0
Room MCU LEDs_0 (Bounding Region = (1067mm, 418mm, 1085.5mm, 451.5mm) (InComponentClass('MCU LEDs_0'))0
Room MCU Button_0 (Bounding Region = (1155.5mm, 355mm, 1179.5mm, 367mm) (InComponentClass('MCU Button_0'))0
Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)0
Total107

Warnings

 + + + + + + +
Zero hole size multi-layer pad(s) detected
Pad U8-38(249.7mm,109.25mm) on Multi-Layer on Net GND
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+ + + + + + +
Multilayer Pads with 0 size Hole found
Pad U8-38(249.7mm,109.25mm) on Multi-Layer
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Minimum Annular Ring (Minimum=0.13mm) (All)
Minimum Annular Ring: (Collision < 0.13mm) Via (248.3mm,108.55mm) from Top Layer to Bottom Layer (Annular Ring=0mm) On (Top Layer)
Minimum Annular Ring: (Collision < 0.13mm) Via (248.3mm,109.95mm) from Top Layer to Bottom Layer (Annular Ring=0mm) On (Top Layer)
Minimum Annular Ring: (Collision < 0.13mm) Via (249.7mm,108.55mm) from Top Layer to Bottom Layer (Annular Ring=0mm) On (Top Layer)
Minimum Annular Ring: (Collision < 0.13mm) Via (249.7mm,109.95mm) from Top Layer to Bottom Layer (Annular Ring=0mm) On (Top Layer)
Minimum Annular Ring: (Collision < 0.13mm) Via (249mm,107.85mm) from Top Layer to Bottom Layer (Annular Ring=0mm) On (Top Layer)
Minimum Annular Ring: (Collision < 0.13mm) Via (249mm,109.25mm) from Top Layer to Bottom Layer (Annular Ring=0mm) On (Top Layer)
Minimum Annular Ring: (Collision < 0.13mm) Via (249mm,110.65mm) from Top Layer to Bottom Layer (Annular Ring=0mm) On (Top Layer)
Minimum Annular Ring: (Collision < 0.13mm) Via (250.4mm,107.85mm) from Top Layer to Bottom Layer (Annular Ring=0mm) On (Top Layer)
Minimum Annular Ring: (Collision < 0.13mm) Via (250.4mm,109.25mm) from Top Layer to Bottom Layer (Annular Ring=0mm) On (Top Layer)
Minimum Annular Ring: (Collision < 0.13mm) Via (250.4mm,110.65mm) from Top Layer to Bottom Layer (Annular Ring=0mm) On (Top Layer)
Minimum Annular Ring: (Collision < 0.13mm) Via (251.1mm,108.55mm) from Top Layer to Bottom Layer (Annular Ring=0mm) On (Top Layer)
Minimum Annular Ring: (Collision < 0.13mm) Via (251.1mm,109.95mm) from Top Layer to Bottom Layer (Annular Ring=0mm) On (Top Layer)
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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Minimum Solder Mask Sliver (Gap=0.1mm) (All),(All)
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_1-1(228mm,148.5mm) on Top Layer And Pad U9_1-2(228mm,147.865mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_1-10(233.334mm,144.69mm) on Top Layer And Pad U9_1-11(233.334mm,145.325mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_1-10(233.334mm,144.69mm) on Top Layer And Pad U9_1-9(233.334mm,144.055mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_1-11(233.334mm,145.325mm) on Top Layer And Pad U9_1-12(233.334mm,145.96mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_1-12(233.334mm,145.96mm) on Top Layer And Pad U9_1-13(233.334mm,146.595mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_1-13(233.334mm,146.595mm) on Top Layer And Pad U9_1-14(233.334mm,147.23mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_1-14(233.334mm,147.23mm) on Top Layer And Pad U9_1-15(233.334mm,147.865mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_1-15(233.334mm,147.865mm) on Top Layer And Pad U9_1-16(233.334mm,148.5mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_1-2(228mm,147.865mm) on Top Layer And Pad U9_1-3(228mm,147.23mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_1-3(228mm,147.23mm) on Top Layer And Pad U9_1-4(228mm,146.595mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_1-4(228mm,146.595mm) on Top Layer And Pad U9_1-5(228mm,145.96mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_1-5(228mm,145.96mm) on Top Layer And Pad U9_1-6(228mm,145.325mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_1-6(228mm,145.325mm) on Top Layer And Pad U9_1-7(228mm,144.69mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_1-7(228mm,144.69mm) on Top Layer And Pad U9_1-8(228mm,144.055mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_2-1(229mm,38.5mm) on Top Layer And Pad U9_2-2(229mm,37.865mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_2-10(234.334mm,34.69mm) on Top Layer And Pad U9_2-11(234.334mm,35.325mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_2-10(234.334mm,34.69mm) on Top Layer And Pad U9_2-9(234.334mm,34.055mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_2-11(234.334mm,35.325mm) on Top Layer And Pad U9_2-12(234.334mm,35.96mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_2-12(234.334mm,35.96mm) on Top Layer And Pad U9_2-13(234.334mm,36.595mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_2-13(234.334mm,36.595mm) on Top Layer And Pad U9_2-14(234.334mm,37.23mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_2-14(234.334mm,37.23mm) on Top Layer And Pad U9_2-15(234.334mm,37.865mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_2-15(234.334mm,37.865mm) on Top Layer And Pad U9_2-16(234.334mm,38.5mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_2-2(229mm,37.865mm) on Top Layer And Pad U9_2-3(229mm,37.23mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_2-3(229mm,37.23mm) on Top Layer And Pad U9_2-4(229mm,36.595mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_2-4(229mm,36.595mm) on Top Layer And Pad U9_2-5(229mm,35.96mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_2-5(229mm,35.96mm) on Top Layer And Pad U9_2-6(229mm,35.325mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_2-6(229mm,35.325mm) on Top Layer And Pad U9_2-7(229mm,34.69mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
Minimum Solder Mask Sliver Constraint: (0.054mm < 0.1mm) Between Pad U9_2-7(229mm,34.69mm) on Top Layer And Pad U9_2-8(229mm,34.055mm) on Top Layer [Top Solder] Mask Sliver [0.054mm]
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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Silk To Solder Mask (Clearance=0.15mm) (IsPad),(All)
Silk To Solder Mask Clearance Constraint: (Collision < 0.15mm) Between Pad J3_1-5(17.54mm,135.77mm) on Multi-Layer And Track (18.048mm,125.737mm)(18.048mm,145.803mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (Collision < 0.15mm) Between Pad J3_2-5(17.54mm,93.27mm) on Multi-Layer And Track (18.048mm,83.237mm)(18.048mm,103.303mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0mm]
Silk To Solder Mask Clearance Constraint: (0.131mm < 0.15mm) Between Pad L2-2(57.86mm,152.913mm) on Top Layer And Track (37.508mm,151.008mm)(104.12mm,151.008mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.131mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED1-1(178mm,75.5mm) on Top Layer And Track (173.936mm,73.976mm)(179.016mm,73.976mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED1-1(178mm,75.5mm) on Top Layer And Track (173.936mm,77.024mm)(179.016mm,77.024mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED1-2(175mm,75.5mm) on Top Layer And Track (173.936mm,73.976mm)(179.016mm,73.976mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED1-2(175mm,75.5mm) on Top Layer And Track (173.936mm,77.024mm)(179.016mm,77.024mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED2-1(178mm,83.5mm) on Top Layer And Track (173.936mm,81.976mm)(179.016mm,81.976mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED2-1(178mm,83.5mm) on Top Layer And Track (173.936mm,85.024mm)(179.016mm,85.024mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED2-2(175mm,83.5mm) on Top Layer And Track (173.936mm,81.976mm)(179.016mm,81.976mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED2-2(175mm,83.5mm) on Top Layer And Track (173.936mm,85.024mm)(179.016mm,85.024mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED3-1(178mm,91.5mm) on Top Layer And Track (173.936mm,89.976mm)(179.016mm,89.976mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED3-1(178mm,91.5mm) on Top Layer And Track (173.936mm,93.024mm)(179.016mm,93.024mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED3-2(175mm,91.5mm) on Top Layer And Track (173.936mm,89.976mm)(179.016mm,89.976mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED3-2(175mm,91.5mm) on Top Layer And Track (173.936mm,93.024mm)(179.016mm,93.024mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED4-1(178mm,99.5mm) on Top Layer And Track (173.936mm,101.024mm)(179.016mm,101.024mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED4-1(178mm,99.5mm) on Top Layer And Track (173.936mm,97.976mm)(179.016mm,97.976mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED4-2(175mm,99.5mm) on Top Layer And Track (173.936mm,101.024mm)(179.016mm,101.024mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED4-2(175mm,99.5mm) on Top Layer And Track (173.936mm,97.976mm)(179.016mm,97.976mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED5_1-1(251.5mm,158mm) on Top Layer And Track (247.436mm,156.476mm)(252.516mm,156.476mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED5_1-1(251.5mm,158mm) on Top Layer And Track (247.436mm,159.524mm)(252.516mm,159.524mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED5_1-2(248.5mm,158mm) on Top Layer And Track (247.436mm,156.476mm)(252.516mm,156.476mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED5_1-2(248.5mm,158mm) on Top Layer And Track (247.436mm,159.524mm)(252.516mm,159.524mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED5_2-1(252.5mm,48mm) on Top Layer And Track (248.436mm,46.476mm)(253.516mm,46.476mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED5_2-1(252.5mm,48mm) on Top Layer And Track (248.436mm,49.524mm)(253.516mm,49.524mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED5_2-2(249.5mm,48mm) on Top Layer And Track (248.436mm,46.476mm)(253.516mm,46.476mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED5_2-2(249.5mm,48mm) on Top Layer And Track (248.436mm,49.524mm)(253.516mm,49.524mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED6_1-1(251.5mm,154mm) on Top Layer And Track (247.436mm,152.476mm)(252.516mm,152.476mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED6_1-1(251.5mm,154mm) on Top Layer And Track (247.436mm,155.524mm)(252.516mm,155.524mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED6_1-2(248.5mm,154mm) on Top Layer And Track (247.436mm,152.476mm)(252.516mm,152.476mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED6_1-2(248.5mm,154mm) on Top Layer And Track (247.436mm,155.524mm)(252.516mm,155.524mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED6_2-1(252.5mm,44mm) on Top Layer And Track (248.436mm,42.476mm)(253.516mm,42.476mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED6_2-1(252.5mm,44mm) on Top Layer And Track (248.436mm,45.524mm)(253.516mm,45.524mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED6_2-2(249.5mm,44mm) on Top Layer And Track (248.436mm,42.476mm)(253.516mm,42.476mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED6_2-2(249.5mm,44mm) on Top Layer And Track (248.436mm,45.524mm)(253.516mm,45.524mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED7-1(38mm,65.5mm) on Top Layer And Track (36.476mm,64.484mm)(36.476mm,69.564mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED7-1(38mm,65.5mm) on Top Layer And Track (39.524mm,64.484mm)(39.524mm,69.564mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED7-2(38mm,68.5mm) on Top Layer And Track (36.476mm,64.484mm)(36.476mm,69.564mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.124mm < 0.15mm) Between Pad LED7-2(38mm,68.5mm) on Top Layer And Track (39.524mm,64.484mm)(39.524mm,69.564mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.124mm]
Silk To Solder Mask Clearance Constraint: (0.149mm < 0.15mm) Between Pad U9_1-10(233.334mm,144.69mm) on Top Layer And Track (234.281mm,143.621mm)(234.281mm,148.955mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.149mm]
Silk To Solder Mask Clearance Constraint: (0.149mm < 0.15mm) Between Pad U9_1-11(233.334mm,145.325mm) on Top Layer And Track (234.281mm,143.621mm)(234.281mm,148.955mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.149mm]
Silk To Solder Mask Clearance Constraint: (0.149mm < 0.15mm) Between Pad U9_1-12(233.334mm,145.96mm) on Top Layer And Track (234.281mm,143.621mm)(234.281mm,148.955mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.149mm]
Silk To Solder Mask Clearance Constraint: (0.149mm < 0.15mm) Between Pad U9_1-13(233.334mm,146.595mm) on Top Layer And Track (234.281mm,143.621mm)(234.281mm,148.955mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.149mm]
Silk To Solder Mask Clearance Constraint: (0.149mm < 0.15mm) Between Pad U9_1-14(233.334mm,147.23mm) on Top Layer And Track (234.281mm,143.621mm)(234.281mm,148.955mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.149mm]
Silk To Solder Mask Clearance Constraint: (0.149mm < 0.15mm) Between Pad U9_1-15(233.334mm,147.865mm) on Top Layer And Track (234.281mm,143.621mm)(234.281mm,148.955mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.149mm]
Silk To Solder Mask Clearance Constraint: (0.149mm < 0.15mm) Between Pad U9_1-16(233.334mm,148.5mm) on Top Layer And Track (234.281mm,143.621mm)(234.281mm,148.955mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.149mm]
Silk To Solder Mask Clearance Constraint: (0.143mm < 0.15mm) Between Pad U9_1-8(228mm,144.055mm) on Top Layer And Track (227.042mm,143.621mm)(234.281mm,143.621mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.143mm]
Silk To Solder Mask Clearance Constraint: (0.143mm < 0.15mm) Between Pad U9_1-9(233.334mm,144.055mm) on Top Layer And Track (227.042mm,143.621mm)(234.281mm,143.621mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.143mm]
Silk To Solder Mask Clearance Constraint: (0.149mm < 0.15mm) Between Pad U9_1-9(233.334mm,144.055mm) on Top Layer And Track (234.281mm,143.621mm)(234.281mm,148.955mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.149mm]
Silk To Solder Mask Clearance Constraint: (0.149mm < 0.15mm) Between Pad U9_2-10(234.334mm,34.69mm) on Top Layer And Track (235.281mm,33.621mm)(235.281mm,38.955mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.149mm]
Silk To Solder Mask Clearance Constraint: (0.149mm < 0.15mm) Between Pad U9_2-11(234.334mm,35.325mm) on Top Layer And Track (235.281mm,33.621mm)(235.281mm,38.955mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.149mm]
Silk To Solder Mask Clearance Constraint: (0.149mm < 0.15mm) Between Pad U9_2-12(234.334mm,35.96mm) on Top Layer And Track (235.281mm,33.621mm)(235.281mm,38.955mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.149mm]
Silk To Solder Mask Clearance Constraint: (0.149mm < 0.15mm) Between Pad U9_2-13(234.334mm,36.595mm) on Top Layer And Track (235.281mm,33.621mm)(235.281mm,38.955mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.149mm]
Silk To Solder Mask Clearance Constraint: (0.149mm < 0.15mm) Between Pad U9_2-14(234.334mm,37.23mm) on Top Layer And Track (235.281mm,33.621mm)(235.281mm,38.955mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.149mm]
Silk To Solder Mask Clearance Constraint: (0.149mm < 0.15mm) Between Pad U9_2-15(234.334mm,37.865mm) on Top Layer And Track (235.281mm,33.621mm)(235.281mm,38.955mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.149mm]
Silk To Solder Mask Clearance Constraint: (0.149mm < 0.15mm) Between Pad U9_2-16(234.334mm,38.5mm) on Top Layer And Track (235.281mm,33.621mm)(235.281mm,38.955mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.149mm]
Silk To Solder Mask Clearance Constraint: (0.143mm < 0.15mm) Between Pad U9_2-8(229mm,34.055mm) on Top Layer And Track (228.042mm,33.621mm)(235.281mm,33.621mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.143mm]
Silk To Solder Mask Clearance Constraint: (0.143mm < 0.15mm) Between Pad U9_2-9(234.334mm,34.055mm) on Top Layer And Track (228.042mm,33.621mm)(235.281mm,33.621mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.143mm]
Silk To Solder Mask Clearance Constraint: (0.149mm < 0.15mm) Between Pad U9_2-9(234.334mm,34.055mm) on Top Layer And Track (235.281mm,33.621mm)(235.281mm,38.955mm) on Top Overlay [Top Overlay] to [Top Solder] clearance [0.149mm]
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+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Net Antennae (Tolerance=0mm) (All)
Net Antennae: Via (248.3mm,108.55mm) from Top Layer to Bottom Layer
Net Antennae: Via (248.3mm,109.95mm) from Top Layer to Bottom Layer
Net Antennae: Via (249mm,107.85mm) from Top Layer to Bottom Layer
Net Antennae: Via (249mm,110.65mm) from Top Layer to Bottom Layer
Net Antennae: Via (250.4mm,107.85mm) from Top Layer to Bottom Layer
Net Antennae: Via (250.4mm,110.65mm) from Top Layer to Bottom Layer
Net Antennae: Via (251.1mm,108.55mm) from Top Layer to Bottom Layer
Net Antennae: Via (251.1mm,109.95mm) from Top Layer to Bottom Layer
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+ diff --git a/Hardware/AltiumProject/2020-2021 Telemetry Board/Stage 1 - Power.PcbDoc b/Hardware/AltiumProject/2020-2021 Telemetry Board/Stage 1 - Power.PcbDoc index 074cd80..9ec28fe 100644 Binary files a/Hardware/AltiumProject/2020-2021 Telemetry Board/Stage 1 - Power.PcbDoc and b/Hardware/AltiumProject/2020-2021 Telemetry Board/Stage 1 - Power.PcbDoc differ diff --git a/Hardware/AltiumProject/2020-2021 Telemetry Board/Stage 1 - Telemetry.PcbDoc b/Hardware/AltiumProject/2020-2021 Telemetry Board/Stage 1 - Telemetry.PcbDoc index 627ca25..1347555 100644 Binary files a/Hardware/AltiumProject/2020-2021 Telemetry Board/Stage 1 - Telemetry.PcbDoc and b/Hardware/AltiumProject/2020-2021 Telemetry Board/Stage 1 - Telemetry.PcbDoc differ diff --git a/Hardware/AltiumProject/2020-2021 Telemetry Board/Stage 2 - Combined.PcbDoc b/Hardware/AltiumProject/2020-2021 Telemetry Board/Stage 2 - Combined.PcbDoc new file mode 100644 index 0000000..d5ea7dd Binary files /dev/null and b/Hardware/AltiumProject/2020-2021 Telemetry Board/Stage 2 - Combined.PcbDoc differ