2020-2021 Sunseeker Telemetry and Lighting System
adc12_a.c
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1 //*****************************************************************************
2 //
3 // adc12_a.c - Driver for the adc12_a Module.
4 //
5 //*****************************************************************************
6 
7 //*****************************************************************************
8 //
11 //
12 //*****************************************************************************
13 
14 #include "inc/hw_memmap.h"
15 
16 #ifdef __MSP430_HAS_ADC12_PLUS__
17 #include "adc12_a.h"
18 
19 #include <assert.h>
20 
21 bool ADC12_A_init (uint16_t baseAddress,
22  uint16_t sampleHoldSignalSourceSelect,
23  uint8_t clockSourceSelect,
24  uint16_t clockSourceDivider)
25 {
26  //Make sure the ENC bit is cleared before initializing the ADC12_A
27  HWREG8(baseAddress + OFS_ADC12CTL0_L) &= ~ADC12ENC;
28 
29  bool retVal = STATUS_SUCCESS;
30 
31  //Turn OFF ADC12_A Module & Clear Interrupt Registers
32  HWREG16(baseAddress + OFS_ADC12CTL0) &= ~(ADC12ON + ADC12OVIE + ADC12TOVIE
33  + ADC12ENC + ADC12SC);
34  HWREG16(baseAddress + OFS_ADC12IE) &= 0x0000; //Reset ALL interrupt enables
35  HWREG16(baseAddress + OFS_ADC12IFG) &= 0x0000; //Reset ALL interrupt flags
36 
37  //Set ADC12_A Control 1
38  HWREG16(baseAddress + OFS_ADC12CTL1) =
39  sampleHoldSignalSourceSelect //Setup the Sample-and-Hold Source
40  + (clockSourceDivider & ADC12DIV_7) //Set Clock Divider
41  + clockSourceSelect; //Setup Clock Source
42 
43  //Set ADC12_A Control 2
44  HWREG16(baseAddress + OFS_ADC12CTL2) =
45  (clockSourceDivider & ADC12PDIV) //Set Clock Pre-Divider
46  + ADC12RES_2; //Default resolution to 12-bits
47 
48  return ( retVal) ;
49 }
50 
51 void ADC12_A_enable (uint16_t baseAddress)
52 {
53  //Enable the ADC12_A Module
54  HWREG8(baseAddress + OFS_ADC12CTL0_L) |= ADC12ON;
55 }
56 
57 void ADC12_A_disable (uint16_t baseAddress)
58 {
59  //Disable ADC12_A module
60  HWREG8(baseAddress + OFS_ADC12CTL0_L) &= ~ADC12ON;
61 }
62 
63 void ADC12_A_setupSamplingTimer (uint16_t baseAddress,
64  uint16_t clockCycleHoldCountLowMem,
65  uint16_t clockCycleHoldCountHighMem,
66  uint16_t multipleSamplesEnabled)
67 {
68  HWREG16(baseAddress + OFS_ADC12CTL1) |= ADC12SHP;
69 
70  //Reset clock cycle hold counts and msc bit before setting them
71  HWREG16(baseAddress + OFS_ADC12CTL0) &=
72  ~(ADC12SHT0_15 + ADC12SHT1_15 + ADC12MSC);
73 
74  //Set clock cycle hold counts and msc bit
75  HWREG16(baseAddress + OFS_ADC12CTL0) |= clockCycleHoldCountLowMem
76  + (clockCycleHoldCountHighMem << 4)
77  + multipleSamplesEnabled;
78 }
79 
80 
81 void ADC12_A_disableSamplingTimer (uint16_t baseAddress)
82 {
83  HWREG16(baseAddress + OFS_ADC12CTL1) &= ~(ADC12SHP);
84 }
85 
86 
87 void ADC12_A_configureMemory(uint16_t baseAddress,
88  ADC12_A_configureMemoryParam *param)
89 {
90  //Make sure the ENC bit is cleared before configuring a Memory Buffer Control
91  assert( !(HWREG16(baseAddress + OFS_ADC12CTL0) & ADC12ENC) );
92 
93  if(!(HWREG16(baseAddress + OFS_ADC12CTL0) & ADC12ENC))
94  {
95  //Set the offset in respect to ADC12MCTL0
96  uint16_t memoryBufferControlOffset =
97  (OFS_ADC12MCTL0 + param->memoryBufferControlIndex);
98 
99  //Reset the memory buffer control and Set the input source
100  HWREG8(baseAddress + memoryBufferControlOffset) =
101  param->inputSourceSelect //Set Input Source
102  + param->positiveRefVoltageSourceSelect //Set Vref+
103  + param->negativeRefVoltageSourceSelect //Set Vref-
104  + param->endOfSequence; //Set End of Sequence
105  }
106 }
107 void ADC12_A_enableInterrupt (uint16_t baseAddress,
108  uint32_t interruptMask)
109 {
110  if (interruptMask & ADC12_A_CONVERSION_TIME_OVERFLOW_IE) {
111  HWREG16(baseAddress + OFS_ADC12CTL0) |= ADC12TOVIE;
112  interruptMask &= ~ADC12_A_CONVERSION_TIME_OVERFLOW_IE;
113  }
114  if (interruptMask & ADC12_A_OVERFLOW_IE) {
115  HWREG16(baseAddress + OFS_ADC12CTL0) |= ADC12OVIE;
116  interruptMask &= ~ADC12_A_OVERFLOW_IE;
117  }
118 
119  HWREG16(baseAddress + OFS_ADC12IE) |= interruptMask;
120 }
121 
122 void ADC12_A_disableInterrupt (uint16_t baseAddress,
123  uint32_t interruptMask)
124 {
125  if (interruptMask & ADC12_A_CONVERSION_TIME_OVERFLOW_IE) {
126  HWREG16(baseAddress + OFS_ADC12CTL0) &= ~(ADC12TOVIE);
127  interruptMask &= ~ADC12_A_CONVERSION_TIME_OVERFLOW_IE;
128  }
129  if (interruptMask & ADC12_A_OVERFLOW_IE) {
130  HWREG16(baseAddress + OFS_ADC12CTL0) &= ~(ADC12OVIE);
131  interruptMask &= ~ADC12_A_OVERFLOW_IE;
132  }
133 
134  HWREG16(baseAddress + OFS_ADC12IE) &= ~(interruptMask);
135 }
136 
137 void ADC12_A_clearInterrupt (uint16_t baseAddress,
138  uint16_t memoryInterruptFlagMask)
139 {
140  HWREG16(baseAddress + OFS_ADC12IFG) &= ~(memoryInterruptFlagMask);
141 }
142 
143 uint16_t ADC12_A_getInterruptStatus (uint16_t baseAddress,
144  uint16_t memoryInterruptFlagMask)
145 {
146  return ( HWREG16(baseAddress + OFS_ADC12IFG) & memoryInterruptFlagMask );
147 }
148 
149 void ADC12_A_startConversion (uint16_t baseAddress,
150  uint16_t startingMemoryBufferIndex,
151  uint8_t conversionSequenceModeSelect)
152 {
153  //Reset the ENC bit to set the starting memory address and conversion mode
154  //sequence
155  HWREG8(baseAddress + OFS_ADC12CTL0_L) &= ~(ADC12ENC);
156  //Reset the bits about to be set
157  HWREG16(baseAddress + OFS_ADC12CTL1) &= ~(ADC12CSTARTADD_15 + ADC12CONSEQ_3);
158 
159  HWREG8(baseAddress + OFS_ADC12CTL1_H) |= (startingMemoryBufferIndex << 4);
160  HWREG8(baseAddress + OFS_ADC12CTL1_L) |= conversionSequenceModeSelect;
161  HWREG8(baseAddress + OFS_ADC12CTL0_L) |= ADC12ENC + ADC12SC;
162 }
163 
164 void ADC12_A_disableConversions (uint16_t baseAddress, bool preempt)
165 {
166  if (ADC12_A_PREEMPTCONVERSION == preempt) {
167  HWREG8(baseAddress + OFS_ADC12CTL1_L) &= ~(ADC12CONSEQ_3);
168  //Reset conversion sequence mode to single-channel, single-conversion
169  }
170  else if (~(HWREG8(baseAddress + OFS_ADC12CTL1_L) & ADC12CONSEQ_3)) {
171  //To prevent preemoption of a single-channel, single-conversion we must
172  //wait for the ADC core to finish the conversion.
173  while (ADC12_A_isBusy(baseAddress)) ;
174  }
175 
176  HWREG8(baseAddress + OFS_ADC12CTL0_L) &= ~(ADC12ENC);
177 }
178 
179 uint16_t ADC12_A_getResults (uint16_t baseAddress, uint8_t memoryBufferIndex)
180 {
181  //(0x20 + (memoryBufferIndex * 2)) == offset of ADC12MEMx
182  return ( HWREG16(baseAddress + (0x20 + (memoryBufferIndex * 2))) );
183 }
184 
185 void ADC12_A_setResolution (uint16_t baseAddress,
186  uint8_t resolutionSelect)
187 {
188  HWREG8(baseAddress + OFS_ADC12CTL2_L) &= ~(ADC12RES_3);
189  HWREG8(baseAddress + OFS_ADC12CTL2_L) |= resolutionSelect;
190 }
191 
192 void ADC12_A_setSampleHoldSignalInversion (uint16_t baseAddress,
193  uint16_t invertedSignal)
194 {
195  HWREG16(baseAddress + OFS_ADC12CTL1) &= ~(ADC12ISSH);
196  HWREG16(baseAddress + OFS_ADC12CTL1) |= invertedSignal;
197 }
198 
199 void ADC12_A_setDataReadBackFormat (uint16_t baseAddress,
200  uint8_t readBackFormat)
201 {
202  HWREG8(baseAddress + OFS_ADC12CTL2_L) &= ~(ADC12DF);
203  HWREG8(baseAddress + OFS_ADC12CTL2_L) |= readBackFormat;
204 }
205 
206 void ADC12_A_enableReferenceBurst (uint16_t baseAddress)
207 {
208  HWREG8(baseAddress + OFS_ADC12CTL2_L) |= ADC12REFBURST;
209 }
210 
211 void ADC12_A_disableReferenceBurst (uint16_t baseAddress)
212 {
213  HWREG8(baseAddress + OFS_ADC12CTL2_L) &= ~(ADC12REFBURST);
214 }
215 
216 void ADC12_A_setReferenceBufferSamplingRate (uint16_t baseAddress,
217  uint8_t samplingRateSelect)
218 {
219  HWREG8(baseAddress + OFS_ADC12CTL2_L) &= ~(ADC12SR);
220  HWREG8(baseAddress + OFS_ADC12CTL2_L) |= samplingRateSelect;
221 }
222 
223 uint32_t ADC12_A_getMemoryAddressForDMA (uint16_t baseAddress,
224  uint8_t memoryIndex)
225 {
226  return ( baseAddress + (0x20 + (memoryIndex * 2)) );
227 }
228 
229 uint16_t ADC12_A_isBusy (uint16_t baseAddress)
230 {
231  return (HWREG8(baseAddress + OFS_ADC12CTL1_L) & ADC12BUSY);
232 }
233 
234 
235 #endif
236 //*****************************************************************************
237 //
240 //
241 //*****************************************************************************
MPU_initThreeSegmentsParam param
#define HWREG8(x)
Definition: hw_memmap.h:41
#define HWREG16(x)
Definition: hw_memmap.h:39
#define STATUS_SUCCESS
Definition: hw_memmap.h:22