7 #ifndef __MSP430WARE_DMA_H__
8 #define __MSP430WARE_DMA_H__
12 #if defined(__MSP430_HAS_DMAX_3__) || defined(__MSP430_HAS_DMAX_6__)
31 typedef struct DMA_initParam {
42 uint8_t channelSelect;
57 uint16_t transferModeSelect;
61 uint16_t transferSize;
97 uint8_t triggerSourceSelect;
104 uint8_t transferUnitSelect;
112 uint8_t triggerTypeSelect;
124 #define DMA_TRIGGERSOURCE_0 (0x00)
125 #define DMA_TRIGGERSOURCE_1 (0x01)
126 #define DMA_TRIGGERSOURCE_2 (0x02)
127 #define DMA_TRIGGERSOURCE_3 (0x03)
128 #define DMA_TRIGGERSOURCE_4 (0x04)
129 #define DMA_TRIGGERSOURCE_5 (0x05)
130 #define DMA_TRIGGERSOURCE_6 (0x06)
131 #define DMA_TRIGGERSOURCE_7 (0x07)
132 #define DMA_TRIGGERSOURCE_8 (0x08)
133 #define DMA_TRIGGERSOURCE_9 (0x09)
134 #define DMA_TRIGGERSOURCE_10 (0x0A)
135 #define DMA_TRIGGERSOURCE_11 (0x0B)
136 #define DMA_TRIGGERSOURCE_12 (0x0C)
137 #define DMA_TRIGGERSOURCE_13 (0x0D)
138 #define DMA_TRIGGERSOURCE_14 (0x0E)
139 #define DMA_TRIGGERSOURCE_15 (0x0F)
140 #define DMA_TRIGGERSOURCE_16 (0x10)
141 #define DMA_TRIGGERSOURCE_17 (0x11)
142 #define DMA_TRIGGERSOURCE_18 (0x12)
143 #define DMA_TRIGGERSOURCE_19 (0x13)
144 #define DMA_TRIGGERSOURCE_20 (0x14)
145 #define DMA_TRIGGERSOURCE_21 (0x15)
146 #define DMA_TRIGGERSOURCE_22 (0x16)
147 #define DMA_TRIGGERSOURCE_23 (0x17)
148 #define DMA_TRIGGERSOURCE_24 (0x18)
149 #define DMA_TRIGGERSOURCE_25 (0x19)
150 #define DMA_TRIGGERSOURCE_26 (0x1A)
151 #define DMA_TRIGGERSOURCE_27 (0x1B)
152 #define DMA_TRIGGERSOURCE_28 (0x1C)
153 #define DMA_TRIGGERSOURCE_29 (0x1D)
154 #define DMA_TRIGGERSOURCE_30 (0x1E)
155 #define DMA_TRIGGERSOURCE_31 (0x1F)
164 #define DMA_TRANSFER_SINGLE (DMADT_0)
165 #define DMA_TRANSFER_BLOCK (DMADT_1)
166 #define DMA_TRANSFER_BURSTBLOCK (DMADT_2)
167 #define DMA_TRANSFER_REPEATED_SINGLE (DMADT_4)
168 #define DMA_TRANSFER_REPEATED_BLOCK (DMADT_5)
169 #define DMA_TRANSFER_REPEATED_BURSTBLOCK (DMADT_6)
182 #define DMA_CHANNEL_0 (0x00)
183 #define DMA_CHANNEL_1 (0x10)
184 #define DMA_CHANNEL_2 (0x20)
185 #define DMA_CHANNEL_3 (0x30)
186 #define DMA_CHANNEL_4 (0x40)
187 #define DMA_CHANNEL_5 (0x50)
188 #define DMA_CHANNEL_6 (0x60)
189 #define DMA_CHANNEL_7 (0x70)
198 #define DMA_TRIGGER_RISINGEDGE (!(DMALEVEL))
199 #define DMA_TRIGGER_HIGH (DMALEVEL)
208 #define DMA_SIZE_SRCWORD_DSTWORD (!(DMASRCBYTE + DMADSTBYTE))
209 #define DMA_SIZE_SRCBYTE_DSTWORD (DMASRCBYTE)
210 #define DMA_SIZE_SRCWORD_DSTBYTE (DMADSTBYTE)
211 #define DMA_SIZE_SRCBYTE_DSTBYTE (DMASRCBYTE + DMADSTBYTE)
219 #define DMA_DIRECTION_UNCHANGED (DMASRCINCR_0)
220 #define DMA_DIRECTION_DECREMENT (DMASRCINCR_2)
221 #define DMA_DIRECTION_INCREMENT (DMASRCINCR_3)
229 #define DMA_INT_INACTIVE (0x0)
230 #define DMA_INT_ACTIVE (DMAIFG)
238 #define DMA_NOTABORTED (0x0)
239 #define DMA_ABORTED (DMAABORT)
265 extern void DMA_init(DMA_initParam *
param);
294 extern void DMA_setTransferSize(uint8_t channelSelect,
295 uint16_t transferSize);
319 extern uint16_t DMA_getTransferSize(uint8_t channelSelect);
355 extern void DMA_setSrcAddress(uint8_t channelSelect,
357 uint16_t directionSelect);
392 extern void DMA_setDstAddress(uint8_t channelSelect,
394 uint16_t directionSelect);
417 extern void DMA_enableTransfers(uint8_t channelSelect);
441 extern void DMA_disableTransfers(uint8_t channelSelect);
468 extern void DMA_startTransfer(uint8_t channelSelect);
492 extern void DMA_enableInterrupt(uint8_t channelSelect);
516 extern void DMA_disableInterrupt(uint8_t channelSelect);
542 extern uint16_t DMA_getInterruptStatus(uint8_t channelSelect);
566 extern void DMA_clearInterrupt(uint8_t channelSelect);
594 extern uint16_t DMA_getNMIAbortStatus(uint8_t channelSelect);
619 extern void DMA_clearNMIAbort(uint8_t channelSelect);
633 extern void DMA_disableTransferDuringReadModifyWrite(
void);
647 extern void DMA_enableTransferDuringReadModifyWrite(
void);
662 extern void DMA_enableRoundRobinPriority(
void);
677 extern void DMA_disableRoundRobinPriority(
void);
691 extern void DMA_enableNMIAbort(
void);
704 extern void DMA_disableNMIAbort(
void);
MPU_initThreeSegmentsParam param