2020-2021 Sunseeker Telemetry and Lighting System
pmm.c
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1 //*****************************************************************************
2 //
3 // pmm.c - Driver for the pmm Module.
4 //
5 //*****************************************************************************
6 
7 //*****************************************************************************
8 //
11 //
12 //*****************************************************************************
13 
14 #include "inc/hw_memmap.h"
15 
16 #ifdef __MSP430_HAS_PMM__
17 #include "pmm.h"
18 
19 #include <assert.h>
20 
21 void PMM_enableSvsL (void)
22 {
23  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;
24  HWREG16(PMM_BASE + OFS_SVSMLCTL) |= SVSLE;
25  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;
26 }
27 
28 void PMM_disableSvsL (void)
29 {
30  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;
31  HWREG16(PMM_BASE + OFS_SVSMLCTL) &= ~SVSLE;
32  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;
33 }
34 
35 void PMM_enableSvmL (void)
36 {
37  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;
38  HWREG16(PMM_BASE + OFS_SVSMLCTL) |= SVMLE;
39  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;
40 }
41 
42 void PMM_disableSvmL (void)
43 {
44  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;
45  HWREG16(PMM_BASE + OFS_SVSMLCTL) &= ~SVMLE;
46  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;
47 }
48 
49 void PMM_enableSvsH (void)
50 {
51  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;
52  HWREG16(PMM_BASE + OFS_SVSMHCTL) |= SVSHE;
53  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;
54 }
55 
56 void PMM_disableSvsH (void)
57 {
58  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;
59  HWREG16(PMM_BASE + OFS_SVSMHCTL) &= ~SVSHE;
60  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;
61 }
62 
63 void PMM_enableSvmH (void)
64 {
65  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;
66  HWREG16(PMM_BASE + OFS_SVSMHCTL) |= SVMHE;
67  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;
68 }
69 
70 void PMM_disableSvmH (void)
71 {
72  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;
73  HWREG16(PMM_BASE + OFS_SVSMHCTL) &= ~SVMHE;
74  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;
75 }
76 
77 void PMM_enableSvsLSvmL (void)
78 {
79  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;
80  HWREG16(PMM_BASE + OFS_SVSMLCTL) |= (SVSLE + SVMLE);
81  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;
82 }
83 
84 void PMM_disableSvsLSvmL (void)
85 {
86  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;
87  HWREG16(PMM_BASE + OFS_SVSMLCTL) &= ~(SVSLE + SVMLE);
88  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;
89 }
90 
91 void PMM_enableSvsHSvmH (void)
92 {
93  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;
94  HWREG16(PMM_BASE + OFS_SVSMHCTL) |= (SVSHE + SVMHE);
95  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;
96 }
97 
98 void PMM_disableSvsHSvmH (void)
99 {
100  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;
101  HWREG16(PMM_BASE + OFS_SVSMHCTL) &= ~(SVSHE + SVMHE);
102  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;
103 }
104 
105 void PMM_enableSvsLReset (void)
106 {
107  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;
108  HWREG16(PMM_BASE + OFS_PMMRIE) |= SVSLPE;
109  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;
110 }
111 
112 void PMM_disableSvsLReset (void)
113 {
114  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;
115  HWREG16(PMM_BASE + OFS_PMMRIE) &= ~SVSLPE;
116  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;
117 }
118 
119 void PMM_enableSvmLInterrupt (void)
120 {
121  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;
122  HWREG16(PMM_BASE + OFS_PMMRIE) |= SVMLIE;
123  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;
124 }
125 
126 void PMM_disableSvmLInterrupt (void)
127 {
128  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;
129  HWREG16(PMM_BASE + OFS_PMMRIE) &= ~SVMLIE;
130  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;
131 }
132 
133 void PMM_enableSvsHReset (void)
134 {
135  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;
136  HWREG16(PMM_BASE + OFS_PMMRIE) |= SVSHPE;
137  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;
138 }
139 
140 void PMM_disableSvsHReset (void)
141 {
142  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;
143  HWREG16(PMM_BASE + OFS_PMMRIE) &= ~SVSHPE;
144  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;
145 }
146 
147 void PMM_enableSvmHInterrupt (void)
148 {
149  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;
150  HWREG16(PMM_BASE + OFS_PMMRIE) |= SVMHIE;
151  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;
152 }
153 
154 void PMM_disableSvmHInterrupt (void)
155 {
156  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;
157  HWREG16(PMM_BASE + OFS_PMMRIE) &= ~SVMHIE;
158  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;
159 }
160 
161 void PMM_clearPMMIFGS (void)
162 {
163  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;
164  HWREG16(PMM_BASE + OFS_PMMIFG) = 0;
165  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;
166 }
167 
168 void PMM_enableSvsLInLPMFastWake (void)
169 {
170  //These settings use SVSH/LACE = 0
171  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;
172  HWREG16(PMM_BASE + OFS_SVSMLCTL) |= (SVSLFP + SVSLMD);
173  HWREG16(PMM_BASE + OFS_SVSMLCTL) &= ~SVSMLACE;
174  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;
175 }
176 
177 void PMM_enableSvsLInLPMSlowWake (void)
178 {
179  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;
180  HWREG16(PMM_BASE + OFS_SVSMLCTL) |= SVSLMD;
181  HWREG16(PMM_BASE + OFS_SVSMLCTL) &= ~(SVSLFP + SVSMLACE);
182  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;
183 }
184 
185 void PMM_disableSvsLInLPMFastWake (void)
186 {
187  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;
188  HWREG16(PMM_BASE + OFS_SVSMLCTL) |= SVSLFP;
189  HWREG16(PMM_BASE + OFS_SVSMLCTL) &= ~(SVSLMD + SVSMLACE);
190  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;
191 }
192 
193 void PMM_disableSvsLInLPMSlowWake (void)
194 {
195  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;
196  HWREG16(PMM_BASE + OFS_SVSMLCTL) &= ~(SVSLFP + SVSMLACE + SVSLMD);
197  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;
198 }
199 
200 void PMM_enableSvsHInLPMNormPerf (void)
201 {
202  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;
203  HWREG16(PMM_BASE + OFS_SVSMHCTL) |= SVSHMD;
204  HWREG16(PMM_BASE + OFS_SVSMHCTL) &= ~(SVSMHACE + SVSHFP);
205  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;
206 }
207 
208 void PMM_enableSvsHInLPMFullPerf (void)
209 {
210  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;
211  HWREG16(PMM_BASE + OFS_SVSMHCTL) |= (SVSHMD + SVSHFP);
212  HWREG16(PMM_BASE + OFS_SVSMHCTL) &= ~SVSMHACE;
213  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;
214 }
215 
216 void PMM_disableSvsHInLPMNormPerf (void)
217 {
218  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;
219  HWREG16(PMM_BASE + OFS_SVSMHCTL) &= ~(SVSMHACE + SVSHFP + SVSHMD);
220  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;
221 }
222 
223 void PMM_disableSvsHInLPMFullPerf (void)
224 {
225  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;
226  HWREG16(PMM_BASE + OFS_SVSMHCTL) |= SVSHFP;
227  HWREG16(PMM_BASE + OFS_SVSMHCTL) &= ~(SVSMHACE + SVSHMD);
228  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;
229 }
230 
231 void PMM_optimizeSvsLInLPMFastWake (void)
232 {
233  //These setting use SVSH/LACE = 1
234  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;
235  HWREG16(PMM_BASE + OFS_SVSMLCTL) |= (SVSLFP + SVSLMD + SVSMLACE);
236  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;
237 }
238 
239 void PMM_optimizeSvsHInLPMFullPerf (void)
240 {
241  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;
242  HWREG16(PMM_BASE + OFS_SVSMHCTL) |= (SVSHMD + SVSHFP + SVSMHACE);
243  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;
244 }
245 
246 uint16_t PMM_setVCoreUp ( uint8_t level){
247  uint32_t PMMRIE_backup, SVSMHCTL_backup, SVSMLCTL_backup;
248 
249  //The code flow for increasing the Vcore has been altered to work around
250  //the erratum FLASH37.
251  //Please refer to the Errata sheet to know if a specific device is affected
252  //DO NOT ALTER THIS FUNCTION
253 
254  //Open PMM registers for write access
255  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;
256 
257  //Disable dedicated Interrupts
258  //Backup all registers
259  PMMRIE_backup = HWREG16(PMM_BASE + OFS_PMMRIE);
260  HWREG16(PMM_BASE + OFS_PMMRIE) &= ~(SVMHVLRPE | SVSHPE | SVMLVLRPE |
261  SVSLPE | SVMHVLRIE | SVMHIE |
262  SVSMHDLYIE | SVMLVLRIE | SVMLIE |
263  SVSMLDLYIE
264  );
265  SVSMHCTL_backup = HWREG16(PMM_BASE + OFS_SVSMHCTL);
266  SVSMLCTL_backup = HWREG16(PMM_BASE + OFS_SVSMLCTL);
267 
268  //Clear flags
269  HWREG16(PMM_BASE + OFS_PMMIFG) = 0;
270 
271  //Set SVM highside to new level and check if a VCore increase is possible
272  HWREG16(PMM_BASE + OFS_SVSMHCTL) = SVMHE | SVSHE | (SVSMHRRL0 * level);
273 
274  //Wait until SVM highside is settled
275  while ((HWREG16(PMM_BASE + OFS_PMMIFG) & SVSMHDLYIFG) == 0) ;
276 
277  //Clear flag
278  HWREG16(PMM_BASE + OFS_PMMIFG) &= ~SVSMHDLYIFG;
279 
280  //Check if a VCore increase is possible
281  if ((HWREG16(PMM_BASE + OFS_PMMIFG) & SVMHIFG) == SVMHIFG){
282  //-> Vcc is too low for a Vcore increase
283  //recover the previous settings
284  HWREG16(PMM_BASE + OFS_PMMIFG) &= ~SVSMHDLYIFG;
285  HWREG16(PMM_BASE + OFS_SVSMHCTL) = SVSMHCTL_backup;
286 
287  //Wait until SVM highside is settled
288  while ((HWREG16(PMM_BASE + OFS_PMMIFG) & SVSMHDLYIFG) == 0) ;
289 
290  //Clear all Flags
291  HWREG16(PMM_BASE +
292  OFS_PMMIFG) &= ~(SVMHVLRIFG | SVMHIFG | SVSMHDLYIFG |
293  SVMLVLRIFG | SVMLIFG |
294  SVSMLDLYIFG
295  );
296 
297  //Restore PMM interrupt enable register
298  HWREG16(PMM_BASE + OFS_PMMRIE) = PMMRIE_backup;
299  //Lock PMM registers for write access
300  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;
301  //return: voltage not set
302  return ( STATUS_FAIL) ;
303  }
304 
305  //Set also SVS highside to new level
306  //Vcc is high enough for a Vcore increase
307  HWREG16(PMM_BASE + OFS_SVSMHCTL) |= (SVSHRVL0 * level);
308 
309  //Wait until SVM highside is settled
310  while ((HWREG16(PMM_BASE + OFS_PMMIFG) & SVSMHDLYIFG) == 0) ;
311 
312  //Clear flag
313  HWREG16(PMM_BASE + OFS_PMMIFG) &= ~SVSMHDLYIFG;
314 
315  //Set VCore to new level
316  HWREG8(PMM_BASE + OFS_PMMCTL0_L) = PMMCOREV0 * level;
317 
318  //Set SVM, SVS low side to new level
319  HWREG16(PMM_BASE + OFS_SVSMLCTL) = SVMLE | (SVSMLRRL0 * level) |
320  SVSLE | (SVSLRVL0 * level);
321 
322  //Wait until SVM, SVS low side is settled
323  while ((HWREG16(PMM_BASE + OFS_PMMIFG) & SVSMLDLYIFG) == 0) ;
324 
325  //Clear flag
326  HWREG16(PMM_BASE + OFS_PMMIFG) &= ~SVSMLDLYIFG;
327  //SVS, SVM core and high side are now set to protect for the new core level
328 
329  //Restore Low side settings
330  //Clear all other bits _except_ level settings
331  HWREG16(PMM_BASE + OFS_SVSMLCTL) &= (SVSLRVL0 + SVSLRVL1 + SVSMLRRL0 +
332  SVSMLRRL1 + SVSMLRRL2
333  );
334 
335  //Clear level settings in the backup register,keep all other bits
336  SVSMLCTL_backup &=
337  ~(SVSLRVL0 + SVSLRVL1 + SVSMLRRL0 + SVSMLRRL1 + SVSMLRRL2);
338 
339  //Restore low-side SVS monitor settings
340  HWREG16(PMM_BASE + OFS_SVSMLCTL) |= SVSMLCTL_backup;
341 
342  //Restore High side settings
343  //Clear all other bits except level settings
344  HWREG16(PMM_BASE + OFS_SVSMHCTL) &= (SVSHRVL0 + SVSHRVL1 +
345  SVSMHRRL0 + SVSMHRRL1 +
346  SVSMHRRL2
347  );
348 
349  //Clear level settings in the backup register,keep all other bits
350  SVSMHCTL_backup &=
351  ~(SVSHRVL0 + SVSHRVL1 + SVSMHRRL0 + SVSMHRRL1 + SVSMHRRL2);
352 
353  //Restore backup
354  HWREG16(PMM_BASE + OFS_SVSMHCTL) |= SVSMHCTL_backup;
355 
356  //Wait until high side, low side settled
357  while (((HWREG16(PMM_BASE + OFS_PMMIFG) & SVSMLDLYIFG) == 0) ||
358  ((HWREG16(PMM_BASE + OFS_PMMIFG) & SVSMHDLYIFG) == 0)) ;
359 
360  //Clear all Flags
361  HWREG16(PMM_BASE + OFS_PMMIFG) &= ~(SVMHVLRIFG | SVMHIFG | SVSMHDLYIFG |
362  SVMLVLRIFG | SVMLIFG | SVSMLDLYIFG
363  );
364 
365  //Restore PMM interrupt enable register
366  HWREG16(PMM_BASE + OFS_PMMRIE) = PMMRIE_backup;
367 
368  //Lock PMM registers for write access
369  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;
370 
371  return ( STATUS_SUCCESS) ;
372 }
373 
374 uint16_t PMM_setVCoreDown ( uint8_t level){
375  uint32_t PMMRIE_backup, SVSMHCTL_backup, SVSMLCTL_backup;
376 
377  //The code flow for decreasing the Vcore has been altered to work around
378  //the erratum FLASH37.
379  //Please refer to the Errata sheet to know if a specific device is affected
380  //DO NOT ALTER THIS FUNCTION
381 
382  //Open PMM registers for write access
383  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0xA5;
384 
385  //Disable dedicated Interrupts
386  //Backup all registers
387  PMMRIE_backup = HWREG16(PMM_BASE + OFS_PMMRIE);
388  HWREG16(PMM_BASE + OFS_PMMRIE) &= ~(SVMHVLRPE | SVSHPE | SVMLVLRPE |
389  SVSLPE | SVMHVLRIE | SVMHIE |
390  SVSMHDLYIE | SVMLVLRIE | SVMLIE |
391  SVSMLDLYIE
392  );
393  SVSMHCTL_backup = HWREG16(PMM_BASE + OFS_SVSMHCTL);
394  SVSMLCTL_backup = HWREG16(PMM_BASE + OFS_SVSMLCTL);
395 
396  //Clear flags
397  HWREG16(PMM_BASE + OFS_PMMIFG) &= ~(SVMHIFG | SVSMHDLYIFG |
398  SVMLIFG | SVSMLDLYIFG
399  );
400 
401  //Set SVM, SVS high & low side to new settings in normal mode
402  HWREG16(PMM_BASE + OFS_SVSMHCTL) = SVMHE | (SVSMHRRL0 * level) |
403  SVSHE | (SVSHRVL0 * level);
404  HWREG16(PMM_BASE + OFS_SVSMLCTL) = SVMLE | (SVSMLRRL0 * level) |
405  SVSLE | (SVSLRVL0 * level);
406 
407  //Wait until SVM high side and SVM low side is settled
408  while ((HWREG16(PMM_BASE + OFS_PMMIFG) & SVSMHDLYIFG) == 0 ||
409  (HWREG16(PMM_BASE + OFS_PMMIFG) & SVSMLDLYIFG) == 0) ;
410 
411  //Clear flags
412  HWREG16(PMM_BASE + OFS_PMMIFG) &= ~(SVSMHDLYIFG + SVSMLDLYIFG);
413  //SVS, SVM core and high side are now set to protect for the new core level
414 
415  //Set VCore to new level
416  HWREG8(PMM_BASE + OFS_PMMCTL0_L) = PMMCOREV0 * level;
417 
418  //Restore Low side settings
419  //Clear all other bits _except_ level settings
420  HWREG16(PMM_BASE + OFS_SVSMLCTL) &= (SVSLRVL0 + SVSLRVL1 + SVSMLRRL0 +
421  SVSMLRRL1 + SVSMLRRL2
422  );
423 
424  //Clear level settings in the backup register,keep all other bits
425  SVSMLCTL_backup &=
426  ~(SVSLRVL0 + SVSLRVL1 + SVSMLRRL0 + SVSMLRRL1 + SVSMLRRL2);
427 
428  //Restore low-side SVS monitor settings
429  HWREG16(PMM_BASE + OFS_SVSMLCTL) |= SVSMLCTL_backup;
430 
431  //Restore High side settings
432  //Clear all other bits except level settings
433  HWREG16(PMM_BASE + OFS_SVSMHCTL) &= (SVSHRVL0 + SVSHRVL1 + SVSMHRRL0 +
434  SVSMHRRL1 + SVSMHRRL2
435  );
436 
437  //Clear level settings in the backup register, keep all other bits
438  SVSMHCTL_backup &=
439  ~(SVSHRVL0 + SVSHRVL1 + SVSMHRRL0 + SVSMHRRL1 + SVSMHRRL2);
440 
441  //Restore backup
442  HWREG16(PMM_BASE + OFS_SVSMHCTL) |= SVSMHCTL_backup;
443 
444  //Wait until high side, low side settled
445  while (((HWREG16(PMM_BASE + OFS_PMMIFG) & SVSMLDLYIFG) == 0) ||
446  ((HWREG16(PMM_BASE + OFS_PMMIFG) & SVSMHDLYIFG) == 0)) ;
447 
448  //Clear all Flags
449  HWREG16(PMM_BASE + OFS_PMMIFG) &= ~(SVMHVLRIFG | SVMHIFG | SVSMHDLYIFG |
450  SVMLVLRIFG | SVMLIFG | SVSMLDLYIFG
451  );
452 
453  //Restore PMM interrupt enable register
454  HWREG16(PMM_BASE + OFS_PMMRIE) = PMMRIE_backup;
455  //Lock PMM registers for write access
456  HWREG8(PMM_BASE + OFS_PMMCTL0_H) = 0x00;
457  //Return: OK
458  return ( STATUS_SUCCESS) ;
459 }
460 
461 bool PMM_setVCore ( uint8_t level){
462  uint8_t actlevel;
463  bool status = STATUS_SUCCESS;
464  uint16_t interruptState;
465 
466  //Set Mask for Max. level
467  level &= PMMCOREV_3;
468 
469  //Get actual VCore
470  actlevel = (HWREG16(PMM_BASE + OFS_PMMCTL0) & PMMCOREV_3);
471 
472  //Disable interrupts because certain peripherals will not
473  //work during VCORE change
474  interruptState = __get_interrupt_state();
475  __disable_interrupt();
476  __no_operation();
477 
478  //step by step increase or decrease
479  while ((level != actlevel) && (status == STATUS_SUCCESS))
480  {
481  if (level > actlevel){
482  status = PMM_setVCoreUp(++actlevel);
483  } else {
484  status = PMM_setVCoreDown(--actlevel);
485  }
486  }
487 
488  //Re-enable interrupt state to whatever it was before
489  if(interruptState & GIE)
490  {
491  __enable_interrupt();
492  }
493 
494  return ( status) ;
495 }
496 
497 uint16_t PMM_getInterruptStatus (uint16_t mask)
498 {
499  return ( (HWREG16(PMM_BASE + OFS_PMMIFG)) & mask );
500 }
501 
502 #endif
503 //*****************************************************************************
504 //
507 //
508 //*****************************************************************************
__no_operation
__no_operation()
hw_memmap.h
HWREG8
#define HWREG8(x)
Definition: hw_memmap.h:41
HWREG16
#define HWREG16(x)
Definition: hw_memmap.h:39
STATUS_FAIL
#define STATUS_FAIL
Definition: hw_memmap.h:23
STATUS_SUCCESS
#define STATUS_SUCCESS
Definition: hw_memmap.h:22
status
uint16_t status
Definition: pmm_ex1_vcore3.c:60