16 #ifdef __MSP430_HAS_TxD7__
22 void Timer_D_startCounter ( uint16_t baseAddress,
26 HWREG16(baseAddress + OFS_TDxCTL0) |= timerMode;
29 void Timer_D_initContinuousMode(uint16_t baseAddress,
30 Timer_D_initContinuousModeParam *
param)
33 OFS_TDxCTL0) &= ~(TIMER_D_CLOCKSOURCE_INVERTED_EXTERNAL_TDCLK +
36 TIMER_D_TDIE_INTERRUPT_ENABLE +
39 HWREG16(baseAddress + OFS_TDxCTL1) &= ~(TDCLKM0 + TDCLKM1 + TDIDEX_7);
41 HWREG16(baseAddress + OFS_TDxCTL0) |=
param->clockSource;
42 HWREG16(baseAddress + OFS_TDxCTL1) |= (
param->clockingMode +
43 ((
param->clockSourceDivider&0x7)<<8));
45 HWREG16(baseAddress + OFS_TDxCTL0) |= (
param->timerClear +
46 param->timerInterruptEnable_TDIE +
47 ((
param->clockSourceDivider>>3)<<6));
50 void Timer_D_initUpMode(uint16_t baseAddress, Timer_D_initUpModeParam *
param)
52 HWREG16(baseAddress + OFS_TDxCTL0) &=
53 ~(TIMER_D_CLOCKSOURCE_INVERTED_EXTERNAL_TDCLK +
56 TIMER_D_TDIE_INTERRUPT_ENABLE +
59 HWREG16(baseAddress + OFS_TDxCTL1) &= ~(TDCLKM0 + TDCLKM1 + TDIDEX_7);
61 HWREG16(baseAddress + OFS_TDxCTL0) |=
param->clockSource;
62 HWREG16(baseAddress + OFS_TDxCTL1) |= (
param->clockingMode +
63 ((
param->clockSourceDivider&0x7)<<8));
65 HWREG16(baseAddress + OFS_TDxCTL0) |= (TIMER_D_STOP_MODE +
67 param->timerInterruptEnable_TDIE +
68 ((
param->clockSourceDivider>>3)<<6));
70 if (TIMER_D_CCIE_CCR0_INTERRUPT_ENABLE ==
71 param->captureCompareInterruptEnable_CCR0_CCIE){
72 HWREG16(baseAddress + OFS_TDxCCTL0) |= TIMER_D_CCIE_CCR0_INTERRUPT_ENABLE;
74 HWREG16(baseAddress + OFS_TDxCCTL0) &= ~TIMER_D_CCIE_CCR0_INTERRUPT_ENABLE;
80 void Timer_D_initUpDownMode(uint16_t baseAddress,
81 Timer_D_initUpDownModeParam *
param)
83 HWREG16(baseAddress + OFS_TDxCTL0) &=
84 ~(TIMER_D_CLOCKSOURCE_INVERTED_EXTERNAL_TDCLK +
87 TIMER_D_TDIE_INTERRUPT_ENABLE +
90 HWREG16(baseAddress + OFS_TDxCTL1) &= ~(TDCLKM0 + TDCLKM1 + TDIDEX_7);
92 HWREG16(baseAddress + OFS_TDxCTL0) |=
param->clockSource;
93 HWREG16(baseAddress + OFS_TDxCTL1) |= (
param->clockingMode +
94 ((
param->clockSourceDivider&0x7)<<8));
96 HWREG16(baseAddress + OFS_TDxCTL0) |= (TIMER_D_STOP_MODE +
98 param->timerInterruptEnable_TDIE +
99 ((
param->clockSourceDivider>>3)<<6));
101 if (TIMER_D_CCIE_CCR0_INTERRUPT_ENABLE ==
102 param->captureCompareInterruptEnable_CCR0_CCIE){
103 HWREG16(baseAddress + OFS_TDxCCTL0) |= TIMER_D_CCIE_CCR0_INTERRUPT_ENABLE;
105 HWREG16(baseAddress + OFS_TDxCCTL0) &= ~TIMER_D_CCIE_CCR0_INTERRUPT_ENABLE;
108 HWREG16(baseAddress + OFS_TDxCCR0) =
param->timerPeriod;
111 void Timer_D_initCaptureMode(uint16_t baseAddress,
112 Timer_D_initCaptureModeParam *
param)
117 HWREG8(baseAddress + OFS_TDxCTL2) |=
118 (
param->channelCaptureMode << ((
param->captureRegister - TIMER_D_CAPTURECOMPARE_REGISTER_0)/6));
121 ~(TIMER_D_CAPTUREMODE_RISING_AND_FALLING_EDGE +
122 TIMER_D_CAPTURE_INPUTSELECT_Vcc +
123 TIMER_D_CAPTURE_SYNCHRONOUS +
125 TIMER_D_TDIE_INTERRUPT_ENABLE +
130 param->captureInputSelect +
131 param->synchronizeCaptureSource +
132 param->captureInterruptEnable +
133 param->captureOutputMode
137 void Timer_D_initCompareMode(uint16_t baseAddress,
138 Timer_D_initCompareModeParam *
param)
143 ~(TIMER_D_CAPTURECOMPARE_INTERRUPT_ENABLE +
144 TIMER_D_OUTPUTMODE_RESET_SET
147 HWREG16(baseAddress +
param->compareRegister) |= (
param->compareInterruptEnable +
148 param->compareOutputMode
154 void Timer_D_enableTimerInterrupt (uint16_t baseAddress)
156 HWREG8(baseAddress + OFS_TDxCTL0) &= ~TDIFG;
157 HWREG8(baseAddress + OFS_TDxCTL0) |= TDIE;
160 void Timer_D_enableHighResInterrupt (uint16_t baseAddress,
163 HWREG16(baseAddress + OFS_TDxHINT) &= ~(mask >> 8);
164 HWREG16(baseAddress + OFS_TDxHINT) |= mask;
167 void Timer_D_disableTimerInterrupt (uint16_t baseAddress)
169 HWREG8(baseAddress + OFS_TDxCTL0) &= ~TDIE;
172 void Timer_D_disableHighResInterrupt (uint16_t baseAddress,
175 HWREG16(baseAddress + OFS_TDxHINT) &= ~mask;
178 uint32_t Timer_D_getTimerInterruptStatus (uint16_t baseAddress)
180 return (
HWREG8(baseAddress + OFS_TDxCTL0) & TDIFG);
183 void Timer_D_enableCaptureCompareInterrupt (uint16_t baseAddress,
184 uint16_t captureCompareRegister
187 HWREG8(baseAddress + captureCompareRegister) &= ~CCIFG;
188 HWREG16(baseAddress + captureCompareRegister) |= CCIE;
191 void Timer_D_disableCaptureCompareInterrupt (uint16_t baseAddress,
192 uint16_t captureCompareRegister
195 HWREG16(baseAddress + captureCompareRegister) &= ~CCIE;
198 uint32_t Timer_D_getCaptureCompareInterruptStatus (uint16_t baseAddress,
199 uint16_t captureCompareRegister,
203 return (
HWREG16(baseAddress + captureCompareRegister) & mask );
206 uint16_t Timer_D_getHighResInterruptStatus (uint16_t baseAddress,
210 return ( (
HWREG16(baseAddress + OFS_TDxHINT) & mask) << 8 );
213 void Timer_D_clear (uint16_t baseAddress)
215 HWREG16(baseAddress + OFS_TDxCTL0) |= TDCLR;
218 void Timer_D_clearHighResInterrupt (uint16_t baseAddress,
222 HWREG16(baseAddress + OFS_TDxHINT) &= ~mask;
225 uint8_t Timer_D_getSynchronizedCaptureCompareInput
226 (uint16_t baseAddress,
227 uint16_t captureCompareRegister,
228 uint16_t
synchronized
231 if (
HWREG16(baseAddress + captureCompareRegister) &
synchronized){
232 return ( TIMER_D_CAPTURECOMPARE_INPUT_HIGH) ;
234 return ( TIMER_D_CAPTURECOMPARE_INPUT_LOW) ;
238 uint8_t Timer_D_getOutputForOutputModeOutBitValue
239 (uint16_t baseAddress,
240 uint16_t captureCompareRegister
243 if (
HWREG16(baseAddress + captureCompareRegister) & OUT){
244 return ( TIMER_D_OUTPUTMODE_OUTBITVALUE_HIGH) ;
246 return ( TIMER_D_OUTPUTMODE_OUTBITVALUE_LOW) ;
250 uint16_t Timer_D_getCaptureCompareCount
251 (uint16_t baseAddress,
252 uint16_t captureCompareRegister
255 return (
HWREG16(baseAddress + captureCompareRegister + 2));
258 uint16_t Timer_D_getCaptureCompareLatchCount
259 (uint16_t baseAddress,
260 uint16_t captureCompareRegister
263 return (
HWREG16(baseAddress + captureCompareRegister + 4));
266 uint8_t Timer_D_getCaptureCompareInputSignal
267 (uint16_t baseAddress,
268 uint16_t captureCompareRegister
271 return ((
HWREG8(baseAddress + captureCompareRegister) & CCI));
274 void Timer_D_setOutputForOutputModeOutBitValue
275 (uint16_t baseAddress,
276 uint16_t captureCompareRegister,
277 uint8_t outputModeOutBitValue
280 HWREG16(baseAddress + captureCompareRegister) &= ~OUT;
281 HWREG16(baseAddress + captureCompareRegister) |= outputModeOutBitValue;
284 void Timer_D_outputPWM(uint16_t baseAddress, Timer_D_outputPWMParam *
param)
286 HWREG16(baseAddress + OFS_TDxCTL1) &= ~(TDCLKM0 + TDCLKM1 + TDIDEX_7);
288 HWREG16(baseAddress + OFS_TDxCTL0) &=
289 ~(TIMER_D_CLOCKSOURCE_INVERTED_EXTERNAL_TDCLK +
290 TIMER_D_UPDOWN_MODE + TIMER_D_DO_CLEAR +
291 TIMER_D_TDIE_INTERRUPT_ENABLE +
295 HWREG16(baseAddress + OFS_TDxCTL0) |=
param->clockSource;
296 HWREG16(baseAddress + OFS_TDxCTL1) |= (
param->clockingMode +
297 ((
param->clockSourceDivider&0x7)<<8));
299 HWREG16(baseAddress + OFS_TDxCTL0) |= (TIMER_D_UP_MODE +
301 ((
param->clockSourceDivider>>3)<<6));
303 HWREG16(baseAddress + OFS_TDxCCR0) =
param->timerPeriod;
305 HWREG16(baseAddress + OFS_TDxCCTL0) &=
306 ~(TIMER_D_CAPTURECOMPARE_INTERRUPT_ENABLE +
307 TIMER_D_OUTPUTMODE_RESET_SET
314 void Timer_D_stop ( uint16_t baseAddress )
316 HWREG16(baseAddress + OFS_TDxCTL0) &= ~MC_3;
319 void Timer_D_setCompareValue ( uint16_t baseAddress,
320 uint16_t compareRegister,
321 uint16_t compareValue
324 HWREG16(baseAddress + compareRegister + 0x02) = compareValue;
327 void Timer_D_clearTimerInterrupt (uint16_t baseAddress)
329 HWREG16(baseAddress + OFS_TDxCTL0) &= ~TDIFG;
332 void Timer_D_clearCaptureCompareInterrupt (uint16_t baseAddress,
333 uint16_t captureCompareRegister
336 HWREG16(baseAddress + captureCompareRegister) &= ~CCIFG;
339 uint8_t Timer_D_initHighResGeneratorInFreeRunningMode
340 (uint16_t baseAddress,
341 uint8_t desiredHighResFrequency
344 struct s_TLV_Timer_D_Cal_Data * pTD0CAL;
345 uint8_t TD0CAL_bytes;
348 TLV_getInfo(TLV_TAG_TIMER_D_CAL,
351 (uint16_t **)&pTD0CAL
354 if(0x00 == TD0CAL_bytes)
360 HWREG16(baseAddress + OFS_TDxHCTL1) = TDHCLKTRIM6;
361 HWREG16(baseAddress + OFS_TDxCTL1) = 0x00;
362 HWREG16(baseAddress + OFS_TDxHCTL0) = 0x00;
364 switch( desiredHighResFrequency )
366 case TIMER_D_HIGHRES_64MHZ:
367 HWREG16(baseAddress + OFS_TDxHCTL1) = pTD0CAL->TDH0CTL1_64;
370 case TIMER_D_HIGHRES_128MHZ:
371 HWREG16(baseAddress + OFS_TDxHCTL1) = pTD0CAL->TDH0CTL1_128;
374 case TIMER_D_HIGHRES_200MHZ:
375 HWREG16(baseAddress + OFS_TDxHCTL1) = pTD0CAL->TDH0CTL1_200;
378 case TIMER_D_HIGHRES_256MHZ:
379 HWREG16(baseAddress + OFS_TDxHCTL1) = pTD0CAL->TDH0CTL1_256;
384 HWREG16(baseAddress + OFS_TDxCTL1) |= TDCLKM_1;
387 if(TIMER_D_HIGHRES_256MHZ == desiredHighResFrequency)
388 HWREG16(baseAddress + OFS_TDxHCTL0) |= TDHM_1;
390 HWREG16(baseAddress + OFS_TDxHCTL0) |= TDHEN;
396 void Timer_D_initHighResGeneratorInRegulatedMode(uint16_t baseAddress,
397 Timer_D_initHighResGeneratorInRegulatedModeParam *
param)
399 HWREG16(baseAddress + OFS_TDxCTL0) &= ~(TDSSEL_3 + TDHD_3 + TDCLR + ID__8);
400 HWREG16(baseAddress + OFS_TDxCTL1) &= ~(TDCLKM0 + TDCLKM1 + TDIDEX_7);
402 HWREG16(baseAddress + OFS_TDxCTL0) |= (
param->clockSource +
403 ((
param->clockSourceDivider>>3)<<6));
404 HWREG16(baseAddress + OFS_TDxCTL1) |= (
param->clockingMode +
405 ((
param->clockSourceDivider&0x7)<<8));
409 HWREG16(baseAddress + OFS_TDxCTL1) |= TDCLKM_1;
411 HWREG16(baseAddress + OFS_TDxHCTL0) = TDHREGEN + TDHEN ;
412 HWREG16(baseAddress + OFS_TDxHCTL0) |=
param->highResClockMultiplyFactor +
413 param->highResClockDivider;
416 void Timer_D_combineTDCCRToOutputPWM(uint16_t baseAddress,
417 Timer_D_combineTDCCRToOutputPWMParam *
param)
419 HWREG16(baseAddress + OFS_TDxCCTL2) &= ~OUTMOD_7;
420 HWREG16(baseAddress + OFS_TDxCCTL2) |=
param->compareOutputMode;
422 HWREG16(baseAddress + OFS_TDxCCR0) =
param->timerPeriod;
424 HWREG16(baseAddress + OFS_TDxCCR1 + (0x05 *
425 (
param->combineCCRRegistersCombination - TIMER_D_COMBINE_CCR1_CCR2))) =
param->dutyCycle1;
426 HWREG16(baseAddress + OFS_TDxCCR2 + (0x05 *
427 (
param->combineCCRRegistersCombination - TIMER_D_COMBINE_CCR1_CCR2))) =
param->dutyCycle2;
429 HWREG16(baseAddress + OFS_TDxCTL0) &= ~ID__8;
430 HWREG16(baseAddress + OFS_TDxCTL1) &= ~(TDCLKM0 + TDCLKM1 + TDIDEX_7);
432 HWREG16(baseAddress + OFS_TDxCTL0) |= (
param->clockSource +
433 ((
param->clockSourceDivider>>3)<<6));
434 HWREG16(baseAddress + OFS_TDxCTL1) |= (
param->clockingMode +
435 ((
param->clockSourceDivider&0x7)<<8));
436 HWREG16(baseAddress + OFS_TDxCTL1) |=
437 (TD2CMB << (
param->combineCCRRegistersCombination - TIMER_D_COMBINE_CCR1_CCR2));
440 void Timer_D_selectLatchingGroup(uint16_t baseAddress,
444 HWREG16(baseAddress + OFS_TDxCTL0) &= ~TDCLGRP_3;
445 HWREG16(baseAddress + OFS_TDxCTL0) |= groupLatch;
448 void Timer_D_selectCounterLength (uint16_t baseAddress,
449 uint16_t counterLength
453 HWREG16(baseAddress + OFS_TDxCTL0) &= ~CNTL_3;
454 HWREG16(baseAddress + OFS_TDxCTL0) |= counterLength;
457 void Timer_D_initCompareLatchLoadEvent(uint16_t baseAddress,
458 uint16_t compareRegister,
459 uint16_t compareLatchLoadEvent
463 HWREG16(baseAddress + compareRegister) &= ~CLLD_3;
464 HWREG16(baseAddress + compareRegister) |= compareLatchLoadEvent;
467 void Timer_D_disableHighResFastWakeup (uint16_t baseAddress)
469 HWREG16(baseAddress + OFS_TDxHCTL0) &= ~TDHFW;
472 void Timer_D_enableHighResFastWakeup (uint16_t baseAddress)
474 HWREG16(baseAddress + OFS_TDxHCTL0) |= TDHFW;
477 void Timer_D_disableHighResClockEnhancedAccuracy (uint16_t baseAddress)
479 HWREG16(baseAddress + OFS_TDxHCTL0) &= ~TDHEAEN;
482 void Timer_D_enableHighResClockEnhancedAccuracy (uint16_t baseAddress)
484 HWREG16(baseAddress + OFS_TDxHCTL0) |= TDHEAEN;
487 void Timer_D_disableHighResGeneratorForceON (uint16_t baseAddress)
489 HWREG16(baseAddress + OFS_TDxHCTL0) &= ~TDHRON;
492 void Timer_D_enableHighResGeneratorForceON (uint16_t baseAddress)
494 HWREG16(baseAddress + OFS_TDxHCTL0) |= TDHRON;
497 void Timer_D_selectHighResCoarseClockRange (uint16_t baseAddress,
498 uint16_t highResCoarseClockRange
501 HWREG16(baseAddress + OFS_TDxHCTL1) &= ~TDHCLKCR;
502 HWREG16(baseAddress + OFS_TDxHCTL1) |= highResCoarseClockRange;
505 void Timer_D_selectHighResClockRange (uint16_t baseAddress,
506 uint16_t highResClockRange
509 HWREG16(baseAddress + OFS_TDxHCTL1) &= ~TDHCLKCR;
510 HWREG16(baseAddress + OFS_TDxHCTL1) |= highResClockRange;
513 uint16_t Timer_D_getCounterValue (uint16_t baseAddress)
515 uint16_t voteOne, voteTwo, res;
517 voteTwo =
HWREG16(baseAddress + OFS_TDxR);
522 voteTwo =
HWREG16(baseAddress + OFS_TDxR);
524 if(voteTwo > voteOne) {
525 res = voteTwo - voteOne;
526 }
else if(voteOne > voteTwo) {
527 res = voteOne - voteTwo;
532 }
while ( res > TIMER_D_THRESHOLD);
537 void Timer_D_setOutputMode(uint16_t baseAddress,
538 uint16_t compareRegister,
539 uint16_t compareOutputMode)
541 uint16_t
temp =
HWREG16(baseAddress + compareRegister);
542 HWREG16(baseAddress + compareRegister) =
temp & ~(OUTMOD_7) | compareOutputMode;
MPU_initThreeSegmentsParam param