2020-2021 Sunseeker Telemetry and Lighting System
timer_d.c
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1 //*****************************************************************************
2 //
3 // timer_d.c - Driver for the timer_d Module.
4 //
5 //*****************************************************************************
6 
7 //*****************************************************************************
8 //
11 //
12 //*****************************************************************************
13 
14 #include "inc/hw_memmap.h"
15 
16 #ifdef __MSP430_HAS_TxD7__
17 #include "timer_d.h"
18 
19 #include <assert.h>
20 
21 #include "tlv.h"
22 void Timer_D_startCounter ( uint16_t baseAddress,
23  uint16_t timerMode
24  )
25 {
26  HWREG16(baseAddress + OFS_TDxCTL0) |= timerMode;
27 }
28 
29 void Timer_D_initContinuousMode(uint16_t baseAddress,
30  Timer_D_initContinuousModeParam *param)
31 {
32  HWREG16(baseAddress +
33  OFS_TDxCTL0) &= ~(TIMER_D_CLOCKSOURCE_INVERTED_EXTERNAL_TDCLK +
34  TIMER_D_UPDOWN_MODE +
35  TIMER_D_DO_CLEAR +
36  TIMER_D_TDIE_INTERRUPT_ENABLE +
37  ID__8
38  );
39  HWREG16(baseAddress + OFS_TDxCTL1) &= ~(TDCLKM0 + TDCLKM1 + TDIDEX_7);
40 
41  HWREG16(baseAddress + OFS_TDxCTL0) |= param->clockSource;
42  HWREG16(baseAddress + OFS_TDxCTL1) |= (param->clockingMode +
43  ((param->clockSourceDivider&0x7)<<8));
44 
45  HWREG16(baseAddress + OFS_TDxCTL0) |= (param->timerClear +
46  param->timerInterruptEnable_TDIE +
47  ((param->clockSourceDivider>>3)<<6));
48 }
49 
50 void Timer_D_initUpMode(uint16_t baseAddress, Timer_D_initUpModeParam *param)
51 {
52  HWREG16(baseAddress + OFS_TDxCTL0) &=
53  ~(TIMER_D_CLOCKSOURCE_INVERTED_EXTERNAL_TDCLK +
54  TIMER_D_UPDOWN_MODE +
55  TIMER_D_DO_CLEAR +
56  TIMER_D_TDIE_INTERRUPT_ENABLE +
57  ID__8
58  );
59  HWREG16(baseAddress + OFS_TDxCTL1) &= ~(TDCLKM0 + TDCLKM1 + TDIDEX_7);
60 
61  HWREG16(baseAddress + OFS_TDxCTL0) |= param->clockSource;
62  HWREG16(baseAddress + OFS_TDxCTL1) |= (param->clockingMode +
63  ((param->clockSourceDivider&0x7)<<8));
64 
65  HWREG16(baseAddress + OFS_TDxCTL0) |= (TIMER_D_STOP_MODE +
66  param->timerClear +
67  param->timerInterruptEnable_TDIE +
68  ((param->clockSourceDivider>>3)<<6));
69 
70  if (TIMER_D_CCIE_CCR0_INTERRUPT_ENABLE ==
71  param->captureCompareInterruptEnable_CCR0_CCIE){
72  HWREG16(baseAddress + OFS_TDxCCTL0) |= TIMER_D_CCIE_CCR0_INTERRUPT_ENABLE;
73  } else {
74  HWREG16(baseAddress + OFS_TDxCCTL0) &= ~TIMER_D_CCIE_CCR0_INTERRUPT_ENABLE;
75  }
76 
77  HWREG16(baseAddress + OFS_TDxCCR0) = param->timerPeriod;
78 }
79 
80 void Timer_D_initUpDownMode(uint16_t baseAddress,
81  Timer_D_initUpDownModeParam *param)
82 {
83  HWREG16(baseAddress + OFS_TDxCTL0) &=
84  ~(TIMER_D_CLOCKSOURCE_INVERTED_EXTERNAL_TDCLK +
85  TIMER_D_UPDOWN_MODE +
86  TIMER_D_DO_CLEAR +
87  TIMER_D_TDIE_INTERRUPT_ENABLE +
88  ID__8
89  );
90  HWREG16(baseAddress + OFS_TDxCTL1) &= ~(TDCLKM0 + TDCLKM1 + TDIDEX_7);
91 
92  HWREG16(baseAddress + OFS_TDxCTL0) |= param->clockSource;
93  HWREG16(baseAddress + OFS_TDxCTL1) |= (param->clockingMode +
94  ((param->clockSourceDivider&0x7)<<8));
95 
96  HWREG16(baseAddress + OFS_TDxCTL0) |= (TIMER_D_STOP_MODE +
97  param->timerClear +
98  param->timerInterruptEnable_TDIE +
99  ((param->clockSourceDivider>>3)<<6));
100 
101  if (TIMER_D_CCIE_CCR0_INTERRUPT_ENABLE ==
102  param->captureCompareInterruptEnable_CCR0_CCIE){
103  HWREG16(baseAddress + OFS_TDxCCTL0) |= TIMER_D_CCIE_CCR0_INTERRUPT_ENABLE;
104  } else {
105  HWREG16(baseAddress + OFS_TDxCCTL0) &= ~TIMER_D_CCIE_CCR0_INTERRUPT_ENABLE;
106  }
107 
108  HWREG16(baseAddress + OFS_TDxCCR0) = param->timerPeriod;
109 }
110 
111 void Timer_D_initCaptureMode(uint16_t baseAddress,
112  Timer_D_initCaptureModeParam *param)
113 {
114 
115  HWREG16(baseAddress + param->captureRegister ) |= CAP;
116 
117  HWREG8(baseAddress + OFS_TDxCTL2) |=
118  (param->channelCaptureMode << ((param->captureRegister - TIMER_D_CAPTURECOMPARE_REGISTER_0)/6));
119 
120  HWREG16(baseAddress + param->captureRegister) &=
121  ~(TIMER_D_CAPTUREMODE_RISING_AND_FALLING_EDGE +
122  TIMER_D_CAPTURE_INPUTSELECT_Vcc +
123  TIMER_D_CAPTURE_SYNCHRONOUS +
124  TIMER_D_DO_CLEAR +
125  TIMER_D_TDIE_INTERRUPT_ENABLE +
126  CM_3
127  );
128 
129  HWREG16(baseAddress + param->captureRegister) |= (param->captureMode +
130  param->captureInputSelect +
131  param->synchronizeCaptureSource +
132  param->captureInterruptEnable +
133  param->captureOutputMode
134  );
135 }
136 
137 void Timer_D_initCompareMode(uint16_t baseAddress,
138  Timer_D_initCompareModeParam *param)
139 {
140  HWREG16(baseAddress + param->compareRegister ) &= ~CAP;
141 
142  HWREG16(baseAddress + param->compareRegister) &=
143  ~(TIMER_D_CAPTURECOMPARE_INTERRUPT_ENABLE +
144  TIMER_D_OUTPUTMODE_RESET_SET
145  );
146 
147  HWREG16(baseAddress + param->compareRegister) |= (param->compareInterruptEnable +
148  param->compareOutputMode
149  );
150 
151  HWREG16(baseAddress + param->compareRegister + 2) = param->compareValue;
152 }
153 
154 void Timer_D_enableTimerInterrupt (uint16_t baseAddress)
155 {
156  HWREG8(baseAddress + OFS_TDxCTL0) &= ~TDIFG;
157  HWREG8(baseAddress + OFS_TDxCTL0) |= TDIE;
158 }
159 
160 void Timer_D_enableHighResInterrupt (uint16_t baseAddress,
161  uint16_t mask)
162 {
163  HWREG16(baseAddress + OFS_TDxHINT) &= ~(mask >> 8);
164  HWREG16(baseAddress + OFS_TDxHINT) |= mask;
165 }
166 
167 void Timer_D_disableTimerInterrupt (uint16_t baseAddress)
168 {
169  HWREG8(baseAddress + OFS_TDxCTL0) &= ~TDIE;
170 }
171 
172 void Timer_D_disableHighResInterrupt (uint16_t baseAddress,
173  uint16_t mask)
174 {
175  HWREG16(baseAddress + OFS_TDxHINT) &= ~mask;
176 }
177 
178 uint32_t Timer_D_getTimerInterruptStatus (uint16_t baseAddress)
179 {
180  return (HWREG8(baseAddress + OFS_TDxCTL0) & TDIFG);
181 }
182 
183 void Timer_D_enableCaptureCompareInterrupt (uint16_t baseAddress,
184  uint16_t captureCompareRegister
185  )
186 {
187  HWREG8(baseAddress + captureCompareRegister) &= ~CCIFG;
188  HWREG16(baseAddress + captureCompareRegister) |= CCIE;
189 }
190 
191 void Timer_D_disableCaptureCompareInterrupt (uint16_t baseAddress,
192  uint16_t captureCompareRegister
193  )
194 {
195  HWREG16(baseAddress + captureCompareRegister) &= ~CCIE;
196 }
197 
198 uint32_t Timer_D_getCaptureCompareInterruptStatus (uint16_t baseAddress,
199  uint16_t captureCompareRegister,
200  uint16_t mask
201  )
202 {
203  return ( HWREG16(baseAddress + captureCompareRegister) & mask );
204 }
205 
206 uint16_t Timer_D_getHighResInterruptStatus (uint16_t baseAddress,
207  uint16_t mask)
208 {
209  mask = (mask >> 8);
210  return ( (HWREG16(baseAddress + OFS_TDxHINT) & mask) << 8 );
211 }
212 
213 void Timer_D_clear (uint16_t baseAddress)
214 {
215  HWREG16(baseAddress + OFS_TDxCTL0) |= TDCLR;
216 }
217 
218 void Timer_D_clearHighResInterrupt (uint16_t baseAddress,
219  uint16_t mask)
220 {
221  mask = (mask >> 8);
222  HWREG16(baseAddress + OFS_TDxHINT) &= ~mask;
223 }
224 
225 uint8_t Timer_D_getSynchronizedCaptureCompareInput
226  (uint16_t baseAddress,
227  uint16_t captureCompareRegister,
228  uint16_t synchronized
229  )
230 {
231  if (HWREG16(baseAddress + captureCompareRegister) & synchronized){
232  return ( TIMER_D_CAPTURECOMPARE_INPUT_HIGH) ;
233  } else {
234  return ( TIMER_D_CAPTURECOMPARE_INPUT_LOW) ;
235  }
236 }
237 
238 uint8_t Timer_D_getOutputForOutputModeOutBitValue
239  (uint16_t baseAddress,
240  uint16_t captureCompareRegister
241  )
242 {
243  if (HWREG16(baseAddress + captureCompareRegister) & OUT){
244  return ( TIMER_D_OUTPUTMODE_OUTBITVALUE_HIGH) ;
245  } else {
246  return ( TIMER_D_OUTPUTMODE_OUTBITVALUE_LOW) ;
247  }
248 }
249 
250 uint16_t Timer_D_getCaptureCompareCount
251  (uint16_t baseAddress,
252  uint16_t captureCompareRegister
253  )
254 {
255  return (HWREG16(baseAddress + captureCompareRegister + 2));
256 }
257 
258 uint16_t Timer_D_getCaptureCompareLatchCount
259  (uint16_t baseAddress,
260  uint16_t captureCompareRegister
261  )
262 {
263  return (HWREG16(baseAddress + captureCompareRegister + 4));
264 }
265 
266 uint8_t Timer_D_getCaptureCompareInputSignal
267  (uint16_t baseAddress,
268  uint16_t captureCompareRegister
269  )
270 {
271  return ((HWREG8(baseAddress + captureCompareRegister) & CCI));
272 }
273 
274 void Timer_D_setOutputForOutputModeOutBitValue
275  (uint16_t baseAddress,
276  uint16_t captureCompareRegister,
277  uint8_t outputModeOutBitValue
278  )
279 {
280  HWREG16(baseAddress + captureCompareRegister) &= ~OUT;
281  HWREG16(baseAddress + captureCompareRegister) |= outputModeOutBitValue;
282 }
283 
284 void Timer_D_outputPWM(uint16_t baseAddress, Timer_D_outputPWMParam *param)
285 {
286  HWREG16(baseAddress + OFS_TDxCTL1) &= ~(TDCLKM0 + TDCLKM1 + TDIDEX_7);
287 
288  HWREG16(baseAddress + OFS_TDxCTL0) &=
289  ~(TIMER_D_CLOCKSOURCE_INVERTED_EXTERNAL_TDCLK +
290  TIMER_D_UPDOWN_MODE + TIMER_D_DO_CLEAR +
291  TIMER_D_TDIE_INTERRUPT_ENABLE +
292  ID__8
293  );
294 
295  HWREG16(baseAddress + OFS_TDxCTL0) |= param->clockSource;
296  HWREG16(baseAddress + OFS_TDxCTL1) |= (param->clockingMode +
297  ((param->clockSourceDivider&0x7)<<8));
298 
299  HWREG16(baseAddress + OFS_TDxCTL0) |= (TIMER_D_UP_MODE +
300  TIMER_D_DO_CLEAR +
301  ((param->clockSourceDivider>>3)<<6));
302 
303  HWREG16(baseAddress + OFS_TDxCCR0) = param->timerPeriod;
304 
305  HWREG16(baseAddress + OFS_TDxCCTL0) &=
306  ~(TIMER_D_CAPTURECOMPARE_INTERRUPT_ENABLE +
307  TIMER_D_OUTPUTMODE_RESET_SET
308  );
309  HWREG16(baseAddress + param->compareRegister) |= param->compareOutputMode;
310 
311  HWREG16(baseAddress + param->compareRegister + 2) = param->dutyCycle;
312 }
313 
314 void Timer_D_stop ( uint16_t baseAddress )
315 {
316  HWREG16(baseAddress + OFS_TDxCTL0) &= ~MC_3;
317 }
318 
319 void Timer_D_setCompareValue ( uint16_t baseAddress,
320  uint16_t compareRegister,
321  uint16_t compareValue
322  )
323 {
324  HWREG16(baseAddress + compareRegister + 0x02) = compareValue;
325 }
326 
327 void Timer_D_clearTimerInterrupt (uint16_t baseAddress)
328 {
329  HWREG16(baseAddress + OFS_TDxCTL0) &= ~TDIFG;
330 }
331 
332 void Timer_D_clearCaptureCompareInterrupt (uint16_t baseAddress,
333  uint16_t captureCompareRegister
334  )
335 {
336  HWREG16(baseAddress + captureCompareRegister) &= ~CCIFG;
337 }
338 
339 uint8_t Timer_D_initHighResGeneratorInFreeRunningMode
340  (uint16_t baseAddress,
341  uint8_t desiredHighResFrequency
342  )
343 {
344  struct s_TLV_Timer_D_Cal_Data * pTD0CAL;
345  uint8_t TD0CAL_bytes;
346 
347  // Read the TimerD TLV Data
348  TLV_getInfo(TLV_TAG_TIMER_D_CAL,
349  0,
350  &TD0CAL_bytes,
351  (uint16_t **)&pTD0CAL
352  );
353 
354  if(0x00 == TD0CAL_bytes)
355  {
356  // No TimerD free running cal data found
357  return STATUS_FAIL;
358  }
359 
360  HWREG16(baseAddress + OFS_TDxHCTL1) = TDHCLKTRIM6;
361  HWREG16(baseAddress + OFS_TDxCTL1) = 0x00;
362  HWREG16(baseAddress + OFS_TDxHCTL0) = 0x00;
363 
364  switch( desiredHighResFrequency )
365  {
366  case TIMER_D_HIGHRES_64MHZ:
367  HWREG16(baseAddress + OFS_TDxHCTL1) = pTD0CAL->TDH0CTL1_64;
368  break;
369 
370  case TIMER_D_HIGHRES_128MHZ:
371  HWREG16(baseAddress + OFS_TDxHCTL1) = pTD0CAL->TDH0CTL1_128;
372  break;
373 
374  case TIMER_D_HIGHRES_200MHZ:
375  HWREG16(baseAddress + OFS_TDxHCTL1) = pTD0CAL->TDH0CTL1_200;
376  break;
377 
378  case TIMER_D_HIGHRES_256MHZ:
379  HWREG16(baseAddress + OFS_TDxHCTL1) = pTD0CAL->TDH0CTL1_256;
380  break;
381  }
382 
383  // Select Hi-res local clock
384  HWREG16(baseAddress + OFS_TDxCTL1) |= TDCLKM_1;
385 
386  // CALEN=0 => free running mode; enable Hi-res mode
387  if(TIMER_D_HIGHRES_256MHZ == desiredHighResFrequency)
388  HWREG16(baseAddress + OFS_TDxHCTL0) |= TDHM_1;
389 
390  HWREG16(baseAddress + OFS_TDxHCTL0) |= TDHEN;
391 
392  return STATUS_SUCCESS;
393 
394 }
395 
396 void Timer_D_initHighResGeneratorInRegulatedMode(uint16_t baseAddress,
397  Timer_D_initHighResGeneratorInRegulatedModeParam *param)
398 {
399  HWREG16(baseAddress + OFS_TDxCTL0) &= ~(TDSSEL_3 + TDHD_3 + TDCLR + ID__8);
400  HWREG16(baseAddress + OFS_TDxCTL1) &= ~(TDCLKM0 + TDCLKM1 + TDIDEX_7);
401 
402  HWREG16(baseAddress + OFS_TDxCTL0) |= (param->clockSource +
403  ((param->clockSourceDivider>>3)<<6));
404  HWREG16(baseAddress + OFS_TDxCTL1) |= (param->clockingMode +
405  ((param->clockSourceDivider&0x7)<<8));
406 
407  // Select Hi-res local clock
408  // Calibration and Hi-res mode enable
409  HWREG16(baseAddress + OFS_TDxCTL1) |= TDCLKM_1;
410  // Select Hi-res local clock
411  HWREG16(baseAddress + OFS_TDxHCTL0) = TDHREGEN + TDHEN ;
412  HWREG16(baseAddress + OFS_TDxHCTL0) |= param->highResClockMultiplyFactor +
413  param->highResClockDivider;
414 }
415 
416 void Timer_D_combineTDCCRToOutputPWM(uint16_t baseAddress,
417  Timer_D_combineTDCCRToOutputPWMParam *param)
418 {
419  HWREG16(baseAddress + OFS_TDxCCTL2) &= ~OUTMOD_7;
420  HWREG16(baseAddress + OFS_TDxCCTL2) |= param->compareOutputMode;
421 
422  HWREG16(baseAddress + OFS_TDxCCR0) = param->timerPeriod;
423 
424  HWREG16(baseAddress + OFS_TDxCCR1 + (0x05 *
425  (param->combineCCRRegistersCombination - TIMER_D_COMBINE_CCR1_CCR2))) = param->dutyCycle1;
426  HWREG16(baseAddress + OFS_TDxCCR2 + (0x05 *
427  (param->combineCCRRegistersCombination - TIMER_D_COMBINE_CCR1_CCR2))) = param->dutyCycle2;
428 
429  HWREG16(baseAddress + OFS_TDxCTL0) &= ~ID__8;
430  HWREG16(baseAddress + OFS_TDxCTL1) &= ~(TDCLKM0 + TDCLKM1 + TDIDEX_7);
431 
432  HWREG16(baseAddress + OFS_TDxCTL0) |= (param->clockSource +
433  ((param->clockSourceDivider>>3)<<6));
434  HWREG16(baseAddress + OFS_TDxCTL1) |= (param->clockingMode +
435  ((param->clockSourceDivider&0x7)<<8));
436  HWREG16(baseAddress + OFS_TDxCTL1) |=
437  (TD2CMB << (param->combineCCRRegistersCombination - TIMER_D_COMBINE_CCR1_CCR2));
438 }
439 
440 void Timer_D_selectLatchingGroup(uint16_t baseAddress,
441  uint16_t groupLatch)
442 {
443 
444  HWREG16(baseAddress + OFS_TDxCTL0) &= ~TDCLGRP_3;
445  HWREG16(baseAddress + OFS_TDxCTL0) |= groupLatch;
446 }
447 
448 void Timer_D_selectCounterLength (uint16_t baseAddress,
449  uint16_t counterLength
450  )
451 {
452 
453  HWREG16(baseAddress + OFS_TDxCTL0) &= ~CNTL_3;
454  HWREG16(baseAddress + OFS_TDxCTL0) |= counterLength;
455 }
456 
457 void Timer_D_initCompareLatchLoadEvent(uint16_t baseAddress,
458  uint16_t compareRegister,
459  uint16_t compareLatchLoadEvent
460  )
461 {
462 
463  HWREG16(baseAddress + compareRegister) &= ~CLLD_3;
464  HWREG16(baseAddress + compareRegister) |= compareLatchLoadEvent;
465 }
466 
467 void Timer_D_disableHighResFastWakeup (uint16_t baseAddress)
468 {
469  HWREG16(baseAddress + OFS_TDxHCTL0) &= ~TDHFW;
470 }
471 
472 void Timer_D_enableHighResFastWakeup (uint16_t baseAddress)
473 {
474  HWREG16(baseAddress + OFS_TDxHCTL0) |= TDHFW;
475 }
476 
477 void Timer_D_disableHighResClockEnhancedAccuracy (uint16_t baseAddress)
478 {
479  HWREG16(baseAddress + OFS_TDxHCTL0) &= ~TDHEAEN;
480 }
481 
482 void Timer_D_enableHighResClockEnhancedAccuracy (uint16_t baseAddress)
483 {
484  HWREG16(baseAddress + OFS_TDxHCTL0) |= TDHEAEN;
485 }
486 
487 void Timer_D_disableHighResGeneratorForceON (uint16_t baseAddress)
488 {
489  HWREG16(baseAddress + OFS_TDxHCTL0) &= ~TDHRON;
490 }
491 
492 void Timer_D_enableHighResGeneratorForceON (uint16_t baseAddress)
493 {
494  HWREG16(baseAddress + OFS_TDxHCTL0) |= TDHRON;
495 }
496 
497 void Timer_D_selectHighResCoarseClockRange (uint16_t baseAddress,
498  uint16_t highResCoarseClockRange
499  )
500 {
501  HWREG16(baseAddress + OFS_TDxHCTL1) &= ~TDHCLKCR;
502  HWREG16(baseAddress + OFS_TDxHCTL1) |= highResCoarseClockRange;
503 }
504 
505 void Timer_D_selectHighResClockRange (uint16_t baseAddress,
506  uint16_t highResClockRange
507  )
508 {
509  HWREG16(baseAddress + OFS_TDxHCTL1) &= ~TDHCLKCR;
510  HWREG16(baseAddress + OFS_TDxHCTL1) |= highResClockRange;
511 }
512 
513 uint16_t Timer_D_getCounterValue (uint16_t baseAddress)
514 {
515  uint16_t voteOne, voteTwo, res;
516 
517  voteTwo = HWREG16(baseAddress + OFS_TDxR);
518 
519  do
520  {
521  voteOne = voteTwo;
522  voteTwo = HWREG16(baseAddress + OFS_TDxR);
523 
524  if(voteTwo > voteOne) {
525  res = voteTwo - voteOne;
526  } else if(voteOne > voteTwo) {
527  res = voteOne - voteTwo;
528  } else{
529  res = 0;
530  }
531 
532  } while ( res > TIMER_D_THRESHOLD);
533 
534  return voteTwo;
535 }
536 
537 void Timer_D_setOutputMode(uint16_t baseAddress,
538  uint16_t compareRegister,
539  uint16_t compareOutputMode)
540 {
541  uint16_t temp = HWREG16(baseAddress + compareRegister);
542  HWREG16(baseAddress + compareRegister) = temp & ~(OUTMOD_7) | compareOutputMode;
543 }
544 
545 #endif
546 //*****************************************************************************
547 //
550 //
551 //*****************************************************************************
MPU_initThreeSegmentsParam param
long temp
#define HWREG8(x)
Definition: hw_memmap.h:41
#define HWREG16(x)
Definition: hw_memmap.h:39
#define STATUS_FAIL
Definition: hw_memmap.h:23
#define STATUS_SUCCESS
Definition: hw_memmap.h:22