From 40043591a8f81b55687cb14829448170111bfb06 Mon Sep 17 00:00:00 2001 From: William Miceli Date: Sat, 26 Jun 2021 17:19:22 -0400 Subject: [PATCH] Moved sections of code to go more in order of the datasheet's listing of registers --- Telem_Debug/Debug_RS-232/usci.c | 14 +++++++------- Telem_Debug/Debug_USB/usci.c | 14 +++++++------- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/Telem_Debug/Debug_RS-232/usci.c b/Telem_Debug/Debug_RS-232/usci.c index e4151eb..478efeb 100644 --- a/Telem_Debug/Debug_RS-232/usci.c +++ b/Telem_Debug/Debug_RS-232/usci.c @@ -32,13 +32,6 @@ void usci_A1_init(void){ void usci_A2_init(void){ UCA2CTL1 |= UCSWRST; // Software Reset Enable - Set high, disabling the USCI module; Changes to USCI configuration registers can only be made when the UCSWRST bit = 1 - UCA2CTL1 &= ~0b11000000; // Reset both UCSSELx bits so the USCI Clock Source Select bits are more predictable - UCA2CTL1 |= UCSSEL__SMCLK; // USCI Clock Source Select - SMCLK - UCA2CTL1 &= ~UCRXEIE; // Receive Erroneous-Character Interrupt Enable - Disabled - UCA2CTL1 &= ~UCBRKIE; // Receive Break Character Interrupt Enable - Disabled - UCA2CTL1 &= ~UCDORM; // Dormant - Disabled; USCI module will not be put into sleep mode - UCA2CTL1 &= ~UCTXADDR; // Transmit Address - Next frame transmitted is data - UCA2CTL1 &= ~UCTXBRK; // Transmit Break - Do not transmit a Break/Synch as the next frame UCA2CTL0 &= ~UCPEN; // Parity Enable - Disabled UCA2CTL0 &= ~UCMSB; // MSB First Select - Set low; Least Significant Bit will be sent first UCA2CTL0 &= ~UC7BIT; // Character Length - 8-bit data selected @@ -46,6 +39,13 @@ void usci_A2_init(void){ UCA2CTL0 &= ~UCMODE1; // USCI Mode [2 Bits Required] - UART mode selected UCA2CTL0 &= ~UCMODE0; // USCI Mode [2 Bits Required] - UART mode selected UCA2CTL0 &= ~UCSYNC; // Synchronous Mode Enable - Asynchronous mode selected + UCA2CTL1 &= ~0b11000000; // Reset both UCSSELx bits so the USCI Clock Source Select bits are more predictable + UCA2CTL1 |= UCSSEL__SMCLK; // USCI Clock Source Select - SMCLK + UCA2CTL1 &= ~UCRXEIE; // Receive Erroneous-Character Interrupt Enable - Disabled + UCA2CTL1 &= ~UCBRKIE; // Receive Break Character Interrupt Enable - Disabled + UCA2CTL1 &= ~UCDORM; // Dormant - Disabled; USCI module will not be put into sleep mode + UCA2CTL1 &= ~UCTXADDR; // Transmit Address - Next frame transmitted is data + UCA2CTL1 &= ~UCTXBRK; // Transmit Break - Do not transmit a Break/Synch as the next frame UCA2BRW = 10; // Clock Prescalar UCA2MCTL &= ~0b11111111; // Reset entire register UCA2MCTL |= 0x0 << 4; // First Modulation Stage Select diff --git a/Telem_Debug/Debug_USB/usci.c b/Telem_Debug/Debug_USB/usci.c index 691707b..fb79ce4 100644 --- a/Telem_Debug/Debug_USB/usci.c +++ b/Telem_Debug/Debug_USB/usci.c @@ -32,13 +32,6 @@ void usci_A1_init(void){ void usci_A2_init(void){ UCA2CTL1 |= UCSWRST; // Software Reset Enable - Set high, disabling the USCI module; Changes to USCI configuration registers can only be made when the UCSWRST bit = 1 - UCA2CTL1 &= ~0b11000000; // Reset both UCSSELx bits so the USCI Clock Source Select bits are more predictable - UCA2CTL1 |= UCSSEL__SMCLK; // USCI Clock Source Select - SMCLK - UCA2CTL1 &= ~UCRXEIE; // Receive Erroneous-Character Interrupt Enable - Disabled - UCA2CTL1 &= ~UCBRKIE; // Receive Break Character Interrupt Enable - Disabled - UCA2CTL1 &= ~UCDORM; // Dormant - Disabled; USCI module will not be put into sleep mode - UCA2CTL1 &= ~UCTXADDR; // Transmit Address - Next frame transmitted is data - UCA2CTL1 &= ~UCTXBRK; // Transmit Break - Do not transmit a Break/Synch as the next frame UCA2CTL0 &= ~UCPEN; // Parity Enable - Disabled UCA2CTL0 &= ~UCMSB; // MSB First Select - Set low; Least Significant Bit will be sent first UCA2CTL0 &= ~UC7BIT; // Character Length - 8-bit data selected @@ -46,6 +39,13 @@ void usci_A2_init(void){ UCA2CTL0 &= ~UCMODE1; // USCI Mode [2 Bits Required] - UART mode selected UCA2CTL0 &= ~UCMODE0; // USCI Mode [2 Bits Required] - UART mode selected UCA2CTL0 &= ~UCSYNC; // Synchronous Mode Enable - Asynchronous mode selected + UCA2CTL1 &= ~0b11000000; // Reset both UCSSELx bits so the USCI Clock Source Select bits are more predictable + UCA2CTL1 |= UCSSEL__SMCLK; // USCI Clock Source Select - SMCLK + UCA2CTL1 &= ~UCRXEIE; // Receive Erroneous-Character Interrupt Enable - Disabled + UCA2CTL1 &= ~UCBRKIE; // Receive Break Character Interrupt Enable - Disabled + UCA2CTL1 &= ~UCDORM; // Dormant - Disabled; USCI module will not be put into sleep mode + UCA2CTL1 &= ~UCTXADDR; // Transmit Address - Next frame transmitted is data + UCA2CTL1 &= ~UCTXBRK; // Transmit Break - Do not transmit a Break/Synch as the next frame UCA2BRW = 10; // Clock Prescalar UCA2MCTL &= ~0b11111111; // Reset entire register UCA2MCTL |= 0x0 << 4; // First Modulation Stage Select