diff --git a/Telem_Debug/Debug1/Debug/Debug1.map b/Telem_Debug/Debug1/Debug/Debug1.map index 24f378e..1e07d49 100644 --- a/Telem_Debug/Debug1/Debug/Debug1.map +++ b/Telem_Debug/Debug1/Debug/Debug1.map @@ -1,10 +1,10 @@ ****************************************************************************** - MSP430 Linker PC v20.2.2 + MSP430 Linker PC v15.12.3 ****************************************************************************** ->> Linked Sat May 15 19:48:00 2021 +>> Linked Fri May 21 16:08:04 2021 OUTPUT FILE NAME: -ENTRY POINT SYMBOL: "_c_int00_noargs" address: 00005c2c +ENTRY POINT SYMBOL: "_c_int00_noargs_noexit" address: 00005c2c MEMORY CONFIGURATION @@ -84,7 +84,7 @@ MEMORY CONFIGURATION INT61 0000fffa 00000002 00000002 00000000 RWIX INT62 0000fffc 00000002 00000002 00000000 RWIX RESET 0000fffe 00000002 00000002 00000000 RWIX - FLASH2 00010000 00035c00 00000280 00035980 RWIX + FLASH2 00010000 00035c00 00000324 000358dc RWIX SECTION ALLOCATION MAP @@ -96,17 +96,17 @@ section page origin length input sections 00001c00 0000000c main.obj (.data) .stack 0 00005b60 000000a0 UNINITIALIZED - 00005b60 00000004 rts430x_lc_rd_eabi.lib : boot.c.obj (.stack) + 00005b60 00000004 rts430x_lc_rd_eabi.lib : boot.obj (.stack) 00005b64 0000009c --HOLE-- .text:_isr -* 0 00005c00 00000050 +* 0 00005c00 0000004e 00005c00 0000002c main.obj (.text:_isr:timer_b0) - 00005c2c 0000001c rts430x_lc_rd_eabi.lib : boot.c.obj (.text:_isr:_c_int00_noargs) - 00005c48 00000008 : isr_trap.asm.obj (.text:_isr:__TI_ISR_TRAP) + 00005c2c 0000001a rts430x_lc_rd_eabi.lib : boot_special.obj (.text:_isr:_c_int00_noargs_noexit) + 00005c46 00000008 : isr_trap.obj (.text:_isr:__TI_ISR_TRAP) -.cinit 0 00005c50 0000001c - 00005c50 0000000b (.cinit..data.load) [load image, compression = lzss] +.cinit 0 00005c4e 0000001e + 00005c4e 0000000d (.cinit..data.load) [load image, compression = rle] 00005c5b 00000001 --HOLE-- [fill = 0] 00005c5c 00000008 (__TI_handler_table) 00005c64 00000008 (__TI_cinit_table) @@ -117,1612 +117,1666 @@ section page origin length input sections * 0 00005c00 00000000 UNINITIALIZED RTC 0 0000ffd2 00000002 - 0000ffd2 00000002 rts430x_lc_rd_eabi.lib : int41.asm.obj (.int41) + 0000ffd2 00000002 rts430x_lc_rd_eabi.lib : int41.obj (.int41) PORT2 0 0000ffd4 00000002 - 0000ffd4 00000002 rts430x_lc_rd_eabi.lib : int42.asm.obj (.int42) + 0000ffd4 00000002 rts430x_lc_rd_eabi.lib : int42.obj (.int42) USCI_B3 0 0000ffd6 00000002 - 0000ffd6 00000002 rts430x_lc_rd_eabi.lib : int43.asm.obj (.int43) + 0000ffd6 00000002 rts430x_lc_rd_eabi.lib : int43.obj (.int43) USCI_A3 0 0000ffd8 00000002 - 0000ffd8 00000002 rts430x_lc_rd_eabi.lib : int44.asm.obj (.int44) + 0000ffd8 00000002 rts430x_lc_rd_eabi.lib : int44.obj (.int44) USCI_B1 0 0000ffda 00000002 - 0000ffda 00000002 rts430x_lc_rd_eabi.lib : int45.asm.obj (.int45) + 0000ffda 00000002 rts430x_lc_rd_eabi.lib : int45.obj (.int45) USCI_A1 0 0000ffdc 00000002 - 0000ffdc 00000002 rts430x_lc_rd_eabi.lib : int46.asm.obj (.int46) + 0000ffdc 00000002 rts430x_lc_rd_eabi.lib : int46.obj (.int46) PORT1 0 0000ffde 00000002 - 0000ffde 00000002 rts430x_lc_rd_eabi.lib : int47.asm.obj (.int47) + 0000ffde 00000002 rts430x_lc_rd_eabi.lib : int47.obj (.int47) TIMER1_A1 * 0 0000ffe0 00000002 - 0000ffe0 00000002 rts430x_lc_rd_eabi.lib : int48.asm.obj (.int48) + 0000ffe0 00000002 rts430x_lc_rd_eabi.lib : int48.obj (.int48) TIMER1_A0 * 0 0000ffe2 00000002 - 0000ffe2 00000002 rts430x_lc_rd_eabi.lib : int49.asm.obj (.int49) + 0000ffe2 00000002 rts430x_lc_rd_eabi.lib : int49.obj (.int49) DMA 0 0000ffe4 00000002 - 0000ffe4 00000002 rts430x_lc_rd_eabi.lib : int50.asm.obj (.int50) + 0000ffe4 00000002 rts430x_lc_rd_eabi.lib : int50.obj (.int50) USCI_B2 0 0000ffe6 00000002 - 0000ffe6 00000002 rts430x_lc_rd_eabi.lib : int51.asm.obj (.int51) + 0000ffe6 00000002 rts430x_lc_rd_eabi.lib : int51.obj (.int51) USCI_A2 0 0000ffe8 00000002 - 0000ffe8 00000002 rts430x_lc_rd_eabi.lib : int52.asm.obj (.int52) + 0000ffe8 00000002 rts430x_lc_rd_eabi.lib : int52.obj (.int52) TIMER0_A1 * 0 0000ffea 00000002 - 0000ffea 00000002 rts430x_lc_rd_eabi.lib : int53.asm.obj (.int53) + 0000ffea 00000002 rts430x_lc_rd_eabi.lib : int53.obj (.int53) TIMER0_A0 * 0 0000ffec 00000002 - 0000ffec 00000002 rts430x_lc_rd_eabi.lib : int54.asm.obj (.int54) + 0000ffec 00000002 rts430x_lc_rd_eabi.lib : int54.obj (.int54) ADC12 0 0000ffee 00000002 - 0000ffee 00000002 rts430x_lc_rd_eabi.lib : int55.asm.obj (.int55) + 0000ffee 00000002 rts430x_lc_rd_eabi.lib : int55.obj (.int55) USCI_B0 0 0000fff0 00000002 - 0000fff0 00000002 rts430x_lc_rd_eabi.lib : int56.asm.obj (.int56) + 0000fff0 00000002 rts430x_lc_rd_eabi.lib : int56.obj (.int56) USCI_A0 0 0000fff2 00000002 - 0000fff2 00000002 rts430x_lc_rd_eabi.lib : int57.asm.obj (.int57) + 0000fff2 00000002 rts430x_lc_rd_eabi.lib : int57.obj (.int57) WDT 0 0000fff4 00000002 - 0000fff4 00000002 rts430x_lc_rd_eabi.lib : int58.asm.obj (.int58) + 0000fff4 00000002 rts430x_lc_rd_eabi.lib : int58.obj (.int58) TIMER0_B1 * 0 0000fff6 00000002 - 0000fff6 00000002 rts430x_lc_rd_eabi.lib : int59.asm.obj (.int59) + 0000fff6 00000002 rts430x_lc_rd_eabi.lib : int59.obj (.int59) TIMER0_B0 * 0 0000fff8 00000002 0000fff8 00000002 main.obj (.int60) UNMI 0 0000fffa 00000002 - 0000fffa 00000002 rts430x_lc_rd_eabi.lib : int61.asm.obj (.int61) + 0000fffa 00000002 rts430x_lc_rd_eabi.lib : int61.obj (.int61) SYSNMI 0 0000fffc 00000002 - 0000fffc 00000002 rts430x_lc_rd_eabi.lib : int62.asm.obj (.int62) + 0000fffc 00000002 rts430x_lc_rd_eabi.lib : int62.obj (.int62) .reset 0 0000fffe 00000002 - 0000fffe 00000002 rts430x_lc_rd_eabi.lib : boot.c.obj (.reset) + 0000fffe 00000002 rts430x_lc_rd_eabi.lib : boot.obj (.reset) -.text 0 00010000 00000280 - 00010000 00000076 rts430x_lc_rd_eabi.lib : copy_decompress_lzss.c.obj (.text:decompress:lzss:__TI_decompress_lzss) - 00010076 0000005c main.obj (.text:main) - 000100d2 00000054 clock_init.obj (.text:SetVCoreUp) - 00010126 00000054 rts430x_lc_rd_eabi.lib : autoinit.c.obj (.text:__TI_auto_init_nobinit_nopinit_hold_wdt:__TI_auto_init_nobinit_nopinit_hold_wdt) - 0001017a 0000003a clock_init.obj (.text:Clock_XT2_Init) - 000101b4 00000032 clock_init.obj (.text:Clock_XT1_Init) - 000101e6 00000028 clock_init.obj (.text:clock_init) - 0001020e 00000026 clock_init.obj (.text:Port_Init) - 00010234 0000001a main.obj (.text:timerB_init) - 0001024e 00000014 rts430x_lc_rd_eabi.lib : memcpy.c.obj (.text:memcpy) - 00010262 00000012 : copy_decompress_none.c.obj (.text:decompress:none:__TI_decompress_none) - 00010274 00000006 : exit.c.obj (.text:abort) - 0001027a 00000004 : pre_init.c.obj (.text:_system_pre_init) - 0001027e 00000002 : startup.c.obj (.text:_system_post_cinit) +.text 0 00010000 00000324 + 00010000 00000082 rts430x_lc_rd_eabi.lib : autoinit_wdt.obj (.text:_auto_init_hold_wdt) + 00010082 00000068 : copy_decompress_rle.obj (.text:__TI_decompress_rle_core) + 000100ea 00000066 : cpy_tbl.obj (.text:copy_in) + 00010150 0000005c main.obj (.text:main) + 000101ac 00000054 clock_init.obj (.text:SetVCoreUp) + 00010200 0000003a clock_init.obj (.text:Clock_XT2_Init) + 0001023a 00000032 clock_init.obj (.text:Clock_XT1_Init) + 0001026c 00000028 clock_init.obj (.text:clock_init) + 00010294 00000026 clock_init.obj (.text:Port_Init) + 000102ba 0000001a main.obj (.text:timerB_init) + 000102d4 00000018 rts430x_lc_rd_eabi.lib : mult16_f5hw.obj (.text) + 000102ec 00000014 : memcpy.obj (.text:memcpy) + 00010300 00000012 : copy_decompress_none.obj (.text:decompress:none:__TI_decompress_none) + 00010312 00000006 : exit.obj (.text:abort) + 00010318 00000006 : copy_decompress_rle.obj (.text:decompress:rle24:__TI_decompress_rle24) + 0001031e 00000004 : pre_init.obj (.text:_system_pre_init) + 00010322 00000002 : startup.obj (.text:_system_post_cinit) MODULE SUMMARY - Module code ro data rw data - ------ ---- ------- ------- + Module code ro data rw data + ------ ---- ------- ------- .\ - clock_init.obj 270 0 0 - main.obj 162 2 12 - +--+----------------------------+------+---------+---------+ - Total: 432 2 12 - - C:\TI_CCS\ccs\tools\compiler\ti-cgt-msp430_20.2.2.LTS\lib\rts430x_lc_rd_eabi.lib - copy_decompress_lzss.c.obj 118 0 0 - autoinit.c.obj 84 0 0 - boot.c.obj 28 2 0 - memcpy.c.obj 20 0 0 - copy_decompress_none.c.obj 18 0 0 - isr_trap.asm.obj 8 0 0 - exit.c.obj 6 0 0 - pre_init.c.obj 4 0 0 - int41.asm.obj 0 2 0 - int42.asm.obj 0 2 0 - int43.asm.obj 0 2 0 - int44.asm.obj 0 2 0 - int45.asm.obj 0 2 0 - int46.asm.obj 0 2 0 - int47.asm.obj 0 2 0 - int48.asm.obj 0 2 0 - int49.asm.obj 0 2 0 - int50.asm.obj 0 2 0 - int51.asm.obj 0 2 0 - int52.asm.obj 0 2 0 - int53.asm.obj 0 2 0 - int54.asm.obj 0 2 0 - int55.asm.obj 0 2 0 - int56.asm.obj 0 2 0 - int57.asm.obj 0 2 0 - int58.asm.obj 0 2 0 - int59.asm.obj 0 2 0 - int61.asm.obj 0 2 0 - int62.asm.obj 0 2 0 - startup.c.obj 2 0 0 - +--+----------------------------+------+---------+---------+ - Total: 288 44 0 - - Stack: 0 0 160 - Linker Generated: 0 27 0 - +--+----------------------------+------+---------+---------+ - Grand Total: 720 73 172 + clock_init.obj 270 0 0 + main.obj 162 2 12 + +--+--------------------------+------+---------+---------+ + Total: 432 2 12 + + C:\ti\ccsv6\tools\compiler\msp430_15.12.3.LTS\lib\rts430x_lc_rd_eabi.lib + autoinit_wdt.obj 130 0 0 + copy_decompress_rle.obj 110 0 0 + cpy_tbl.obj 102 0 0 + boot_special.obj 26 0 0 + mult16_f5hw.obj 24 0 0 + memcpy.obj 20 0 0 + copy_decompress_none.obj 18 0 0 + isr_trap.obj 8 0 0 + exit.obj 6 0 0 + pre_init.obj 4 0 0 + boot.obj 0 2 0 + int41.obj 0 2 0 + int42.obj 0 2 0 + int43.obj 0 2 0 + int44.obj 0 2 0 + int45.obj 0 2 0 + int46.obj 0 2 0 + int47.obj 0 2 0 + int48.obj 0 2 0 + int49.obj 0 2 0 + int50.obj 0 2 0 + int51.obj 0 2 0 + int52.obj 0 2 0 + int53.obj 0 2 0 + int54.obj 0 2 0 + int55.obj 0 2 0 + int56.obj 0 2 0 + int57.obj 0 2 0 + int58.obj 0 2 0 + int59.obj 0 2 0 + int61.obj 0 2 0 + int62.obj 0 2 0 + startup.obj 2 0 0 + +--+--------------------------+------+---------+---------+ + Total: 450 44 0 + + Stack: 0 0 160 + Linker Generated: 0 29 0 + +--+--------------------------+------+---------+---------+ + Grand Total: 882 75 172 LINKER GENERATED COPY TABLES __TI_cinit_table @ 00005c64 records: 1, size/record: 8, table size: 8 - .data: load addr=00005c50, load size=0000000b bytes, run addr=00001c00, run size=0000000c bytes, compression=lzss + .data: load addr=00005c4e, load size=0000000d bytes, run addr=00001c00, run size=0000000c bytes, compression=rle LINKER GENERATED HANDLER TABLE __TI_handler_table @ 00005c5c records: 2, size/record: 4, table size: 8 - index: 0, handler: __TI_decompress_lzss + index: 0, handler: __TI_decompress_rle24 index: 1, handler: __TI_decompress_none GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name -address name -------- ---- -00000700 ADC12CTL0 -00000701 ADC12CTL0_H -00000700 ADC12CTL0_L -00000702 ADC12CTL1 -00000703 ADC12CTL1_H -00000702 ADC12CTL1_L -00000704 ADC12CTL2 -00000705 ADC12CTL2_H -00000704 ADC12CTL2_L -0000070c ADC12IE -0000070d ADC12IE_H -0000070c ADC12IE_L -0000070a ADC12IFG -0000070b ADC12IFG_H -0000070a ADC12IFG_L -0000070e ADC12IV -0000070f ADC12IV_H -0000070e ADC12IV_L -00000710 ADC12MCTL0 -00000711 ADC12MCTL1 -0000071a ADC12MCTL10 -0000071b ADC12MCTL11 -0000071c ADC12MCTL12 -0000071d ADC12MCTL13 -0000071e ADC12MCTL14 -0000071f ADC12MCTL15 -00000712 ADC12MCTL2 -00000713 ADC12MCTL3 -00000714 ADC12MCTL4 -00000715 ADC12MCTL5 -00000716 ADC12MCTL6 -00000717 ADC12MCTL7 -00000718 ADC12MCTL8 -00000719 ADC12MCTL9 -00000720 ADC12MEM0 -00000721 ADC12MEM0_H -00000720 ADC12MEM0_L -00000722 ADC12MEM1 -00000734 ADC12MEM10 -00000735 ADC12MEM10_H -00000734 ADC12MEM10_L -00000736 ADC12MEM11 -00000737 ADC12MEM11_H -00000736 ADC12MEM11_L -00000738 ADC12MEM12 -00000739 ADC12MEM12_H -00000738 ADC12MEM12_L -0000073a ADC12MEM13 -0000073b ADC12MEM13_H -0000073a ADC12MEM13_L -0000073c ADC12MEM14 -0000073d ADC12MEM14_H -0000073c ADC12MEM14_L -0000073e ADC12MEM15 -0000073f ADC12MEM15_H -0000073e ADC12MEM15_L -00000723 ADC12MEM1_H -00000722 ADC12MEM1_L -00000724 ADC12MEM2 -00000725 ADC12MEM2_H -00000724 ADC12MEM2_L -00000726 ADC12MEM3 -00000727 ADC12MEM3_H -00000726 ADC12MEM3_L -00000728 ADC12MEM4 -00000729 ADC12MEM4_H -00000728 ADC12MEM4_L -0000072a ADC12MEM5 -0000072b ADC12MEM5_H -0000072a ADC12MEM5_L -0000072c ADC12MEM6 -0000072d ADC12MEM6_H -0000072c ADC12MEM6_L -0000072e ADC12MEM7 -0000072f ADC12MEM7_H -0000072e ADC12MEM7_L -00000730 ADC12MEM8 -00000731 ADC12MEM8_H -00000730 ADC12MEM8_L -00000732 ADC12MEM9 -00000733 ADC12MEM9_H -00000732 ADC12MEM9_L -00010274 C$$EXIT -00000150 CRCDI -00000152 CRCDIRB -00000153 CRCDIRB_H -00000152 CRCDIRB_L -00000151 CRCDI_H -00000150 CRCDI_L -00000154 CRCINIRES -00000155 CRCINIRES_H -00000154 CRCINIRES_L -00000156 CRCRESR -00000157 CRCRESR_H -00000156 CRCRESR_L -000101b4 Clock_XT1_Init -0001017a Clock_XT2_Init -00000510 DMA0CTL -00000516 DMA0DA -00000518 DMA0DAH -00000516 DMA0DAL -00000512 DMA0SA -00000514 DMA0SAH -00000512 DMA0SAL -0000051a DMA0SZ -00000520 DMA1CTL -00000526 DMA1DA -00000528 DMA1DAH -00000526 DMA1DAL -00000522 DMA1SA -00000524 DMA1SAH -00000522 DMA1SAL -0000052a DMA1SZ -00000530 DMA2CTL -00000536 DMA2DA -00000538 DMA2DAH -00000536 DMA2DAL -00000532 DMA2SA -00000534 DMA2SAH -00000532 DMA2SAL -0000053a DMA2SZ -00000500 DMACTL0 -00000502 DMACTL1 -00000504 DMACTL2 -00000506 DMACTL3 -00000508 DMACTL4 -0000050e DMAIV -00000140 FCTL1 -00000141 FCTL1_H -00000140 FCTL1_L -00000144 FCTL3 -00000145 FCTL3_H -00000144 FCTL3_L -00000146 FCTL4 -00000147 FCTL4_H -00000146 FCTL4_L -000004c4 MAC -000004da MAC32H -000004db MAC32H_H -000004da MAC32H_L -000004d8 MAC32L -000004d9 MAC32L_H -000004d8 MAC32L_L -000004c6 MACS -000004de MACS32H -000004df MACS32H_H -000004de MACS32H_L -000004dc MACS32L -000004dd MACS32L_H -000004dc MACS32L_L -000004c7 MACS_H -000004c6 MACS_L -000004c5 MAC_H -000004c4 MAC_L -000004c0 MPY -000004ec MPY32CTL0 -000004ed MPY32CTL0_H -000004ec MPY32CTL0_L -000004d2 MPY32H -000004d3 MPY32H_H -000004d2 MPY32H_L -000004d0 MPY32L -000004d1 MPY32L_H -000004d0 MPY32L_L -000004c2 MPYS -000004d6 MPYS32H -000004d7 MPYS32H_H -000004d6 MPYS32H_L -000004d4 MPYS32L -000004d5 MPYS32L_H -000004d4 MPYS32L_L -000004c3 MPYS_H -000004c2 MPYS_L -000004c1 MPY_H -000004c0 MPY_L -000004c8 OP2 -000004e2 OP2H -000004e3 OP2H_H -000004e2 OP2H_L -000004e0 OP2L -000004e1 OP2L_H -000004e0 OP2L_L -000004c9 OP2_H -000004c8 OP2_L -0000020e P1IV -0000021e P2IV -00000204 PADIR -00000205 PADIR_H -00000204 PADIR_L -00000208 PADS -00000209 PADS_H -00000208 PADS_L -0000021a PAIE -00000218 PAIES -00000219 PAIES_H -00000218 PAIES_L -0000021b PAIE_H -0000021a PAIE_L -0000021c PAIFG -0000021d PAIFG_H -0000021c PAIFG_L -00000200 PAIN -00000201 PAIN_H -00000200 PAIN_L -00000202 PAOUT -00000203 PAOUT_H -00000202 PAOUT_L -00000206 PAREN -00000207 PAREN_H -00000206 PAREN_L -0000020a PASEL -0000020b PASEL_H -0000020a PASEL_L -00000224 PBDIR -00000225 PBDIR_H -00000224 PBDIR_L -00000228 PBDS -00000229 PBDS_H -00000228 PBDS_L -00000220 PBIN -00000221 PBIN_H -00000220 PBIN_L -00000222 PBOUT -00000223 PBOUT_H -00000222 PBOUT_L -00000226 PBREN -00000227 PBREN_H -00000226 PBREN_L -0000022a PBSEL -0000022b PBSEL_H -0000022a PBSEL_L -00000244 PCDIR -00000245 PCDIR_H -00000244 PCDIR_L -00000248 PCDS -00000249 PCDS_H -00000248 PCDS_L -00000240 PCIN -00000241 PCIN_H -00000240 PCIN_L -00000242 PCOUT -00000243 PCOUT_H -00000242 PCOUT_L -00000246 PCREN -00000247 PCREN_H -00000246 PCREN_L -0000024a PCSEL -0000024b PCSEL_H -0000024a PCSEL_L -00000264 PDDIR -00000265 PDDIR_H -00000264 PDDIR_L -00000268 PDDS -00000269 PDDS_H -00000268 PDDS_L -00000260 PDIN -00000261 PDIN_H -00000260 PDIN_L -00000262 PDOUT -00000263 PDOUT_H -00000262 PDOUT_L -00000266 PDREN -00000267 PDREN_H -00000266 PDREN_L -0000026a PDSEL -0000026b PDSEL_H -0000026a PDSEL_L -00000284 PEDIR -00000285 PEDIR_H -00000284 PEDIR_L -00000288 PEDS -00000289 PEDS_H -00000288 PEDS_L -00000280 PEIN -00000281 PEIN_H -00000280 PEIN_L -00000282 PEOUT -00000283 PEOUT_H -00000282 PEOUT_L -00000286 PEREN -00000287 PEREN_H -00000286 PEREN_L -0000028a PESEL -0000028b PESEL_H -0000028a PESEL_L -000002a4 PFDIR -000002a5 PFDIR_H -000002a4 PFDIR_L -000002a8 PFDS -000002a9 PFDS_H -000002a8 PFDS_L -000002a0 PFIN -000002a1 PFIN_H -000002a0 PFIN_L -000002a2 PFOUT -000002a3 PFOUT_H -000002a2 PFOUT_L -000002a6 PFREN -000002a7 PFREN_H -000002a6 PFREN_L -000002aa PFSEL -000002ab PFSEL_H -000002aa PFSEL_L -00000324 PJDIR -00000325 PJDIR_H -00000324 PJDIR_L -00000328 PJDS -00000329 PJDS_H -00000328 PJDS_L -00000320 PJIN -00000321 PJIN_H -00000320 PJIN_L -00000322 PJOUT -00000323 PJOUT_H -00000322 PJOUT_L -00000326 PJREN -00000327 PJREN_H -00000326 PJREN_L -00000130 PM5CTL0 -00000131 PM5CTL0_H -00000130 PM5CTL0_L -00000120 PMMCTL0 -00000121 PMMCTL0_H -00000120 PMMCTL0_L -00000122 PMMCTL1 -00000123 PMMCTL1_H -00000122 PMMCTL1_L -0000012c PMMIFG -0000012d PMMIFG_H -0000012c PMMIFG_L -0000012e PMMRIE -0000012f PMMRIE_H -0000012e PMMRIE_L -0001020e Port_Init -00000158 RCCTL0 -00000159 RCCTL0_H -00000158 RCCTL0_L -000001b0 REFCTL0 -000001b1 REFCTL0_H -000001b0 REFCTL0_L -000004e4 RES0 -000004e5 RES0_H -000004e4 RES0_L -000004e6 RES1 -000004e7 RES1_H -000004e6 RES1_L -000004e8 RES2 -000004e9 RES2_H -000004e8 RES2_L -000004ea RES3 -000004eb RES3_H -000004ea RES3_L -000004cc RESHI -000004cd RESHI_H -000004cc RESHI_L -000004ca RESLO -000004cb RESLO_H -000004ca RESLO_L -000004ba RTCADOWDAY -000004bb RTCADOWDAY_H -000004ba RTCADOWDAY_L -000004b8 RTCAMINHR -000004b9 RTCAMINHR_H -000004b8 RTCAMINHR_L -000004a0 RTCCTL01 -000004a1 RTCCTL01_H -000004a0 RTCCTL01_L -000004a2 RTCCTL23 -000004a3 RTCCTL23_H -000004a2 RTCCTL23_L -000004b4 RTCDATE -000004b5 RTCDATE_H -000004b4 RTCDATE_L -000004ae RTCIV -000004ac RTCPS -000004a8 RTCPS0CTL -000004a9 RTCPS0CTL_H -000004a8 RTCPS0CTL_L -000004aa RTCPS1CTL -000004ab RTCPS1CTL_H -000004aa RTCPS1CTL_L -000004ad RTCPS_H -000004ac RTCPS_L -000004b0 RTCTIM0 -000004b1 RTCTIM0_H -000004b0 RTCTIM0_L -000004b2 RTCTIM1 -000004b3 RTCTIM1_H -000004b2 RTCTIM1_L -000004b6 RTCYEAR -000004b7 RTCYEAR_H -000004b6 RTCYEAR_L -00000100 SFRIE1 -00000101 SFRIE1_H -00000100 SFRIE1_L -00000102 SFRIFG1 -00000103 SFRIFG1_H -00000102 SFRIFG1_L -00000104 SFRRPCR -00000105 SFRRPCR_H -00000104 SFRRPCR_L -000004ce SUMEXT -000004cf SUMEXT_H -000004ce SUMEXT_L -00000124 SVSMHCTL -00000125 SVSMHCTL_H -00000124 SVSMHCTL_L -00000128 SVSMIO -00000129 SVSMIO_H -00000128 SVSMIO_L -00000126 SVSMLCTL -00000127 SVSMLCTL_H -00000126 SVSMLCTL_L -00000198 SYSBERRIV -00000199 SYSBERRIV_H -00000198 SYSBERRIV_L -00000182 SYSBSLC -00000183 SYSBSLC_H -00000182 SYSBSLC_L -00000180 SYSCTL -00000181 SYSCTL_H -00000180 SYSCTL_L -00000186 SYSJMBC -00000187 SYSJMBC_H -00000186 SYSJMBC_L -00000188 SYSJMBI0 -00000189 SYSJMBI0_H -00000188 SYSJMBI0_L -0000018a SYSJMBI1 -0000018b SYSJMBI1_H -0000018a SYSJMBI1_L -0000018c SYSJMBO0 -0000018d SYSJMBO0_H -0000018c SYSJMBO0_L -0000018e SYSJMBO1 -0000018f SYSJMBO1_H -0000018e SYSJMBO1_L -0000019e SYSRSTIV -0000019f SYSRSTIV_H -0000019e SYSRSTIV_L -0000019c SYSSNIV -0000019d SYSSNIV_H -0000019c SYSSNIV_L -0000019a SYSUNIV -0000019b SYSUNIV_H -0000019a SYSUNIV_L -000100d2 SetVCoreUp -00000352 TA0CCR0 -00000354 TA0CCR1 -00000356 TA0CCR2 -00000358 TA0CCR3 -0000035a TA0CCR4 -00000342 TA0CCTL0 -00000344 TA0CCTL1 -00000346 TA0CCTL2 -00000348 TA0CCTL3 -0000034a TA0CCTL4 -00000340 TA0CTL -00000360 TA0EX0 -0000036e TA0IV -00000350 TA0R -00000392 TA1CCR0 -00000394 TA1CCR1 -00000396 TA1CCR2 -00000382 TA1CCTL0 -00000384 TA1CCTL1 -00000386 TA1CCTL2 -00000380 TA1CTL -000003a0 TA1EX0 -000003ae TA1IV -00000390 TA1R -000003d2 TB0CCR0 -000003d4 TB0CCR1 -000003d6 TB0CCR2 -000003d8 TB0CCR3 -000003da TB0CCR4 -000003dc TB0CCR5 -000003de TB0CCR6 -000003c2 TB0CCTL0 -000003c4 TB0CCTL1 -000003c6 TB0CCTL2 -000003c8 TB0CCTL3 -000003ca TB0CCTL4 -000003cc TB0CCTL5 -000003ce TB0CCTL6 -000003c0 TB0CTL -000003e0 TB0EX0 -000003ee TB0IV -000003d0 TB0R -000005d0 UCA0ABCTL -000005c6 UCA0BRW -000005c7 UCA0BRW_H -000005c6 UCA0BRW_L -000005c0 UCA0CTLW0 -000005c1 UCA0CTLW0_H -000005c0 UCA0CTLW0_L -000005dc UCA0ICTL -000005dd UCA0ICTL_H -000005dc UCA0ICTL_L -000005d2 UCA0IRCTL -000005d3 UCA0IRCTL_H -000005d2 UCA0IRCTL_L -000005de UCA0IV -000005c8 UCA0MCTL -000005cc UCA0RXBUF -000005ca UCA0STAT -000005ce UCA0TXBUF -00000610 UCA1ABCTL -00000606 UCA1BRW -00000607 UCA1BRW_H -00000606 UCA1BRW_L -00000600 UCA1CTLW0 -00000601 UCA1CTLW0_H -00000600 UCA1CTLW0_L -0000061c UCA1ICTL -0000061d UCA1ICTL_H -0000061c UCA1ICTL_L -00000612 UCA1IRCTL -00000613 UCA1IRCTL_H -00000612 UCA1IRCTL_L -0000061e UCA1IV -00000608 UCA1MCTL -0000060c UCA1RXBUF -0000060a UCA1STAT -0000060e UCA1TXBUF -00000650 UCA2ABCTL -00000646 UCA2BRW -00000647 UCA2BRW_H -00000646 UCA2BRW_L -00000640 UCA2CTLW0 -00000641 UCA2CTLW0_H -00000640 UCA2CTLW0_L -0000065c UCA2ICTL -0000065d UCA2ICTL_H -0000065c UCA2ICTL_L -00000652 UCA2IRCTL -00000653 UCA2IRCTL_H -00000652 UCA2IRCTL_L -0000065e UCA2IV -00000648 UCA2MCTL -0000064c UCA2RXBUF -0000064a UCA2STAT -0000064e UCA2TXBUF -00000690 UCA3ABCTL -00000686 UCA3BRW -00000687 UCA3BRW_H -00000686 UCA3BRW_L -00000680 UCA3CTLW0 -00000681 UCA3CTLW0_H -00000680 UCA3CTLW0_L -0000069c UCA3ICTL -0000069d UCA3ICTL_H -0000069c UCA3ICTL_L -00000692 UCA3IRCTL -00000693 UCA3IRCTL_H -00000692 UCA3IRCTL_L -0000069e UCA3IV -00000688 UCA3MCTL -0000068c UCA3RXBUF -0000068a UCA3STAT -0000068e UCA3TXBUF -000005e6 UCB0BRW -000005e7 UCB0BRW_H -000005e6 UCB0BRW_L -000005e0 UCB0CTLW0 -000005e1 UCB0CTLW0_H -000005e0 UCB0CTLW0_L -000005f0 UCB0I2COA -000005f1 UCB0I2COA_H -000005f0 UCB0I2COA_L -000005f2 UCB0I2CSA -000005f3 UCB0I2CSA_H -000005f2 UCB0I2CSA_L -000005fc UCB0ICTL -000005fd UCB0ICTL_H -000005fc UCB0ICTL_L -000005fe UCB0IV -000005ec UCB0RXBUF -000005ea UCB0STAT -000005ee UCB0TXBUF -00000626 UCB1BRW -00000627 UCB1BRW_H -00000626 UCB1BRW_L -00000620 UCB1CTLW0 -00000621 UCB1CTLW0_H -00000620 UCB1CTLW0_L -00000630 UCB1I2COA -00000631 UCB1I2COA_H -00000630 UCB1I2COA_L -00000632 UCB1I2CSA -00000633 UCB1I2CSA_H -00000632 UCB1I2CSA_L -0000063c UCB1ICTL -0000063d UCB1ICTL_H -0000063c UCB1ICTL_L -0000063e UCB1IV -0000062c UCB1RXBUF -0000062a UCB1STAT -0000062e UCB1TXBUF -00000666 UCB2BRW -00000667 UCB2BRW_H -00000666 UCB2BRW_L -00000660 UCB2CTLW0 -00000661 UCB2CTLW0_H -00000660 UCB2CTLW0_L -00000670 UCB2I2COA -00000671 UCB2I2COA_H -00000670 UCB2I2COA_L -00000672 UCB2I2CSA -00000673 UCB2I2CSA_H -00000672 UCB2I2CSA_L -0000067c UCB2ICTL -0000067d UCB2ICTL_H -0000067c UCB2ICTL_L -0000067e UCB2IV -0000066c UCB2RXBUF -0000066a UCB2STAT -0000066e UCB2TXBUF -000006a6 UCB3BRW -000006a7 UCB3BRW_H -000006a6 UCB3BRW_L -000006a0 UCB3CTLW0 -000006a1 UCB3CTLW0_H -000006a0 UCB3CTLW0_L -000006b0 UCB3I2COA -000006b1 UCB3I2COA_H -000006b0 UCB3I2COA_L -000006b2 UCB3I2CSA -000006b3 UCB3I2CSA_H -000006b2 UCB3I2CSA_L -000006bc UCB3ICTL -000006bd UCB3ICTL_H -000006bc UCB3ICTL_L -000006be UCB3IV -000006ac UCB3RXBUF -000006aa UCB3STAT -000006ae UCB3TXBUF -00000160 UCSCTL0 -00000161 UCSCTL0_H -00000160 UCSCTL0_L -00000162 UCSCTL1 -00000163 UCSCTL1_H -00000162 UCSCTL1_L -00000164 UCSCTL2 -00000165 UCSCTL2_H -00000164 UCSCTL2_L -00000166 UCSCTL3 -00000167 UCSCTL3_H -00000166 UCSCTL3_L -00000168 UCSCTL4 -00000169 UCSCTL4_H -00000168 UCSCTL4_L -0000016a UCSCTL5 -0000016b UCSCTL5_H -0000016a UCSCTL5_L -0000016c UCSCTL6 -0000016d UCSCTL6_H -0000016c UCSCTL6_L -0000016e UCSCTL7 -0000016f UCSCTL7_H -0000016e UCSCTL7_L -00000170 UCSCTL8 -00000171 UCSCTL8_H -00000170 UCSCTL8_L -0000015c WDTCTL -0000015d WDTCTL_H -0000015c WDTCTL_L -00005c00 __STACK_END -000000a0 __STACK_SIZE -00005c64 __TI_CINIT_Base -00005c6c __TI_CINIT_Limit -00005c5c __TI_Handler_Table_Base -00005c64 __TI_Handler_Table_Limit -00005c48 __TI_ISR_TRAP -00010126 __TI_auto_init_nobinit_nopinit_hold_wdt -00010000 __TI_decompress_lzss -00010262 __TI_decompress_none -0000ffd2 __TI_int41 -0000ffd4 __TI_int42 -0000ffd6 __TI_int43 -0000ffd8 __TI_int44 -0000ffda __TI_int45 -0000ffdc __TI_int46 -0000ffde __TI_int47 -0000ffe0 __TI_int48 -0000ffe2 __TI_int49 -0000ffe4 __TI_int50 -0000ffe6 __TI_int51 -0000ffe8 __TI_int52 -0000ffea __TI_int53 -0000ffec __TI_int54 -0000ffee __TI_int55 -0000fff0 __TI_int56 -0000fff2 __TI_int57 -0000fff4 __TI_int58 -0000fff6 __TI_int59 -0000fff8 __TI_int60 -0000fffa __TI_int61 -0000fffc __TI_int62 -ffffffff __TI_pprof_out_hndl -ffffffff __TI_prof_data_size -ffffffff __TI_prof_data_start -ffffffff __c_args__ -00005c2c _c_int00_noargs -0000fffe _reset_vector -00005b60 _stack -0001027e _system_post_cinit -0001027a _system_pre_init -00010274 abort -00001c05 ac_charge_mode -00001c04 can_full -00001c01 cancomm_flag -00001c07 charge_mode -000101e6 clock_init -00001c06 dc_charge_mode -00010076 main -0001024e memcpy -00001c03 rcv_can -00001c02 send_can -00001c00 status_flag -00010234 timerB_init -00005c00 timer_b0 +address name +------- ---- +00000700 ADC12CTL0 +00000701 ADC12CTL0_H +00000700 ADC12CTL0_L +00000702 ADC12CTL1 +00000703 ADC12CTL1_H +00000702 ADC12CTL1_L +00000704 ADC12CTL2 +00000705 ADC12CTL2_H +00000704 ADC12CTL2_L +0000070c ADC12IE +0000070d ADC12IE_H +0000070c ADC12IE_L +0000070a ADC12IFG +0000070b ADC12IFG_H +0000070a ADC12IFG_L +0000070e ADC12IV +0000070f ADC12IV_H +0000070e ADC12IV_L +00000710 ADC12MCTL0 +00000711 ADC12MCTL1 +0000071a ADC12MCTL10 +0000071b ADC12MCTL11 +0000071c ADC12MCTL12 +0000071d ADC12MCTL13 +0000071e ADC12MCTL14 +0000071f ADC12MCTL15 +00000712 ADC12MCTL2 +00000713 ADC12MCTL3 +00000714 ADC12MCTL4 +00000715 ADC12MCTL5 +00000716 ADC12MCTL6 +00000717 ADC12MCTL7 +00000718 ADC12MCTL8 +00000719 ADC12MCTL9 +00000720 ADC12MEM0 +00000721 ADC12MEM0_H +00000720 ADC12MEM0_L +00000722 ADC12MEM1 +00000734 ADC12MEM10 +00000735 ADC12MEM10_H +00000734 ADC12MEM10_L +00000736 ADC12MEM11 +00000737 ADC12MEM11_H +00000736 ADC12MEM11_L +00000738 ADC12MEM12 +00000739 ADC12MEM12_H +00000738 ADC12MEM12_L +0000073a ADC12MEM13 +0000073b ADC12MEM13_H +0000073a ADC12MEM13_L +0000073c ADC12MEM14 +0000073d ADC12MEM14_H +0000073c ADC12MEM14_L +0000073e ADC12MEM15 +0000073f ADC12MEM15_H +0000073e ADC12MEM15_L +00000723 ADC12MEM1_H +00000722 ADC12MEM1_L +00000724 ADC12MEM2 +00000725 ADC12MEM2_H +00000724 ADC12MEM2_L +00000726 ADC12MEM3 +00000727 ADC12MEM3_H +00000726 ADC12MEM3_L +00000728 ADC12MEM4 +00000729 ADC12MEM4_H +00000728 ADC12MEM4_L +0000072a ADC12MEM5 +0000072b ADC12MEM5_H +0000072a ADC12MEM5_L +0000072c ADC12MEM6 +0000072d ADC12MEM6_H +0000072c ADC12MEM6_L +0000072e ADC12MEM7 +0000072f ADC12MEM7_H +0000072e ADC12MEM7_L +00000730 ADC12MEM8 +00000731 ADC12MEM8_H +00000730 ADC12MEM8_L +00000732 ADC12MEM9 +00000733 ADC12MEM9_H +00000732 ADC12MEM9_L +00010312 C$$EXIT +00000150 CRCDI +00000152 CRCDIRB +00000153 CRCDIRB_H +00000152 CRCDIRB_L +00000151 CRCDI_H +00000150 CRCDI_L +00000154 CRCINIRES +00000155 CRCINIRES_H +00000154 CRCINIRES_L +00000156 CRCRESR +00000157 CRCRESR_H +00000156 CRCRESR_L +0001023a Clock_XT1_Init +00010200 Clock_XT2_Init +00000510 DMA0CTL +00000511 DMA0CTL_H +00000510 DMA0CTL_L +00000516 DMA0DA +00000518 DMA0DAH +00000516 DMA0DAL +00000512 DMA0SA +00000514 DMA0SAH +00000512 DMA0SAL +0000051a DMA0SZ +00000520 DMA1CTL +00000521 DMA1CTL_H +00000520 DMA1CTL_L +00000526 DMA1DA +00000528 DMA1DAH +00000526 DMA1DAL +00000522 DMA1SA +00000524 DMA1SAH +00000522 DMA1SAL +0000052a DMA1SZ +00000530 DMA2CTL +00000531 DMA2CTL_H +00000530 DMA2CTL_L +00000536 DMA2DA +00000538 DMA2DAH +00000536 DMA2DAL +00000532 DMA2SA +00000534 DMA2SAH +00000532 DMA2SAL +0000053a DMA2SZ +00000500 DMACTL0 +00000501 DMACTL0_H +00000500 DMACTL0_L +00000502 DMACTL1 +00000503 DMACTL1_H +00000502 DMACTL1_L +00000504 DMACTL2 +00000505 DMACTL2_H +00000504 DMACTL2_L +00000506 DMACTL3 +00000507 DMACTL3_H +00000506 DMACTL3_L +00000508 DMACTL4 +00000509 DMACTL4_H +00000508 DMACTL4_L +0000050e DMAIV +0000050f DMAIV_H +0000050e DMAIV_L +00000140 FCTL1 +00000141 FCTL1_H +00000140 FCTL1_L +00000144 FCTL3 +00000145 FCTL3_H +00000144 FCTL3_L +00000146 FCTL4 +00000147 FCTL4_H +00000146 FCTL4_L +000004c4 MAC +000004da MAC32H +000004db MAC32H_H +000004da MAC32H_L +000004d8 MAC32L +000004d9 MAC32L_H +000004d8 MAC32L_L +000004c6 MACS +000004de MACS32H +000004df MACS32H_H +000004de MACS32H_L +000004dc MACS32L +000004dd MACS32L_H +000004dc MACS32L_L +000004c7 MACS_H +000004c6 MACS_L +000004c5 MAC_H +000004c4 MAC_L +000004c0 MPY +000004ec MPY32CTL0 +000004ed MPY32CTL0_H +000004ec MPY32CTL0_L +000004d2 MPY32H +000004d3 MPY32H_H +000004d2 MPY32H_L +000004d0 MPY32L +000004d1 MPY32L_H +000004d0 MPY32L_L +000004c2 MPYS +000004d6 MPYS32H +000004d7 MPYS32H_H +000004d6 MPYS32H_L +000004d4 MPYS32L +000004d5 MPYS32L_H +000004d4 MPYS32L_L +000004c3 MPYS_H +000004c2 MPYS_L +000004c1 MPY_H +000004c0 MPY_L +000004c8 OP2 +000004e2 OP2H +000004e3 OP2H_H +000004e2 OP2H_L +000004e0 OP2L +000004e1 OP2L_H +000004e0 OP2L_L +000004c9 OP2_H +000004c8 OP2_L +0000020e P1IV +0000021e P2IV +00000204 PADIR +00000205 PADIR_H +00000204 PADIR_L +00000208 PADS +00000209 PADS_H +00000208 PADS_L +0000021a PAIE +00000218 PAIES +00000219 PAIES_H +00000218 PAIES_L +0000021b PAIE_H +0000021a PAIE_L +0000021c PAIFG +0000021d PAIFG_H +0000021c PAIFG_L +00000200 PAIN +00000201 PAIN_H +00000200 PAIN_L +00000202 PAOUT +00000203 PAOUT_H +00000202 PAOUT_L +00000206 PAREN +00000207 PAREN_H +00000206 PAREN_L +0000020a PASEL +0000020b PASEL_H +0000020a PASEL_L +00000224 PBDIR +00000225 PBDIR_H +00000224 PBDIR_L +00000228 PBDS +00000229 PBDS_H +00000228 PBDS_L +00000220 PBIN +00000221 PBIN_H +00000220 PBIN_L +00000222 PBOUT +00000223 PBOUT_H +00000222 PBOUT_L +00000226 PBREN +00000227 PBREN_H +00000226 PBREN_L +0000022a PBSEL +0000022b PBSEL_H +0000022a PBSEL_L +00000244 PCDIR +00000245 PCDIR_H +00000244 PCDIR_L +00000248 PCDS +00000249 PCDS_H +00000248 PCDS_L +00000240 PCIN +00000241 PCIN_H +00000240 PCIN_L +00000242 PCOUT +00000243 PCOUT_H +00000242 PCOUT_L +00000246 PCREN +00000247 PCREN_H +00000246 PCREN_L +0000024a PCSEL +0000024b PCSEL_H +0000024a PCSEL_L +00000264 PDDIR +00000265 PDDIR_H +00000264 PDDIR_L +00000268 PDDS +00000269 PDDS_H +00000268 PDDS_L +00000260 PDIN +00000261 PDIN_H +00000260 PDIN_L +00000262 PDOUT +00000263 PDOUT_H +00000262 PDOUT_L +00000266 PDREN +00000267 PDREN_H +00000266 PDREN_L +0000026a PDSEL +0000026b PDSEL_H +0000026a PDSEL_L +00000284 PEDIR +00000285 PEDIR_H +00000284 PEDIR_L +00000288 PEDS +00000289 PEDS_H +00000288 PEDS_L +00000280 PEIN +00000281 PEIN_H +00000280 PEIN_L +00000282 PEOUT +00000283 PEOUT_H +00000282 PEOUT_L +00000286 PEREN +00000287 PEREN_H +00000286 PEREN_L +0000028a PESEL +0000028b PESEL_H +0000028a PESEL_L +000002a4 PFDIR +000002a5 PFDIR_H +000002a4 PFDIR_L +000002a8 PFDS +000002a9 PFDS_H +000002a8 PFDS_L +000002a0 PFIN +000002a1 PFIN_H +000002a0 PFIN_L +000002a2 PFOUT +000002a3 PFOUT_H +000002a2 PFOUT_L +000002a6 PFREN +000002a7 PFREN_H +000002a6 PFREN_L +000002aa PFSEL +000002ab PFSEL_H +000002aa PFSEL_L +00000324 PJDIR +00000325 PJDIR_H +00000324 PJDIR_L +00000328 PJDS +00000329 PJDS_H +00000328 PJDS_L +00000320 PJIN +00000321 PJIN_H +00000320 PJIN_L +00000322 PJOUT +00000323 PJOUT_H +00000322 PJOUT_L +00000326 PJREN +00000327 PJREN_H +00000326 PJREN_L +00000130 PM5CTL0 +00000131 PM5CTL0_H +00000130 PM5CTL0_L +00000120 PMMCTL0 +00000121 PMMCTL0_H +00000120 PMMCTL0_L +00000122 PMMCTL1 +00000123 PMMCTL1_H +00000122 PMMCTL1_L +0000012c PMMIFG +0000012d PMMIFG_H +0000012c PMMIFG_L +0000012e PMMRIE +0000012f PMMRIE_H +0000012e PMMRIE_L +00010294 Port_Init +00000158 RCCTL0 +00000159 RCCTL0_H +00000158 RCCTL0_L +000001b0 REFCTL0 +000001b1 REFCTL0_H +000001b0 REFCTL0_L +000004e4 RES0 +000004e5 RES0_H +000004e4 RES0_L +000004e6 RES1 +000004e7 RES1_H +000004e6 RES1_L +000004e8 RES2 +000004e9 RES2_H +000004e8 RES2_L +000004ea RES3 +000004eb RES3_H +000004ea RES3_L +000004cc RESHI +000004cd RESHI_H +000004cc RESHI_L +000004ca RESLO +000004cb RESLO_H +000004ca RESLO_L +000004ba RTCADOWDAY +000004bb RTCADOWDAY_H +000004ba RTCADOWDAY_L +000004b8 RTCAMINHR +000004b9 RTCAMINHR_H +000004b8 RTCAMINHR_L +000004a0 RTCCTL01 +000004a1 RTCCTL01_H +000004a0 RTCCTL01_L +000004a2 RTCCTL23 +000004a3 RTCCTL23_H +000004a2 RTCCTL23_L +000004b4 RTCDATE +000004b5 RTCDATE_H +000004b4 RTCDATE_L +000004ae RTCIV +000004ac RTCPS +000004a8 RTCPS0CTL +000004a9 RTCPS0CTL_H +000004a8 RTCPS0CTL_L +000004aa RTCPS1CTL +000004ab RTCPS1CTL_H +000004aa RTCPS1CTL_L +000004ad RTCPS_H +000004ac RTCPS_L +000004b0 RTCTIM0 +000004b1 RTCTIM0_H +000004b0 RTCTIM0_L +000004b2 RTCTIM1 +000004b3 RTCTIM1_H +000004b2 RTCTIM1_L +000004b6 RTCYEAR +000004b7 RTCYEAR_H +000004b6 RTCYEAR_L +00000100 SFRIE1 +00000101 SFRIE1_H +00000100 SFRIE1_L +00000102 SFRIFG1 +00000103 SFRIFG1_H +00000102 SFRIFG1_L +00000104 SFRRPCR +00000105 SFRRPCR_H +00000104 SFRRPCR_L +000004ce SUMEXT +000004cf SUMEXT_H +000004ce SUMEXT_L +00000124 SVSMHCTL +00000125 SVSMHCTL_H +00000124 SVSMHCTL_L +00000128 SVSMIO +00000129 SVSMIO_H +00000128 SVSMIO_L +00000126 SVSMLCTL +00000127 SVSMLCTL_H +00000126 SVSMLCTL_L +00000198 SYSBERRIV +00000199 SYSBERRIV_H +00000198 SYSBERRIV_L +00000182 SYSBSLC +00000183 SYSBSLC_H +00000182 SYSBSLC_L +00000180 SYSCTL +00000181 SYSCTL_H +00000180 SYSCTL_L +00000186 SYSJMBC +00000187 SYSJMBC_H +00000186 SYSJMBC_L +00000188 SYSJMBI0 +00000189 SYSJMBI0_H +00000188 SYSJMBI0_L +0000018a SYSJMBI1 +0000018b SYSJMBI1_H +0000018a SYSJMBI1_L +0000018c SYSJMBO0 +0000018d SYSJMBO0_H +0000018c SYSJMBO0_L +0000018e SYSJMBO1 +0000018f SYSJMBO1_H +0000018e SYSJMBO1_L +0000019e SYSRSTIV +0000019f SYSRSTIV_H +0000019e SYSRSTIV_L +0000019c SYSSNIV +0000019d SYSSNIV_H +0000019c SYSSNIV_L +0000019a SYSUNIV +0000019b SYSUNIV_H +0000019a SYSUNIV_L +000101ac SetVCoreUp +00000352 TA0CCR0 +00000354 TA0CCR1 +00000356 TA0CCR2 +00000358 TA0CCR3 +0000035a TA0CCR4 +00000342 TA0CCTL0 +00000344 TA0CCTL1 +00000346 TA0CCTL2 +00000348 TA0CCTL3 +0000034a TA0CCTL4 +00000340 TA0CTL +00000360 TA0EX0 +0000036e TA0IV +00000350 TA0R +00000392 TA1CCR0 +00000394 TA1CCR1 +00000396 TA1CCR2 +00000382 TA1CCTL0 +00000384 TA1CCTL1 +00000386 TA1CCTL2 +00000380 TA1CTL +000003a0 TA1EX0 +000003ae TA1IV +00000390 TA1R +000003d2 TB0CCR0 +000003d4 TB0CCR1 +000003d6 TB0CCR2 +000003d8 TB0CCR3 +000003da TB0CCR4 +000003dc TB0CCR5 +000003de TB0CCR6 +000003c2 TB0CCTL0 +000003c4 TB0CCTL1 +000003c6 TB0CCTL2 +000003c8 TB0CCTL3 +000003ca TB0CCTL4 +000003cc TB0CCTL5 +000003ce TB0CCTL6 +000003c0 TB0CTL +000003e0 TB0EX0 +000003ee TB0IV +000003d0 TB0R +000005d0 UCA0ABCTL +000005c6 UCA0BRW +000005c7 UCA0BRW_H +000005c6 UCA0BRW_L +000005c0 UCA0CTLW0 +000005c1 UCA0CTLW0_H +000005c0 UCA0CTLW0_L +000005dc UCA0ICTL +000005dd UCA0ICTL_H +000005dc UCA0ICTL_L +000005d2 UCA0IRCTL +000005d3 UCA0IRCTL_H +000005d2 UCA0IRCTL_L +000005de UCA0IV +000005c8 UCA0MCTL +000005cc UCA0RXBUF +000005ca UCA0STAT +000005ce UCA0TXBUF +00000610 UCA1ABCTL +00000606 UCA1BRW +00000607 UCA1BRW_H +00000606 UCA1BRW_L +00000600 UCA1CTLW0 +00000601 UCA1CTLW0_H +00000600 UCA1CTLW0_L +0000061c UCA1ICTL +0000061d UCA1ICTL_H +0000061c UCA1ICTL_L +00000612 UCA1IRCTL +00000613 UCA1IRCTL_H +00000612 UCA1IRCTL_L +0000061e UCA1IV +00000608 UCA1MCTL +0000060c UCA1RXBUF +0000060a UCA1STAT +0000060e UCA1TXBUF +00000650 UCA2ABCTL +00000646 UCA2BRW +00000647 UCA2BRW_H +00000646 UCA2BRW_L +00000640 UCA2CTLW0 +00000641 UCA2CTLW0_H +00000640 UCA2CTLW0_L +0000065c UCA2ICTL +0000065d UCA2ICTL_H +0000065c UCA2ICTL_L +00000652 UCA2IRCTL +00000653 UCA2IRCTL_H +00000652 UCA2IRCTL_L +0000065e UCA2IV +00000648 UCA2MCTL +0000064c UCA2RXBUF +0000064a UCA2STAT +0000064e UCA2TXBUF +00000690 UCA3ABCTL +00000686 UCA3BRW +00000687 UCA3BRW_H +00000686 UCA3BRW_L +00000680 UCA3CTLW0 +00000681 UCA3CTLW0_H +00000680 UCA3CTLW0_L +0000069c UCA3ICTL +0000069d UCA3ICTL_H +0000069c UCA3ICTL_L +00000692 UCA3IRCTL +00000693 UCA3IRCTL_H +00000692 UCA3IRCTL_L +0000069e UCA3IV +00000688 UCA3MCTL +0000068c UCA3RXBUF +0000068a UCA3STAT +0000068e UCA3TXBUF +000005e6 UCB0BRW +000005e7 UCB0BRW_H +000005e6 UCB0BRW_L +000005e0 UCB0CTLW0 +000005e1 UCB0CTLW0_H +000005e0 UCB0CTLW0_L +000005f0 UCB0I2COA +000005f1 UCB0I2COA_H +000005f0 UCB0I2COA_L +000005f2 UCB0I2CSA +000005f3 UCB0I2CSA_H +000005f2 UCB0I2CSA_L +000005fc UCB0ICTL +000005fd UCB0ICTL_H +000005fc UCB0ICTL_L +000005fe UCB0IV +000005ec UCB0RXBUF +000005ea UCB0STAT +000005ee UCB0TXBUF +00000626 UCB1BRW +00000627 UCB1BRW_H +00000626 UCB1BRW_L +00000620 UCB1CTLW0 +00000621 UCB1CTLW0_H +00000620 UCB1CTLW0_L +00000630 UCB1I2COA +00000631 UCB1I2COA_H +00000630 UCB1I2COA_L +00000632 UCB1I2CSA +00000633 UCB1I2CSA_H +00000632 UCB1I2CSA_L +0000063c UCB1ICTL +0000063d UCB1ICTL_H +0000063c UCB1ICTL_L +0000063e UCB1IV +0000062c UCB1RXBUF +0000062a UCB1STAT +0000062e UCB1TXBUF +00000666 UCB2BRW +00000667 UCB2BRW_H +00000666 UCB2BRW_L +00000660 UCB2CTLW0 +00000661 UCB2CTLW0_H +00000660 UCB2CTLW0_L +00000670 UCB2I2COA +00000671 UCB2I2COA_H +00000670 UCB2I2COA_L +00000672 UCB2I2CSA +00000673 UCB2I2CSA_H +00000672 UCB2I2CSA_L +0000067c UCB2ICTL +0000067d UCB2ICTL_H +0000067c UCB2ICTL_L +0000067e UCB2IV +0000066c UCB2RXBUF +0000066a UCB2STAT +0000066e UCB2TXBUF +000006a6 UCB3BRW +000006a7 UCB3BRW_H +000006a6 UCB3BRW_L +000006a0 UCB3CTLW0 +000006a1 UCB3CTLW0_H +000006a0 UCB3CTLW0_L +000006b0 UCB3I2COA +000006b1 UCB3I2COA_H +000006b0 UCB3I2COA_L +000006b2 UCB3I2CSA +000006b3 UCB3I2CSA_H +000006b2 UCB3I2CSA_L +000006bc UCB3ICTL +000006bd UCB3ICTL_H +000006bc UCB3ICTL_L +000006be UCB3IV +000006ac UCB3RXBUF +000006aa UCB3STAT +000006ae UCB3TXBUF +00000160 UCSCTL0 +00000161 UCSCTL0_H +00000160 UCSCTL0_L +00000162 UCSCTL1 +00000163 UCSCTL1_H +00000162 UCSCTL1_L +00000164 UCSCTL2 +00000165 UCSCTL2_H +00000164 UCSCTL2_L +00000166 UCSCTL3 +00000167 UCSCTL3_H +00000166 UCSCTL3_L +00000168 UCSCTL4 +00000169 UCSCTL4_H +00000168 UCSCTL4_L +0000016a UCSCTL5 +0000016b UCSCTL5_H +0000016a UCSCTL5_L +0000016c UCSCTL6 +0000016d UCSCTL6_H +0000016c UCSCTL6_L +0000016e UCSCTL7 +0000016f UCSCTL7_H +0000016e UCSCTL7_L +00000170 UCSCTL8 +00000171 UCSCTL8_H +00000170 UCSCTL8_L +0000015c WDTCTL +0000015d WDTCTL_H +0000015c WDTCTL_L +00005c00 __STACK_END +000000a0 __STACK_SIZE +UNDEFED __TI_BINIT_Base +UNDEFED __TI_BINIT_Limit +00005c64 __TI_CINIT_Base +00005c6c __TI_CINIT_Limit +00005c5c __TI_Handler_Table_Base +00005c64 __TI_Handler_Table_Limit +UNDEFED __TI_INITARRAY_Base +UNDEFED __TI_INITARRAY_Limit +00005c46 __TI_ISR_TRAP +00010300 __TI_decompress_none +00010318 __TI_decompress_rle24 +0000ffd2 __TI_int41 +0000ffd4 __TI_int42 +0000ffd6 __TI_int43 +0000ffd8 __TI_int44 +0000ffda __TI_int45 +0000ffdc __TI_int46 +0000ffde __TI_int47 +0000ffe0 __TI_int48 +0000ffe2 __TI_int49 +0000ffe4 __TI_int50 +0000ffe6 __TI_int51 +0000ffe8 __TI_int52 +0000ffea __TI_int53 +0000ffec __TI_int54 +0000ffee __TI_int55 +0000fff0 __TI_int56 +0000fff2 __TI_int57 +0000fff4 __TI_int58 +0000fff6 __TI_int59 +0000fff8 __TI_int60 +0000fffa __TI_int61 +0000fffc __TI_int62 +ffffffff __TI_pprof_out_hndl +ffffffff __TI_prof_data_size +ffffffff __TI_prof_data_start +ffffffff __c_args__ +000102d4 __mspabi_mpyi_f5hw +00010000 _auto_init_hold_wdt +00005c2c _c_int00_noargs_noexit +0000fffe _reset_vector +00005b60 _stack +00010322 _system_post_cinit +0001031e _system_pre_init +00010312 abort +00001c05 ac_charge_mode +00001c04 can_full +00001c01 cancomm_flag +00001c07 charge_mode +0001026c clock_init +000100ea copy_in +00001c06 dc_charge_mode +00010150 main +000102ec memcpy +00001c03 rcv_can +00001c02 send_can +00001c00 status_flag +000102ba timerB_init +00005c00 timer_b0 GLOBAL SYMBOLS: SORTED BY Symbol Address -address name -------- ---- -000000a0 __STACK_SIZE -00000100 SFRIE1 -00000100 SFRIE1_L -00000101 SFRIE1_H -00000102 SFRIFG1 -00000102 SFRIFG1_L -00000103 SFRIFG1_H -00000104 SFRRPCR -00000104 SFRRPCR_L -00000105 SFRRPCR_H -00000120 PMMCTL0 -00000120 PMMCTL0_L -00000121 PMMCTL0_H -00000122 PMMCTL1 -00000122 PMMCTL1_L -00000123 PMMCTL1_H -00000124 SVSMHCTL -00000124 SVSMHCTL_L -00000125 SVSMHCTL_H -00000126 SVSMLCTL -00000126 SVSMLCTL_L -00000127 SVSMLCTL_H -00000128 SVSMIO -00000128 SVSMIO_L -00000129 SVSMIO_H -0000012c PMMIFG -0000012c PMMIFG_L -0000012d PMMIFG_H -0000012e PMMRIE -0000012e PMMRIE_L -0000012f PMMRIE_H -00000130 PM5CTL0 -00000130 PM5CTL0_L -00000131 PM5CTL0_H -00000140 FCTL1 -00000140 FCTL1_L -00000141 FCTL1_H -00000144 FCTL3 -00000144 FCTL3_L -00000145 FCTL3_H -00000146 FCTL4 -00000146 FCTL4_L -00000147 FCTL4_H -00000150 CRCDI -00000150 CRCDI_L -00000151 CRCDI_H -00000152 CRCDIRB -00000152 CRCDIRB_L -00000153 CRCDIRB_H -00000154 CRCINIRES -00000154 CRCINIRES_L -00000155 CRCINIRES_H -00000156 CRCRESR -00000156 CRCRESR_L -00000157 CRCRESR_H -00000158 RCCTL0 -00000158 RCCTL0_L -00000159 RCCTL0_H -0000015c WDTCTL -0000015c WDTCTL_L -0000015d WDTCTL_H -00000160 UCSCTL0 -00000160 UCSCTL0_L -00000161 UCSCTL0_H -00000162 UCSCTL1 -00000162 UCSCTL1_L -00000163 UCSCTL1_H -00000164 UCSCTL2 -00000164 UCSCTL2_L -00000165 UCSCTL2_H -00000166 UCSCTL3 -00000166 UCSCTL3_L -00000167 UCSCTL3_H -00000168 UCSCTL4 -00000168 UCSCTL4_L -00000169 UCSCTL4_H -0000016a UCSCTL5 -0000016a UCSCTL5_L -0000016b UCSCTL5_H -0000016c UCSCTL6 -0000016c UCSCTL6_L -0000016d UCSCTL6_H -0000016e UCSCTL7 -0000016e UCSCTL7_L -0000016f UCSCTL7_H -00000170 UCSCTL8 -00000170 UCSCTL8_L -00000171 UCSCTL8_H -00000180 SYSCTL -00000180 SYSCTL_L -00000181 SYSCTL_H -00000182 SYSBSLC -00000182 SYSBSLC_L -00000183 SYSBSLC_H -00000186 SYSJMBC -00000186 SYSJMBC_L -00000187 SYSJMBC_H -00000188 SYSJMBI0 -00000188 SYSJMBI0_L -00000189 SYSJMBI0_H -0000018a SYSJMBI1 -0000018a SYSJMBI1_L -0000018b SYSJMBI1_H -0000018c SYSJMBO0 -0000018c SYSJMBO0_L -0000018d SYSJMBO0_H -0000018e SYSJMBO1 -0000018e SYSJMBO1_L -0000018f SYSJMBO1_H -00000198 SYSBERRIV -00000198 SYSBERRIV_L -00000199 SYSBERRIV_H -0000019a SYSUNIV -0000019a SYSUNIV_L -0000019b SYSUNIV_H -0000019c SYSSNIV -0000019c SYSSNIV_L -0000019d SYSSNIV_H -0000019e SYSRSTIV -0000019e SYSRSTIV_L -0000019f SYSRSTIV_H -000001b0 REFCTL0 -000001b0 REFCTL0_L -000001b1 REFCTL0_H -00000200 PAIN -00000200 PAIN_L -00000201 PAIN_H -00000202 PAOUT -00000202 PAOUT_L -00000203 PAOUT_H -00000204 PADIR -00000204 PADIR_L -00000205 PADIR_H -00000206 PAREN -00000206 PAREN_L -00000207 PAREN_H -00000208 PADS -00000208 PADS_L -00000209 PADS_H -0000020a PASEL -0000020a PASEL_L -0000020b PASEL_H -0000020e P1IV -00000218 PAIES -00000218 PAIES_L -00000219 PAIES_H -0000021a PAIE -0000021a PAIE_L -0000021b PAIE_H -0000021c PAIFG -0000021c PAIFG_L -0000021d PAIFG_H -0000021e P2IV -00000220 PBIN -00000220 PBIN_L -00000221 PBIN_H -00000222 PBOUT -00000222 PBOUT_L -00000223 PBOUT_H -00000224 PBDIR -00000224 PBDIR_L -00000225 PBDIR_H -00000226 PBREN -00000226 PBREN_L -00000227 PBREN_H -00000228 PBDS -00000228 PBDS_L -00000229 PBDS_H -0000022a PBSEL -0000022a PBSEL_L -0000022b PBSEL_H -00000240 PCIN -00000240 PCIN_L -00000241 PCIN_H -00000242 PCOUT -00000242 PCOUT_L -00000243 PCOUT_H -00000244 PCDIR -00000244 PCDIR_L -00000245 PCDIR_H -00000246 PCREN -00000246 PCREN_L -00000247 PCREN_H -00000248 PCDS -00000248 PCDS_L -00000249 PCDS_H -0000024a PCSEL -0000024a PCSEL_L -0000024b PCSEL_H -00000260 PDIN -00000260 PDIN_L -00000261 PDIN_H -00000262 PDOUT -00000262 PDOUT_L -00000263 PDOUT_H -00000264 PDDIR -00000264 PDDIR_L -00000265 PDDIR_H -00000266 PDREN -00000266 PDREN_L -00000267 PDREN_H -00000268 PDDS -00000268 PDDS_L -00000269 PDDS_H -0000026a PDSEL -0000026a PDSEL_L -0000026b PDSEL_H -00000280 PEIN -00000280 PEIN_L -00000281 PEIN_H -00000282 PEOUT -00000282 PEOUT_L -00000283 PEOUT_H -00000284 PEDIR -00000284 PEDIR_L -00000285 PEDIR_H -00000286 PEREN -00000286 PEREN_L -00000287 PEREN_H -00000288 PEDS -00000288 PEDS_L -00000289 PEDS_H -0000028a PESEL -0000028a PESEL_L -0000028b PESEL_H -000002a0 PFIN -000002a0 PFIN_L -000002a1 PFIN_H -000002a2 PFOUT -000002a2 PFOUT_L -000002a3 PFOUT_H -000002a4 PFDIR -000002a4 PFDIR_L -000002a5 PFDIR_H -000002a6 PFREN -000002a6 PFREN_L -000002a7 PFREN_H -000002a8 PFDS -000002a8 PFDS_L -000002a9 PFDS_H -000002aa PFSEL -000002aa PFSEL_L -000002ab PFSEL_H -00000320 PJIN -00000320 PJIN_L -00000321 PJIN_H -00000322 PJOUT -00000322 PJOUT_L -00000323 PJOUT_H -00000324 PJDIR -00000324 PJDIR_L -00000325 PJDIR_H -00000326 PJREN -00000326 PJREN_L -00000327 PJREN_H -00000328 PJDS -00000328 PJDS_L -00000329 PJDS_H -00000340 TA0CTL -00000342 TA0CCTL0 -00000344 TA0CCTL1 -00000346 TA0CCTL2 -00000348 TA0CCTL3 -0000034a TA0CCTL4 -00000350 TA0R -00000352 TA0CCR0 -00000354 TA0CCR1 -00000356 TA0CCR2 -00000358 TA0CCR3 -0000035a TA0CCR4 -00000360 TA0EX0 -0000036e TA0IV -00000380 TA1CTL -00000382 TA1CCTL0 -00000384 TA1CCTL1 -00000386 TA1CCTL2 -00000390 TA1R -00000392 TA1CCR0 -00000394 TA1CCR1 -00000396 TA1CCR2 -000003a0 TA1EX0 -000003ae TA1IV -000003c0 TB0CTL -000003c2 TB0CCTL0 -000003c4 TB0CCTL1 -000003c6 TB0CCTL2 -000003c8 TB0CCTL3 -000003ca TB0CCTL4 -000003cc TB0CCTL5 -000003ce TB0CCTL6 -000003d0 TB0R -000003d2 TB0CCR0 -000003d4 TB0CCR1 -000003d6 TB0CCR2 -000003d8 TB0CCR3 -000003da TB0CCR4 -000003dc TB0CCR5 -000003de TB0CCR6 -000003e0 TB0EX0 -000003ee TB0IV -000004a0 RTCCTL01 -000004a0 RTCCTL01_L -000004a1 RTCCTL01_H -000004a2 RTCCTL23 -000004a2 RTCCTL23_L -000004a3 RTCCTL23_H -000004a8 RTCPS0CTL -000004a8 RTCPS0CTL_L -000004a9 RTCPS0CTL_H -000004aa RTCPS1CTL -000004aa RTCPS1CTL_L -000004ab RTCPS1CTL_H -000004ac RTCPS -000004ac RTCPS_L -000004ad RTCPS_H -000004ae RTCIV -000004b0 RTCTIM0 -000004b0 RTCTIM0_L -000004b1 RTCTIM0_H -000004b2 RTCTIM1 -000004b2 RTCTIM1_L -000004b3 RTCTIM1_H -000004b4 RTCDATE -000004b4 RTCDATE_L -000004b5 RTCDATE_H -000004b6 RTCYEAR -000004b6 RTCYEAR_L -000004b7 RTCYEAR_H -000004b8 RTCAMINHR -000004b8 RTCAMINHR_L -000004b9 RTCAMINHR_H -000004ba RTCADOWDAY -000004ba RTCADOWDAY_L -000004bb RTCADOWDAY_H -000004c0 MPY -000004c0 MPY_L -000004c1 MPY_H -000004c2 MPYS -000004c2 MPYS_L -000004c3 MPYS_H -000004c4 MAC -000004c4 MAC_L -000004c5 MAC_H -000004c6 MACS -000004c6 MACS_L -000004c7 MACS_H -000004c8 OP2 -000004c8 OP2_L -000004c9 OP2_H -000004ca RESLO -000004ca RESLO_L -000004cb RESLO_H -000004cc RESHI -000004cc RESHI_L -000004cd RESHI_H -000004ce SUMEXT -000004ce SUMEXT_L -000004cf SUMEXT_H -000004d0 MPY32L -000004d0 MPY32L_L -000004d1 MPY32L_H -000004d2 MPY32H -000004d2 MPY32H_L -000004d3 MPY32H_H -000004d4 MPYS32L -000004d4 MPYS32L_L -000004d5 MPYS32L_H -000004d6 MPYS32H -000004d6 MPYS32H_L -000004d7 MPYS32H_H -000004d8 MAC32L -000004d8 MAC32L_L -000004d9 MAC32L_H -000004da MAC32H -000004da MAC32H_L -000004db MAC32H_H -000004dc MACS32L -000004dc MACS32L_L -000004dd MACS32L_H -000004de MACS32H -000004de MACS32H_L -000004df MACS32H_H -000004e0 OP2L -000004e0 OP2L_L -000004e1 OP2L_H -000004e2 OP2H -000004e2 OP2H_L -000004e3 OP2H_H -000004e4 RES0 -000004e4 RES0_L -000004e5 RES0_H -000004e6 RES1 -000004e6 RES1_L -000004e7 RES1_H -000004e8 RES2 -000004e8 RES2_L -000004e9 RES2_H -000004ea RES3 -000004ea RES3_L -000004eb RES3_H -000004ec MPY32CTL0 -000004ec MPY32CTL0_L -000004ed MPY32CTL0_H -00000500 DMACTL0 -00000502 DMACTL1 -00000504 DMACTL2 -00000506 DMACTL3 -00000508 DMACTL4 -0000050e DMAIV -00000510 DMA0CTL -00000512 DMA0SA -00000512 DMA0SAL -00000514 DMA0SAH -00000516 DMA0DA -00000516 DMA0DAL -00000518 DMA0DAH -0000051a DMA0SZ -00000520 DMA1CTL -00000522 DMA1SA -00000522 DMA1SAL -00000524 DMA1SAH -00000526 DMA1DA -00000526 DMA1DAL -00000528 DMA1DAH -0000052a DMA1SZ -00000530 DMA2CTL -00000532 DMA2SA -00000532 DMA2SAL -00000534 DMA2SAH -00000536 DMA2DA -00000536 DMA2DAL -00000538 DMA2DAH -0000053a DMA2SZ -000005c0 UCA0CTLW0 -000005c0 UCA0CTLW0_L -000005c1 UCA0CTLW0_H -000005c6 UCA0BRW -000005c6 UCA0BRW_L -000005c7 UCA0BRW_H -000005c8 UCA0MCTL -000005ca UCA0STAT -000005cc UCA0RXBUF -000005ce UCA0TXBUF -000005d0 UCA0ABCTL -000005d2 UCA0IRCTL -000005d2 UCA0IRCTL_L -000005d3 UCA0IRCTL_H -000005dc UCA0ICTL -000005dc UCA0ICTL_L -000005dd UCA0ICTL_H -000005de UCA0IV -000005e0 UCB0CTLW0 -000005e0 UCB0CTLW0_L -000005e1 UCB0CTLW0_H -000005e6 UCB0BRW -000005e6 UCB0BRW_L -000005e7 UCB0BRW_H -000005ea UCB0STAT -000005ec UCB0RXBUF -000005ee UCB0TXBUF -000005f0 UCB0I2COA -000005f0 UCB0I2COA_L -000005f1 UCB0I2COA_H -000005f2 UCB0I2CSA -000005f2 UCB0I2CSA_L -000005f3 UCB0I2CSA_H -000005fc UCB0ICTL -000005fc UCB0ICTL_L -000005fd UCB0ICTL_H -000005fe UCB0IV -00000600 UCA1CTLW0 -00000600 UCA1CTLW0_L -00000601 UCA1CTLW0_H -00000606 UCA1BRW -00000606 UCA1BRW_L -00000607 UCA1BRW_H -00000608 UCA1MCTL -0000060a UCA1STAT -0000060c UCA1RXBUF -0000060e UCA1TXBUF -00000610 UCA1ABCTL -00000612 UCA1IRCTL -00000612 UCA1IRCTL_L -00000613 UCA1IRCTL_H -0000061c UCA1ICTL -0000061c UCA1ICTL_L -0000061d UCA1ICTL_H -0000061e UCA1IV -00000620 UCB1CTLW0 -00000620 UCB1CTLW0_L -00000621 UCB1CTLW0_H -00000626 UCB1BRW -00000626 UCB1BRW_L -00000627 UCB1BRW_H -0000062a UCB1STAT -0000062c UCB1RXBUF -0000062e UCB1TXBUF -00000630 UCB1I2COA -00000630 UCB1I2COA_L -00000631 UCB1I2COA_H -00000632 UCB1I2CSA -00000632 UCB1I2CSA_L -00000633 UCB1I2CSA_H -0000063c UCB1ICTL -0000063c UCB1ICTL_L -0000063d UCB1ICTL_H -0000063e UCB1IV -00000640 UCA2CTLW0 -00000640 UCA2CTLW0_L -00000641 UCA2CTLW0_H -00000646 UCA2BRW -00000646 UCA2BRW_L -00000647 UCA2BRW_H -00000648 UCA2MCTL -0000064a UCA2STAT -0000064c UCA2RXBUF -0000064e UCA2TXBUF -00000650 UCA2ABCTL -00000652 UCA2IRCTL -00000652 UCA2IRCTL_L -00000653 UCA2IRCTL_H -0000065c UCA2ICTL -0000065c UCA2ICTL_L -0000065d UCA2ICTL_H -0000065e UCA2IV -00000660 UCB2CTLW0 -00000660 UCB2CTLW0_L -00000661 UCB2CTLW0_H -00000666 UCB2BRW -00000666 UCB2BRW_L -00000667 UCB2BRW_H -0000066a UCB2STAT -0000066c UCB2RXBUF -0000066e UCB2TXBUF -00000670 UCB2I2COA -00000670 UCB2I2COA_L -00000671 UCB2I2COA_H -00000672 UCB2I2CSA -00000672 UCB2I2CSA_L -00000673 UCB2I2CSA_H -0000067c UCB2ICTL -0000067c UCB2ICTL_L -0000067d UCB2ICTL_H -0000067e UCB2IV -00000680 UCA3CTLW0 -00000680 UCA3CTLW0_L -00000681 UCA3CTLW0_H -00000686 UCA3BRW -00000686 UCA3BRW_L -00000687 UCA3BRW_H -00000688 UCA3MCTL -0000068a UCA3STAT -0000068c UCA3RXBUF -0000068e UCA3TXBUF -00000690 UCA3ABCTL -00000692 UCA3IRCTL -00000692 UCA3IRCTL_L -00000693 UCA3IRCTL_H -0000069c UCA3ICTL -0000069c UCA3ICTL_L -0000069d UCA3ICTL_H -0000069e UCA3IV -000006a0 UCB3CTLW0 -000006a0 UCB3CTLW0_L -000006a1 UCB3CTLW0_H -000006a6 UCB3BRW -000006a6 UCB3BRW_L -000006a7 UCB3BRW_H -000006aa UCB3STAT -000006ac UCB3RXBUF -000006ae UCB3TXBUF -000006b0 UCB3I2COA -000006b0 UCB3I2COA_L -000006b1 UCB3I2COA_H -000006b2 UCB3I2CSA -000006b2 UCB3I2CSA_L -000006b3 UCB3I2CSA_H -000006bc UCB3ICTL -000006bc UCB3ICTL_L -000006bd UCB3ICTL_H -000006be UCB3IV -00000700 ADC12CTL0 -00000700 ADC12CTL0_L -00000701 ADC12CTL0_H -00000702 ADC12CTL1 -00000702 ADC12CTL1_L -00000703 ADC12CTL1_H -00000704 ADC12CTL2 -00000704 ADC12CTL2_L -00000705 ADC12CTL2_H -0000070a ADC12IFG -0000070a ADC12IFG_L -0000070b ADC12IFG_H -0000070c ADC12IE -0000070c ADC12IE_L -0000070d ADC12IE_H -0000070e ADC12IV -0000070e ADC12IV_L -0000070f ADC12IV_H -00000710 ADC12MCTL0 -00000711 ADC12MCTL1 -00000712 ADC12MCTL2 -00000713 ADC12MCTL3 -00000714 ADC12MCTL4 -00000715 ADC12MCTL5 -00000716 ADC12MCTL6 -00000717 ADC12MCTL7 -00000718 ADC12MCTL8 -00000719 ADC12MCTL9 -0000071a ADC12MCTL10 -0000071b ADC12MCTL11 -0000071c ADC12MCTL12 -0000071d ADC12MCTL13 -0000071e ADC12MCTL14 -0000071f ADC12MCTL15 -00000720 ADC12MEM0 -00000720 ADC12MEM0_L -00000721 ADC12MEM0_H -00000722 ADC12MEM1 -00000722 ADC12MEM1_L -00000723 ADC12MEM1_H -00000724 ADC12MEM2 -00000724 ADC12MEM2_L -00000725 ADC12MEM2_H -00000726 ADC12MEM3 -00000726 ADC12MEM3_L -00000727 ADC12MEM3_H -00000728 ADC12MEM4 -00000728 ADC12MEM4_L -00000729 ADC12MEM4_H -0000072a ADC12MEM5 -0000072a ADC12MEM5_L -0000072b ADC12MEM5_H -0000072c ADC12MEM6 -0000072c ADC12MEM6_L -0000072d ADC12MEM6_H -0000072e ADC12MEM7 -0000072e ADC12MEM7_L -0000072f ADC12MEM7_H -00000730 ADC12MEM8 -00000730 ADC12MEM8_L -00000731 ADC12MEM8_H -00000732 ADC12MEM9 -00000732 ADC12MEM9_L -00000733 ADC12MEM9_H -00000734 ADC12MEM10 -00000734 ADC12MEM10_L -00000735 ADC12MEM10_H -00000736 ADC12MEM11 -00000736 ADC12MEM11_L -00000737 ADC12MEM11_H -00000738 ADC12MEM12 -00000738 ADC12MEM12_L -00000739 ADC12MEM12_H -0000073a ADC12MEM13 -0000073a ADC12MEM13_L -0000073b ADC12MEM13_H -0000073c ADC12MEM14 -0000073c ADC12MEM14_L -0000073d ADC12MEM14_H -0000073e ADC12MEM15 -0000073e ADC12MEM15_L -0000073f ADC12MEM15_H -00001c00 status_flag -00001c01 cancomm_flag -00001c02 send_can -00001c03 rcv_can -00001c04 can_full -00001c05 ac_charge_mode -00001c06 dc_charge_mode -00001c07 charge_mode -00005b60 _stack -00005c00 __STACK_END -00005c00 timer_b0 -00005c2c _c_int00_noargs -00005c48 __TI_ISR_TRAP -00005c5c __TI_Handler_Table_Base -00005c64 __TI_CINIT_Base -00005c64 __TI_Handler_Table_Limit -00005c6c __TI_CINIT_Limit -0000ffd2 __TI_int41 -0000ffd4 __TI_int42 -0000ffd6 __TI_int43 -0000ffd8 __TI_int44 -0000ffda __TI_int45 -0000ffdc __TI_int46 -0000ffde __TI_int47 -0000ffe0 __TI_int48 -0000ffe2 __TI_int49 -0000ffe4 __TI_int50 -0000ffe6 __TI_int51 -0000ffe8 __TI_int52 -0000ffea __TI_int53 -0000ffec __TI_int54 -0000ffee __TI_int55 -0000fff0 __TI_int56 -0000fff2 __TI_int57 -0000fff4 __TI_int58 -0000fff6 __TI_int59 -0000fff8 __TI_int60 -0000fffa __TI_int61 -0000fffc __TI_int62 -0000fffe _reset_vector -00010000 __TI_decompress_lzss -00010076 main -000100d2 SetVCoreUp -00010126 __TI_auto_init_nobinit_nopinit_hold_wdt -0001017a Clock_XT2_Init -000101b4 Clock_XT1_Init -000101e6 clock_init -0001020e Port_Init -00010234 timerB_init -0001024e memcpy -00010262 __TI_decompress_none -00010274 C$$EXIT -00010274 abort -0001027a _system_pre_init -0001027e _system_post_cinit -ffffffff __TI_pprof_out_hndl -ffffffff __TI_prof_data_size -ffffffff __TI_prof_data_start -ffffffff __c_args__ +address name +------- ---- +000000a0 __STACK_SIZE +00000100 SFRIE1 +00000100 SFRIE1_L +00000101 SFRIE1_H +00000102 SFRIFG1 +00000102 SFRIFG1_L +00000103 SFRIFG1_H +00000104 SFRRPCR +00000104 SFRRPCR_L +00000105 SFRRPCR_H +00000120 PMMCTL0 +00000120 PMMCTL0_L +00000121 PMMCTL0_H +00000122 PMMCTL1 +00000122 PMMCTL1_L +00000123 PMMCTL1_H +00000124 SVSMHCTL +00000124 SVSMHCTL_L +00000125 SVSMHCTL_H +00000126 SVSMLCTL +00000126 SVSMLCTL_L +00000127 SVSMLCTL_H +00000128 SVSMIO +00000128 SVSMIO_L +00000129 SVSMIO_H +0000012c PMMIFG +0000012c PMMIFG_L +0000012d PMMIFG_H +0000012e PMMRIE +0000012e PMMRIE_L +0000012f PMMRIE_H +00000130 PM5CTL0 +00000130 PM5CTL0_L +00000131 PM5CTL0_H +00000140 FCTL1 +00000140 FCTL1_L +00000141 FCTL1_H +00000144 FCTL3 +00000144 FCTL3_L +00000145 FCTL3_H +00000146 FCTL4 +00000146 FCTL4_L +00000147 FCTL4_H +00000150 CRCDI +00000150 CRCDI_L +00000151 CRCDI_H +00000152 CRCDIRB +00000152 CRCDIRB_L +00000153 CRCDIRB_H +00000154 CRCINIRES +00000154 CRCINIRES_L +00000155 CRCINIRES_H +00000156 CRCRESR +00000156 CRCRESR_L +00000157 CRCRESR_H +00000158 RCCTL0 +00000158 RCCTL0_L +00000159 RCCTL0_H +0000015c WDTCTL +0000015c WDTCTL_L +0000015d WDTCTL_H +00000160 UCSCTL0 +00000160 UCSCTL0_L +00000161 UCSCTL0_H +00000162 UCSCTL1 +00000162 UCSCTL1_L +00000163 UCSCTL1_H +00000164 UCSCTL2 +00000164 UCSCTL2_L +00000165 UCSCTL2_H +00000166 UCSCTL3 +00000166 UCSCTL3_L +00000167 UCSCTL3_H +00000168 UCSCTL4 +00000168 UCSCTL4_L +00000169 UCSCTL4_H +0000016a UCSCTL5 +0000016a UCSCTL5_L +0000016b UCSCTL5_H +0000016c UCSCTL6 +0000016c UCSCTL6_L +0000016d UCSCTL6_H +0000016e UCSCTL7 +0000016e UCSCTL7_L +0000016f UCSCTL7_H +00000170 UCSCTL8 +00000170 UCSCTL8_L +00000171 UCSCTL8_H +00000180 SYSCTL +00000180 SYSCTL_L +00000181 SYSCTL_H +00000182 SYSBSLC +00000182 SYSBSLC_L +00000183 SYSBSLC_H +00000186 SYSJMBC +00000186 SYSJMBC_L +00000187 SYSJMBC_H +00000188 SYSJMBI0 +00000188 SYSJMBI0_L +00000189 SYSJMBI0_H +0000018a SYSJMBI1 +0000018a SYSJMBI1_L +0000018b SYSJMBI1_H +0000018c SYSJMBO0 +0000018c SYSJMBO0_L +0000018d SYSJMBO0_H +0000018e SYSJMBO1 +0000018e SYSJMBO1_L +0000018f SYSJMBO1_H +00000198 SYSBERRIV +00000198 SYSBERRIV_L +00000199 SYSBERRIV_H +0000019a SYSUNIV +0000019a SYSUNIV_L +0000019b SYSUNIV_H +0000019c SYSSNIV +0000019c SYSSNIV_L +0000019d SYSSNIV_H +0000019e SYSRSTIV +0000019e SYSRSTIV_L +0000019f SYSRSTIV_H +000001b0 REFCTL0 +000001b0 REFCTL0_L +000001b1 REFCTL0_H +00000200 PAIN +00000200 PAIN_L +00000201 PAIN_H +00000202 PAOUT +00000202 PAOUT_L +00000203 PAOUT_H +00000204 PADIR +00000204 PADIR_L +00000205 PADIR_H +00000206 PAREN +00000206 PAREN_L +00000207 PAREN_H +00000208 PADS +00000208 PADS_L +00000209 PADS_H +0000020a PASEL +0000020a PASEL_L +0000020b PASEL_H +0000020e P1IV +00000218 PAIES +00000218 PAIES_L +00000219 PAIES_H +0000021a PAIE +0000021a PAIE_L +0000021b PAIE_H +0000021c PAIFG +0000021c PAIFG_L +0000021d PAIFG_H +0000021e P2IV +00000220 PBIN +00000220 PBIN_L +00000221 PBIN_H +00000222 PBOUT +00000222 PBOUT_L +00000223 PBOUT_H +00000224 PBDIR +00000224 PBDIR_L +00000225 PBDIR_H +00000226 PBREN +00000226 PBREN_L +00000227 PBREN_H +00000228 PBDS +00000228 PBDS_L +00000229 PBDS_H +0000022a PBSEL +0000022a PBSEL_L +0000022b PBSEL_H +00000240 PCIN +00000240 PCIN_L +00000241 PCIN_H +00000242 PCOUT +00000242 PCOUT_L +00000243 PCOUT_H +00000244 PCDIR +00000244 PCDIR_L +00000245 PCDIR_H +00000246 PCREN +00000246 PCREN_L +00000247 PCREN_H +00000248 PCDS +00000248 PCDS_L +00000249 PCDS_H +0000024a PCSEL +0000024a PCSEL_L +0000024b PCSEL_H +00000260 PDIN +00000260 PDIN_L +00000261 PDIN_H +00000262 PDOUT +00000262 PDOUT_L +00000263 PDOUT_H +00000264 PDDIR +00000264 PDDIR_L +00000265 PDDIR_H +00000266 PDREN +00000266 PDREN_L +00000267 PDREN_H +00000268 PDDS +00000268 PDDS_L +00000269 PDDS_H +0000026a PDSEL +0000026a PDSEL_L +0000026b PDSEL_H +00000280 PEIN +00000280 PEIN_L +00000281 PEIN_H +00000282 PEOUT +00000282 PEOUT_L +00000283 PEOUT_H +00000284 PEDIR +00000284 PEDIR_L +00000285 PEDIR_H +00000286 PEREN +00000286 PEREN_L +00000287 PEREN_H +00000288 PEDS +00000288 PEDS_L +00000289 PEDS_H +0000028a PESEL +0000028a PESEL_L +0000028b PESEL_H +000002a0 PFIN +000002a0 PFIN_L +000002a1 PFIN_H +000002a2 PFOUT +000002a2 PFOUT_L +000002a3 PFOUT_H +000002a4 PFDIR +000002a4 PFDIR_L +000002a5 PFDIR_H +000002a6 PFREN +000002a6 PFREN_L +000002a7 PFREN_H +000002a8 PFDS +000002a8 PFDS_L +000002a9 PFDS_H +000002aa PFSEL +000002aa PFSEL_L +000002ab PFSEL_H +00000320 PJIN +00000320 PJIN_L +00000321 PJIN_H +00000322 PJOUT +00000322 PJOUT_L +00000323 PJOUT_H +00000324 PJDIR +00000324 PJDIR_L +00000325 PJDIR_H +00000326 PJREN +00000326 PJREN_L +00000327 PJREN_H +00000328 PJDS +00000328 PJDS_L +00000329 PJDS_H +00000340 TA0CTL +00000342 TA0CCTL0 +00000344 TA0CCTL1 +00000346 TA0CCTL2 +00000348 TA0CCTL3 +0000034a TA0CCTL4 +00000350 TA0R +00000352 TA0CCR0 +00000354 TA0CCR1 +00000356 TA0CCR2 +00000358 TA0CCR3 +0000035a TA0CCR4 +00000360 TA0EX0 +0000036e TA0IV +00000380 TA1CTL +00000382 TA1CCTL0 +00000384 TA1CCTL1 +00000386 TA1CCTL2 +00000390 TA1R +00000392 TA1CCR0 +00000394 TA1CCR1 +00000396 TA1CCR2 +000003a0 TA1EX0 +000003ae TA1IV +000003c0 TB0CTL +000003c2 TB0CCTL0 +000003c4 TB0CCTL1 +000003c6 TB0CCTL2 +000003c8 TB0CCTL3 +000003ca TB0CCTL4 +000003cc TB0CCTL5 +000003ce TB0CCTL6 +000003d0 TB0R +000003d2 TB0CCR0 +000003d4 TB0CCR1 +000003d6 TB0CCR2 +000003d8 TB0CCR3 +000003da TB0CCR4 +000003dc TB0CCR5 +000003de TB0CCR6 +000003e0 TB0EX0 +000003ee TB0IV +000004a0 RTCCTL01 +000004a0 RTCCTL01_L +000004a1 RTCCTL01_H +000004a2 RTCCTL23 +000004a2 RTCCTL23_L +000004a3 RTCCTL23_H +000004a8 RTCPS0CTL +000004a8 RTCPS0CTL_L +000004a9 RTCPS0CTL_H +000004aa RTCPS1CTL +000004aa RTCPS1CTL_L +000004ab RTCPS1CTL_H +000004ac RTCPS +000004ac RTCPS_L +000004ad RTCPS_H +000004ae RTCIV +000004b0 RTCTIM0 +000004b0 RTCTIM0_L +000004b1 RTCTIM0_H +000004b2 RTCTIM1 +000004b2 RTCTIM1_L +000004b3 RTCTIM1_H +000004b4 RTCDATE +000004b4 RTCDATE_L +000004b5 RTCDATE_H +000004b6 RTCYEAR +000004b6 RTCYEAR_L +000004b7 RTCYEAR_H +000004b8 RTCAMINHR +000004b8 RTCAMINHR_L +000004b9 RTCAMINHR_H +000004ba RTCADOWDAY +000004ba RTCADOWDAY_L +000004bb RTCADOWDAY_H +000004c0 MPY +000004c0 MPY_L +000004c1 MPY_H +000004c2 MPYS +000004c2 MPYS_L +000004c3 MPYS_H +000004c4 MAC +000004c4 MAC_L +000004c5 MAC_H +000004c6 MACS +000004c6 MACS_L +000004c7 MACS_H +000004c8 OP2 +000004c8 OP2_L +000004c9 OP2_H +000004ca RESLO +000004ca RESLO_L +000004cb RESLO_H +000004cc RESHI +000004cc RESHI_L +000004cd RESHI_H +000004ce SUMEXT +000004ce SUMEXT_L +000004cf SUMEXT_H +000004d0 MPY32L +000004d0 MPY32L_L +000004d1 MPY32L_H +000004d2 MPY32H +000004d2 MPY32H_L +000004d3 MPY32H_H +000004d4 MPYS32L +000004d4 MPYS32L_L +000004d5 MPYS32L_H +000004d6 MPYS32H +000004d6 MPYS32H_L +000004d7 MPYS32H_H +000004d8 MAC32L +000004d8 MAC32L_L +000004d9 MAC32L_H +000004da MAC32H +000004da MAC32H_L +000004db MAC32H_H +000004dc MACS32L +000004dc MACS32L_L +000004dd MACS32L_H +000004de MACS32H +000004de MACS32H_L +000004df MACS32H_H +000004e0 OP2L +000004e0 OP2L_L +000004e1 OP2L_H +000004e2 OP2H +000004e2 OP2H_L +000004e3 OP2H_H +000004e4 RES0 +000004e4 RES0_L +000004e5 RES0_H +000004e6 RES1 +000004e6 RES1_L +000004e7 RES1_H +000004e8 RES2 +000004e8 RES2_L +000004e9 RES2_H +000004ea RES3 +000004ea RES3_L +000004eb RES3_H +000004ec MPY32CTL0 +000004ec MPY32CTL0_L +000004ed MPY32CTL0_H +00000500 DMACTL0 +00000500 DMACTL0_L +00000501 DMACTL0_H +00000502 DMACTL1 +00000502 DMACTL1_L +00000503 DMACTL1_H +00000504 DMACTL2 +00000504 DMACTL2_L +00000505 DMACTL2_H +00000506 DMACTL3 +00000506 DMACTL3_L +00000507 DMACTL3_H +00000508 DMACTL4 +00000508 DMACTL4_L +00000509 DMACTL4_H +0000050e DMAIV +0000050e DMAIV_L +0000050f DMAIV_H +00000510 DMA0CTL +00000510 DMA0CTL_L +00000511 DMA0CTL_H +00000512 DMA0SA +00000512 DMA0SAL +00000514 DMA0SAH +00000516 DMA0DA +00000516 DMA0DAL +00000518 DMA0DAH +0000051a DMA0SZ +00000520 DMA1CTL +00000520 DMA1CTL_L +00000521 DMA1CTL_H +00000522 DMA1SA +00000522 DMA1SAL +00000524 DMA1SAH +00000526 DMA1DA +00000526 DMA1DAL +00000528 DMA1DAH +0000052a DMA1SZ +00000530 DMA2CTL +00000530 DMA2CTL_L +00000531 DMA2CTL_H +00000532 DMA2SA +00000532 DMA2SAL +00000534 DMA2SAH +00000536 DMA2DA +00000536 DMA2DAL +00000538 DMA2DAH +0000053a DMA2SZ +000005c0 UCA0CTLW0 +000005c0 UCA0CTLW0_L +000005c1 UCA0CTLW0_H +000005c6 UCA0BRW +000005c6 UCA0BRW_L +000005c7 UCA0BRW_H +000005c8 UCA0MCTL +000005ca UCA0STAT +000005cc UCA0RXBUF +000005ce UCA0TXBUF +000005d0 UCA0ABCTL +000005d2 UCA0IRCTL +000005d2 UCA0IRCTL_L +000005d3 UCA0IRCTL_H +000005dc UCA0ICTL +000005dc UCA0ICTL_L +000005dd UCA0ICTL_H +000005de UCA0IV +000005e0 UCB0CTLW0 +000005e0 UCB0CTLW0_L +000005e1 UCB0CTLW0_H +000005e6 UCB0BRW +000005e6 UCB0BRW_L +000005e7 UCB0BRW_H +000005ea UCB0STAT +000005ec UCB0RXBUF +000005ee UCB0TXBUF +000005f0 UCB0I2COA +000005f0 UCB0I2COA_L +000005f1 UCB0I2COA_H +000005f2 UCB0I2CSA +000005f2 UCB0I2CSA_L +000005f3 UCB0I2CSA_H +000005fc UCB0ICTL +000005fc UCB0ICTL_L +000005fd UCB0ICTL_H +000005fe UCB0IV +00000600 UCA1CTLW0 +00000600 UCA1CTLW0_L +00000601 UCA1CTLW0_H +00000606 UCA1BRW +00000606 UCA1BRW_L +00000607 UCA1BRW_H +00000608 UCA1MCTL +0000060a UCA1STAT +0000060c UCA1RXBUF +0000060e UCA1TXBUF +00000610 UCA1ABCTL +00000612 UCA1IRCTL +00000612 UCA1IRCTL_L +00000613 UCA1IRCTL_H +0000061c UCA1ICTL +0000061c UCA1ICTL_L +0000061d UCA1ICTL_H +0000061e UCA1IV +00000620 UCB1CTLW0 +00000620 UCB1CTLW0_L +00000621 UCB1CTLW0_H +00000626 UCB1BRW +00000626 UCB1BRW_L +00000627 UCB1BRW_H +0000062a UCB1STAT +0000062c UCB1RXBUF +0000062e UCB1TXBUF +00000630 UCB1I2COA +00000630 UCB1I2COA_L +00000631 UCB1I2COA_H +00000632 UCB1I2CSA +00000632 UCB1I2CSA_L +00000633 UCB1I2CSA_H +0000063c UCB1ICTL +0000063c UCB1ICTL_L +0000063d UCB1ICTL_H +0000063e UCB1IV +00000640 UCA2CTLW0 +00000640 UCA2CTLW0_L +00000641 UCA2CTLW0_H +00000646 UCA2BRW +00000646 UCA2BRW_L +00000647 UCA2BRW_H +00000648 UCA2MCTL +0000064a UCA2STAT +0000064c UCA2RXBUF +0000064e UCA2TXBUF +00000650 UCA2ABCTL +00000652 UCA2IRCTL +00000652 UCA2IRCTL_L +00000653 UCA2IRCTL_H +0000065c UCA2ICTL +0000065c UCA2ICTL_L +0000065d UCA2ICTL_H +0000065e UCA2IV +00000660 UCB2CTLW0 +00000660 UCB2CTLW0_L +00000661 UCB2CTLW0_H +00000666 UCB2BRW +00000666 UCB2BRW_L +00000667 UCB2BRW_H +0000066a UCB2STAT +0000066c UCB2RXBUF +0000066e UCB2TXBUF +00000670 UCB2I2COA +00000670 UCB2I2COA_L +00000671 UCB2I2COA_H +00000672 UCB2I2CSA +00000672 UCB2I2CSA_L +00000673 UCB2I2CSA_H +0000067c UCB2ICTL +0000067c UCB2ICTL_L +0000067d UCB2ICTL_H +0000067e UCB2IV +00000680 UCA3CTLW0 +00000680 UCA3CTLW0_L +00000681 UCA3CTLW0_H +00000686 UCA3BRW +00000686 UCA3BRW_L +00000687 UCA3BRW_H +00000688 UCA3MCTL +0000068a UCA3STAT +0000068c UCA3RXBUF +0000068e UCA3TXBUF +00000690 UCA3ABCTL +00000692 UCA3IRCTL +00000692 UCA3IRCTL_L +00000693 UCA3IRCTL_H +0000069c UCA3ICTL +0000069c UCA3ICTL_L +0000069d UCA3ICTL_H +0000069e UCA3IV +000006a0 UCB3CTLW0 +000006a0 UCB3CTLW0_L +000006a1 UCB3CTLW0_H +000006a6 UCB3BRW +000006a6 UCB3BRW_L +000006a7 UCB3BRW_H +000006aa UCB3STAT +000006ac UCB3RXBUF +000006ae UCB3TXBUF +000006b0 UCB3I2COA +000006b0 UCB3I2COA_L +000006b1 UCB3I2COA_H +000006b2 UCB3I2CSA +000006b2 UCB3I2CSA_L +000006b3 UCB3I2CSA_H +000006bc UCB3ICTL +000006bc UCB3ICTL_L +000006bd UCB3ICTL_H +000006be UCB3IV +00000700 ADC12CTL0 +00000700 ADC12CTL0_L +00000701 ADC12CTL0_H +00000702 ADC12CTL1 +00000702 ADC12CTL1_L +00000703 ADC12CTL1_H +00000704 ADC12CTL2 +00000704 ADC12CTL2_L +00000705 ADC12CTL2_H +0000070a ADC12IFG +0000070a ADC12IFG_L +0000070b ADC12IFG_H +0000070c ADC12IE +0000070c ADC12IE_L +0000070d ADC12IE_H +0000070e ADC12IV +0000070e ADC12IV_L +0000070f ADC12IV_H +00000710 ADC12MCTL0 +00000711 ADC12MCTL1 +00000712 ADC12MCTL2 +00000713 ADC12MCTL3 +00000714 ADC12MCTL4 +00000715 ADC12MCTL5 +00000716 ADC12MCTL6 +00000717 ADC12MCTL7 +00000718 ADC12MCTL8 +00000719 ADC12MCTL9 +0000071a ADC12MCTL10 +0000071b ADC12MCTL11 +0000071c ADC12MCTL12 +0000071d ADC12MCTL13 +0000071e ADC12MCTL14 +0000071f ADC12MCTL15 +00000720 ADC12MEM0 +00000720 ADC12MEM0_L +00000721 ADC12MEM0_H +00000722 ADC12MEM1 +00000722 ADC12MEM1_L +00000723 ADC12MEM1_H +00000724 ADC12MEM2 +00000724 ADC12MEM2_L +00000725 ADC12MEM2_H +00000726 ADC12MEM3 +00000726 ADC12MEM3_L +00000727 ADC12MEM3_H +00000728 ADC12MEM4 +00000728 ADC12MEM4_L +00000729 ADC12MEM4_H +0000072a ADC12MEM5 +0000072a ADC12MEM5_L +0000072b ADC12MEM5_H +0000072c ADC12MEM6 +0000072c ADC12MEM6_L +0000072d ADC12MEM6_H +0000072e ADC12MEM7 +0000072e ADC12MEM7_L +0000072f ADC12MEM7_H +00000730 ADC12MEM8 +00000730 ADC12MEM8_L +00000731 ADC12MEM8_H +00000732 ADC12MEM9 +00000732 ADC12MEM9_L +00000733 ADC12MEM9_H +00000734 ADC12MEM10 +00000734 ADC12MEM10_L +00000735 ADC12MEM10_H +00000736 ADC12MEM11 +00000736 ADC12MEM11_L +00000737 ADC12MEM11_H +00000738 ADC12MEM12 +00000738 ADC12MEM12_L +00000739 ADC12MEM12_H +0000073a ADC12MEM13 +0000073a ADC12MEM13_L +0000073b ADC12MEM13_H +0000073c ADC12MEM14 +0000073c ADC12MEM14_L +0000073d ADC12MEM14_H +0000073e ADC12MEM15 +0000073e ADC12MEM15_L +0000073f ADC12MEM15_H +00001c00 status_flag +00001c01 cancomm_flag +00001c02 send_can +00001c03 rcv_can +00001c04 can_full +00001c05 ac_charge_mode +00001c06 dc_charge_mode +00001c07 charge_mode +00005b60 _stack +00005c00 __STACK_END +00005c00 timer_b0 +00005c2c _c_int00_noargs_noexit +00005c46 __TI_ISR_TRAP +00005c5c __TI_Handler_Table_Base +00005c64 __TI_CINIT_Base +00005c64 __TI_Handler_Table_Limit +00005c6c __TI_CINIT_Limit +0000ffd2 __TI_int41 +0000ffd4 __TI_int42 +0000ffd6 __TI_int43 +0000ffd8 __TI_int44 +0000ffda __TI_int45 +0000ffdc __TI_int46 +0000ffde __TI_int47 +0000ffe0 __TI_int48 +0000ffe2 __TI_int49 +0000ffe4 __TI_int50 +0000ffe6 __TI_int51 +0000ffe8 __TI_int52 +0000ffea __TI_int53 +0000ffec __TI_int54 +0000ffee __TI_int55 +0000fff0 __TI_int56 +0000fff2 __TI_int57 +0000fff4 __TI_int58 +0000fff6 __TI_int59 +0000fff8 __TI_int60 +0000fffa __TI_int61 +0000fffc __TI_int62 +0000fffe _reset_vector +00010000 _auto_init_hold_wdt +000100ea copy_in +00010150 main +000101ac SetVCoreUp +00010200 Clock_XT2_Init +0001023a Clock_XT1_Init +0001026c clock_init +00010294 Port_Init +000102ba timerB_init +000102d4 __mspabi_mpyi_f5hw +000102ec memcpy +00010300 __TI_decompress_none +00010312 C$$EXIT +00010312 abort +00010318 __TI_decompress_rle24 +0001031e _system_pre_init +00010322 _system_post_cinit +ffffffff __TI_pprof_out_hndl +ffffffff __TI_prof_data_size +ffffffff __TI_prof_data_start +ffffffff __c_args__ +UNDEFED __TI_BINIT_Base +UNDEFED __TI_BINIT_Limit +UNDEFED __TI_INITARRAY_Base +UNDEFED __TI_INITARRAY_Limit -[722 symbols] +[746 symbols] diff --git a/Telem_Debug/Debug1/Debug/Debug1.out b/Telem_Debug/Debug1/Debug/Debug1.out index 22f8531..a5ee95a 100644 Binary files a/Telem_Debug/Debug1/Debug/Debug1.out and b/Telem_Debug/Debug1/Debug/Debug1.out differ diff --git a/Telem_Debug/Debug1/Debug/Debug1_linkInfo.xml b/Telem_Debug/Debug1/Debug/Debug1_linkInfo.xml index 4ac8b5e..546b640 100644 --- a/Telem_Debug/Debug1/Debug/Debug1_linkInfo.xml +++ b/Telem_Debug/Debug1/Debug/Debug1_linkInfo.xml @@ -1,12 +1,12 @@ - + - MSP430 Linker PC v20.2.2.LTS - Copyright (c) 2003-2018 Texas Instruments Incorporated - 0x60a05db0 + MSP430 Linker PC v15.12.3.LTS + Copyright (c) 2003-2015 Texas Instruments Incorporated + 0x60a81324 0x0 Debug1.out - _c_int00_noargs + _c_int00_noargs_noexit
0x5c2c
 @@ -22,429 +22,451 @@ main.obj main.obj - - object - <internal> - <internal> - - C:\TI_CCS\ccs\tools\compiler\ti-cgt-msp430_20.2.2.LTS\lib\ + C:\ti\ccsv6\tools\compiler\msp430_15.12.3.LTS\lib\ archive rts430x_lc_rd_eabi.lib - int41.asm.obj + boot.obj - C:\TI_CCS\ccs\tools\compiler\ti-cgt-msp430_20.2.2.LTS\lib\ + C:\ti\ccsv6\tools\compiler\msp430_15.12.3.LTS\lib\ archive rts430x_lc_rd_eabi.lib - int42.asm.obj + boot_special.obj - C:\TI_CCS\ccs\tools\compiler\ti-cgt-msp430_20.2.2.LTS\lib\ + C:\ti\ccsv6\tools\compiler\msp430_15.12.3.LTS\lib\ archive rts430x_lc_rd_eabi.lib - int43.asm.obj + copy_decompress_none.obj - C:\TI_CCS\ccs\tools\compiler\ti-cgt-msp430_20.2.2.LTS\lib\ + C:\ti\ccsv6\tools\compiler\msp430_15.12.3.LTS\lib\ archive rts430x_lc_rd_eabi.lib - int44.asm.obj + copy_decompress_rle.obj - C:\TI_CCS\ccs\tools\compiler\ti-cgt-msp430_20.2.2.LTS\lib\ + C:\ti\ccsv6\tools\compiler\msp430_15.12.3.LTS\lib\ archive rts430x_lc_rd_eabi.lib - int45.asm.obj + copy_zero_init.obj - C:\TI_CCS\ccs\tools\compiler\ti-cgt-msp430_20.2.2.LTS\lib\ + C:\ti\ccsv6\tools\compiler\msp430_15.12.3.LTS\lib\ archive rts430x_lc_rd_eabi.lib - int46.asm.obj + exit.obj - C:\TI_CCS\ccs\tools\compiler\ti-cgt-msp430_20.2.2.LTS\lib\ + C:\ti\ccsv6\tools\compiler\msp430_15.12.3.LTS\lib\ archive rts430x_lc_rd_eabi.lib - int47.asm.obj + exit_gvars.obj - C:\TI_CCS\ccs\tools\compiler\ti-cgt-msp430_20.2.2.LTS\lib\ + C:\ti\ccsv6\tools\compiler\msp430_15.12.3.LTS\lib\ archive rts430x_lc_rd_eabi.lib - int48.asm.obj + int41.obj - C:\TI_CCS\ccs\tools\compiler\ti-cgt-msp430_20.2.2.LTS\lib\ + C:\ti\ccsv6\tools\compiler\msp430_15.12.3.LTS\lib\ archive rts430x_lc_rd_eabi.lib - int49.asm.obj + int42.obj - C:\TI_CCS\ccs\tools\compiler\ti-cgt-msp430_20.2.2.LTS\lib\ + C:\ti\ccsv6\tools\compiler\msp430_15.12.3.LTS\lib\ archive rts430x_lc_rd_eabi.lib - int50.asm.obj + int43.obj - C:\TI_CCS\ccs\tools\compiler\ti-cgt-msp430_20.2.2.LTS\lib\ + C:\ti\ccsv6\tools\compiler\msp430_15.12.3.LTS\lib\ archive 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0x6bc - 0x1f - - - - .debug_pubtypes - 0x6db - 0x6db - 0x50 - - - - .debug_pubtypes - 0x72b - 0x72b + 0x189 + 0x189 0x1d - + .debug_pubtypes - 0x748 - 0x748 - 0x48 - + 0x1a6 + 0x1a6 + 0x32 + - + .debug_pubtypes - 0x790 - 0x790 - 0x5d - + 0x1d8 + 0x1d8 + 0x1f + - + .debug_pubtypes - 0x7ed - 0x7ed - 0x48 - + 0x1f7 + 0x1f7 + 0x50 + - + .debug_pubtypes - 0x835 - 0x835 - 0x35 - + 0x247 + 0x247 + 0x23 + @@ -1925,7 +1982,7 @@ 0x1c00 0xc - + @@ -1947,58 +2004,61 @@ 0x5b60 0xa0 - - + + - + .text 0x10000 0x10000 - 0x280 + 0x324 + + + + + + + + + + + + - - - - - - - - - + - - - + + .text - + .text:_isr 0x5c00 0x5c00 - 0x50 + 0x4e - - - + + + .cinit - 0x5c50 - 0x5c50 - 0x1c + 0x5c4e + 0x5c4e + 0x1e - - - + + + @@ -2028,7 +2088,7 @@ 0x5c00 0x0 - + @@ -2578,267 +2638,272 @@ 0xfffe 0x2 - + - + .TI.persistent 0x0 0x0 - + .debug_info 0x0 0x0 - 0x2e6e + 0x311b - - - - - - - - - - - - + + + - - - - - - - - - - - - - - - - - - + + + + - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + .debug_line 0x0 0x0 - 0xc93 + 0xcdc - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + .debug_frame 0x0 0x0 - 0x3d0 + 0x520 - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + - + .debug_abbrev 0x0 0x0 - 0xae7 + 0xc1c - + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + .debug_str 0x0 0x0 - 0x1221 + 0x9bb - - - - - - - - - - - - + + + + + + + + + - + .debug_aranges 0x0 0x0 - 0x220 + 0x280 - - - - - - - - - - - - - - + + + + + + + + + - - + + + + + + + + + + - + .debug_pubnames 0x0 0x0 - 0x322 + 0x38c - - - - - + + + + + + + + - - - - - - - - - - - - - + + + + + + + + + + + + + - + .debug_pubtypes 0x0 0x0 - 0x86a + 0x26a - - - - - - - - - - - - + + + + + + + + + - + SEGMENT_0 0x1c00 0xc @@ -2847,7 +2912,7 @@ - + SEGMENT_1 0x5b60 0xa0 @@ -2856,7 +2921,7 @@ - + SEGMENT_2 0x5c00 0x5c00 @@ -2867,11 +2932,11 @@ - + SEGMENT_3 0xffd2 0xffd2 - 0x2ae + 0x352 0x5 @@ -2897,7 +2962,7 @@ - + @@ -3020,12 +3085,12 @@ 0x5c00 - 0x50 + 0x4e - 0x5c50 - 0x1c + 0x5c4e + 0x1e @@ -3858,18 +3923,18 @@ 0x0 0x10000 0x35c00 - 0x280 - 0x35980 + 0x324 + 0x358dc RWIX 0x10000 - 0x280 - + 0x324 + - 0x10280 - 0x35980 + 0x10324 + 0x358dc @@ -3879,11 +3944,11 @@ __TI_cinit_table .data - 0x5c50 - 0xb + 0x5c4e + 0xd 0x1c00 0xc - lzss + rle @@ -3891,7 +3956,7 @@ __TI_handler_table 0x0 - __TI_decompress_lzss + __TI_decompress_rle24 0x1 @@ -4280,2562 +4345,2660 @@ 0x500 + DMACTL0_L + 0x500 + + + DMACTL0_H + 0x501 + + DMACTL1 0x502 - + + DMACTL1_L + 0x502 + + + DMACTL1_H + 0x503 + + DMACTL2 0x504 - + + DMACTL2_L + 0x504 + + + DMACTL2_H + 0x505 + + DMACTL3 0x506 - + + DMACTL3_L + 0x506 + + + DMACTL3_H + 0x507 + + DMACTL4 0x508 - + + DMACTL4_L + 0x508 + + + DMACTL4_H + 0x509 + + DMAIV 0x50e - + + DMAIV_L + 0x50e + + + DMAIV_H + 0x50f + + DMA0CTL 0x510 - + + DMA0CTL_L + 0x510 + + + DMA0CTL_H + 0x511 + + DMA0SA 0x512 - + DMA0SAL 0x512 - + DMA0SAH 0x514 - + DMA0DA 0x516 - + DMA0DAL 0x516 - + DMA0DAH 0x518 - + DMA0SZ 0x51a - + DMA1CTL 0x520 - + + DMA1CTL_L + 0x520 + + + DMA1CTL_H + 0x521 + + DMA1SA 0x522 - + DMA1SAL 0x522 - + DMA1SAH 0x524 - + DMA1DA 0x526 - + DMA1DAL 0x526 - + DMA1DAH 0x528 - + DMA1SZ 0x52a - + DMA2CTL 0x530 - + + DMA2CTL_L + 0x530 + + + DMA2CTL_H + 0x531 + + DMA2SA 0x532 - + DMA2SAL 0x532 - + DMA2SAH 0x534 - + DMA2DA 0x536 - + DMA2DAL 0x536 - + DMA2DAH 0x538 - + DMA2SZ 0x53a - + FCTL1 0x140 - + FCTL1_L 0x140 - + FCTL1_H 0x141 - + FCTL3 0x144 - + FCTL3_L 0x144 - + FCTL3_H 0x145 - + FCTL4 0x146 - + FCTL4_L 0x146 - + FCTL4_H 0x147 - + MPY 0x4c0 - + MPY_L 0x4c0 - + MPY_H 0x4c1 - + MPYS 0x4c2 - + MPYS_L 0x4c2 - + MPYS_H 0x4c3 - + MAC 0x4c4 - + MAC_L 0x4c4 - + MAC_H 0x4c5 - + MACS 0x4c6 - + MACS_L 0x4c6 - + MACS_H 0x4c7 - + OP2 0x4c8 - + OP2_L 0x4c8 - + OP2_H 0x4c9 - + RESLO 0x4ca - + RESLO_L 0x4ca - + RESLO_H 0x4cb - + RESHI 0x4cc - + RESHI_L 0x4cc - + RESHI_H 0x4cd - + SUMEXT 0x4ce - + SUMEXT_L 0x4ce - + SUMEXT_H 0x4cf - + MPY32L 0x4d0 - + MPY32L_L 0x4d0 - + MPY32L_H 0x4d1 - + MPY32H 0x4d2 - + MPY32H_L 0x4d2 - + MPY32H_H 0x4d3 - + MPYS32L 0x4d4 - + MPYS32L_L 0x4d4 - + MPYS32L_H 0x4d5 - + MPYS32H 0x4d6 - + MPYS32H_L 0x4d6 - + MPYS32H_H 0x4d7 - + MAC32L 0x4d8 - + MAC32L_L 0x4d8 - + MAC32L_H 0x4d9 - + MAC32H 0x4da - + MAC32H_L 0x4da - + MAC32H_H 0x4db - + MACS32L 0x4dc - + MACS32L_L 0x4dc - + MACS32L_H 0x4dd - + MACS32H 0x4de - + MACS32H_L 0x4de - + MACS32H_H 0x4df - + OP2L 0x4e0 - + OP2L_L 0x4e0 - + OP2L_H 0x4e1 - + OP2H 0x4e2 - + OP2H_L 0x4e2 - + OP2H_H 0x4e3 - + RES0 0x4e4 - + RES0_L 0x4e4 - + RES0_H 0x4e5 - + RES1 0x4e6 - + RES1_L 0x4e6 - + RES1_H 0x4e7 - + RES2 0x4e8 - + RES2_L 0x4e8 - + RES2_H 0x4e9 - + RES3 0x4ea - + RES3_L 0x4ea - + RES3_H 0x4eb - + MPY32CTL0 0x4ec - + MPY32CTL0_L 0x4ec - + MPY32CTL0_H 0x4ed - + PAIN 0x200 - + PAIN_L 0x200 - + PAIN_H 0x201 - + PAOUT 0x202 - + PAOUT_L 0x202 - + PAOUT_H 0x203 - + PADIR 0x204 - + PADIR_L 0x204 - + PADIR_H 0x205 - + PAREN 0x206 - + PAREN_L 0x206 - + PAREN_H 0x207 - + PADS 0x208 - + PADS_L 0x208 - + PADS_H 0x209 - + PASEL 0x20a - + PASEL_L 0x20a - + PASEL_H 0x20b - + PAIES 0x218 - + PAIES_L 0x218 - + PAIES_H 0x219 - + PAIE 0x21a - + PAIE_L 0x21a - + PAIE_H 0x21b - + PAIFG 0x21c - + PAIFG_L 0x21c - + PAIFG_H 0x21d - + P1IV 0x20e - + P2IV 0x21e - + PBIN 0x220 - + PBIN_L 0x220 - + PBIN_H 0x221 - + PBOUT 0x222 - + PBOUT_L 0x222 - + PBOUT_H 0x223 - + PBDIR 0x224 - + PBDIR_L 0x224 - + PBDIR_H 0x225 - + PBREN 0x226 - + PBREN_L 0x226 - + PBREN_H 0x227 - + PBDS 0x228 - + PBDS_L 0x228 - + PBDS_H 0x229 - + PBSEL 0x22a - + PBSEL_L 0x22a - + PBSEL_H 0x22b - + PCIN 0x240 - + PCIN_L 0x240 - + PCIN_H 0x241 - + PCOUT 0x242 - + PCOUT_L 0x242 - + PCOUT_H 0x243 - + PCDIR 0x244 - + PCDIR_L 0x244 - + PCDIR_H 0x245 - + PCREN 0x246 - + PCREN_L 0x246 - + PCREN_H 0x247 - + PCDS 0x248 - + PCDS_L 0x248 - + PCDS_H 0x249 - + PCSEL 0x24a - + PCSEL_L 0x24a - + PCSEL_H 0x24b - + PDIN 0x260 - + PDIN_L 0x260 - + PDIN_H 0x261 - + PDOUT 0x262 - + PDOUT_L 0x262 - + PDOUT_H 0x263 - + PDDIR 0x264 - + PDDIR_L 0x264 - + PDDIR_H 0x265 - + PDREN 0x266 - + PDREN_L 0x266 - + PDREN_H 0x267 - + PDDS 0x268 - + PDDS_L 0x268 - + PDDS_H 0x269 - + PDSEL 0x26a - + PDSEL_L 0x26a - + PDSEL_H 0x26b - + PEIN 0x280 - + PEIN_L 0x280 - + PEIN_H 0x281 - + PEOUT 0x282 - + PEOUT_L 0x282 - + PEOUT_H 0x283 - + PEDIR 0x284 - + PEDIR_L 0x284 - + PEDIR_H 0x285 - + PEREN 0x286 - + PEREN_L 0x286 - + PEREN_H 0x287 - + PEDS 0x288 - + PEDS_L 0x288 - + PEDS_H 0x289 - + PESEL 0x28a - + PESEL_L 0x28a - + PESEL_H 0x28b - + PFIN 0x2a0 - + PFIN_L 0x2a0 - + PFIN_H 0x2a1 - + PFOUT 0x2a2 - + PFOUT_L 0x2a2 - + PFOUT_H 0x2a3 - + PFDIR 0x2a4 - + PFDIR_L 0x2a4 - + PFDIR_H 0x2a5 - + PFREN 0x2a6 - + PFREN_L 0x2a6 - + PFREN_H 0x2a7 - + PFDS 0x2a8 - + PFDS_L 0x2a8 - + PFDS_H 0x2a9 - + PFSEL 0x2aa - + PFSEL_L 0x2aa - + PFSEL_H 0x2ab - + PJIN 0x320 - + PJIN_L 0x320 - + PJIN_H 0x321 - + PJOUT 0x322 - + PJOUT_L 0x322 - + PJOUT_H 0x323 - + PJDIR 0x324 - + PJDIR_L 0x324 - + PJDIR_H 0x325 - + PJREN 0x326 - + PJREN_L 0x326 - + PJREN_H 0x327 - + PJDS 0x328 - + PJDS_L 0x328 - + PJDS_H 0x329 - + PMMCTL0 0x120 - + PMMCTL0_L 0x120 - + PMMCTL0_H 0x121 - + PMMCTL1 0x122 - + PMMCTL1_L 0x122 - + PMMCTL1_H 0x123 - + SVSMHCTL 0x124 - + SVSMHCTL_L 0x124 - + SVSMHCTL_H 0x125 - + SVSMLCTL 0x126 - + SVSMLCTL_L 0x126 - + SVSMLCTL_H 0x127 - + SVSMIO 0x128 - + SVSMIO_L 0x128 - + SVSMIO_H 0x129 - + PMMIFG 0x12c - + PMMIFG_L 0x12c - + PMMIFG_H 0x12d - + PMMRIE 0x12e - + PMMRIE_L 0x12e - + PMMRIE_H 0x12f - + PM5CTL0 0x130 - + PM5CTL0_L 0x130 - + PM5CTL0_H 0x131 - + RCCTL0 0x158 - + RCCTL0_L 0x158 - + RCCTL0_H 0x159 - + REFCTL0 0x1b0 - + REFCTL0_L 0x1b0 - + REFCTL0_H 0x1b1 - + RTCCTL01 0x4a0 - + RTCCTL01_L 0x4a0 - + RTCCTL01_H 0x4a1 - + RTCCTL23 0x4a2 - + RTCCTL23_L 0x4a2 - + RTCCTL23_H 0x4a3 - + RTCPS0CTL 0x4a8 - + RTCPS0CTL_L 0x4a8 - + RTCPS0CTL_H 0x4a9 - + RTCPS1CTL 0x4aa - + RTCPS1CTL_L 0x4aa - + RTCPS1CTL_H 0x4ab - + RTCPS 0x4ac - + RTCPS_L 0x4ac - + RTCPS_H 0x4ad - + RTCIV 0x4ae - + RTCTIM0 0x4b0 - + RTCTIM0_L 0x4b0 - + RTCTIM0_H 0x4b1 - + RTCTIM1 0x4b2 - + RTCTIM1_L 0x4b2 - + RTCTIM1_H 0x4b3 - + RTCDATE 0x4b4 - + RTCDATE_L 0x4b4 - + RTCDATE_H 0x4b5 - + RTCYEAR 0x4b6 - + RTCYEAR_L 0x4b6 - + RTCYEAR_H 0x4b7 - + RTCAMINHR 0x4b8 - + RTCAMINHR_L 0x4b8 - + RTCAMINHR_H 0x4b9 - + RTCADOWDAY 0x4ba - + RTCADOWDAY_L 0x4ba - + RTCADOWDAY_H 0x4bb - + SFRIE1 0x100 - + SFRIE1_L 0x100 - + SFRIE1_H 0x101 - + SFRIFG1 0x102 - + SFRIFG1_L 0x102 - + SFRIFG1_H 0x103 - + SFRRPCR 0x104 - + SFRRPCR_L 0x104 - + SFRRPCR_H 0x105 - + SYSCTL 0x180 - + SYSCTL_L 0x180 - + SYSCTL_H 0x181 - + SYSBSLC 0x182 - + SYSBSLC_L 0x182 - + SYSBSLC_H 0x183 - + SYSJMBC 0x186 - + SYSJMBC_L 0x186 - + SYSJMBC_H 0x187 - + SYSJMBI0 0x188 - + SYSJMBI0_L 0x188 - + SYSJMBI0_H 0x189 - + SYSJMBI1 0x18a - + SYSJMBI1_L 0x18a - + SYSJMBI1_H 0x18b - + SYSJMBO0 0x18c - + SYSJMBO0_L 0x18c - + SYSJMBO0_H 0x18d - + SYSJMBO1 0x18e - + SYSJMBO1_L 0x18e - + SYSJMBO1_H 0x18f - + SYSBERRIV 0x198 - + SYSBERRIV_L 0x198 - + SYSBERRIV_H 0x199 - + SYSUNIV 0x19a - + SYSUNIV_L 0x19a - + SYSUNIV_H 0x19b - + SYSSNIV 0x19c - + SYSSNIV_L 0x19c - + SYSSNIV_H 0x19d - + SYSRSTIV 0x19e - + SYSRSTIV_L 0x19e - + SYSRSTIV_H 0x19f - + TA0CTL 0x340 - + TA0CCTL0 0x342 - + TA0CCTL1 0x344 - + TA0CCTL2 0x346 - + TA0CCTL3 0x348 - + TA0CCTL4 0x34a - + TA0R 0x350 - + TA0CCR0 0x352 - + TA0CCR1 0x354 - + TA0CCR2 0x356 - + TA0CCR3 0x358 - + TA0CCR4 0x35a - + TA0IV 0x36e - + TA0EX0 0x360 - + TA1CTL 0x380 - + TA1CCTL0 0x382 - + TA1CCTL1 0x384 - + TA1CCTL2 0x386 - + TA1R 0x390 - + TA1CCR0 0x392 - + TA1CCR1 0x394 - + TA1CCR2 0x396 - + TA1IV 0x3ae - + TA1EX0 0x3a0 - + TB0CTL 0x3c0 - + TB0CCTL0 0x3c2 - + TB0CCTL1 0x3c4 - + TB0CCTL2 0x3c6 - + TB0CCTL3 0x3c8 - + TB0CCTL4 0x3ca - + TB0CCTL5 0x3cc - + TB0CCTL6 0x3ce - + TB0R 0x3d0 - + TB0CCR0 0x3d2 - + TB0CCR1 0x3d4 - + TB0CCR2 0x3d6 - + TB0CCR3 0x3d8 - + TB0CCR4 0x3da - + TB0CCR5 0x3dc - + TB0CCR6 0x3de - + TB0EX0 0x3e0 - + TB0IV 0x3ee - + UCSCTL0 0x160 - + UCSCTL0_L 0x160 - + UCSCTL0_H 0x161 - + UCSCTL1 0x162 - + UCSCTL1_L 0x162 - + UCSCTL1_H 0x163 - + UCSCTL2 0x164 - + UCSCTL2_L 0x164 - + UCSCTL2_H 0x165 - + UCSCTL3 0x166 - + UCSCTL3_L 0x166 - + UCSCTL3_H 0x167 - + UCSCTL4 0x168 - + UCSCTL4_L 0x168 - + UCSCTL4_H 0x169 - + UCSCTL5 0x16a - + UCSCTL5_L 0x16a - + UCSCTL5_H 0x16b - + UCSCTL6 0x16c - + UCSCTL6_L 0x16c - + UCSCTL6_H 0x16d - + UCSCTL7 0x16e - + UCSCTL7_L 0x16e - + UCSCTL7_H 0x16f - + UCSCTL8 0x170 - + UCSCTL8_L 0x170 - + UCSCTL8_H 0x171 - + UCA0CTLW0 0x5c0 - + UCA0CTLW0_L 0x5c0 - + UCA0CTLW0_H 0x5c1 - + UCA0BRW 0x5c6 - + UCA0BRW_L 0x5c6 - + UCA0BRW_H 0x5c7 - + UCA0MCTL 0x5c8 - + UCA0STAT 0x5ca - + UCA0RXBUF 0x5cc - + UCA0TXBUF 0x5ce - + UCA0ABCTL 0x5d0 - + UCA0IRCTL 0x5d2 - + UCA0IRCTL_L 0x5d2 - + UCA0IRCTL_H 0x5d3 - + UCA0ICTL 0x5dc - + UCA0ICTL_L 0x5dc - + UCA0ICTL_H 0x5dd - + UCA0IV 0x5de - + UCB0CTLW0 0x5e0 - + UCB0CTLW0_L 0x5e0 - + UCB0CTLW0_H 0x5e1 - + UCB0BRW 0x5e6 - + UCB0BRW_L 0x5e6 - + UCB0BRW_H 0x5e7 - + UCB0STAT 0x5ea - + UCB0RXBUF 0x5ec - + UCB0TXBUF 0x5ee - + UCB0I2COA 0x5f0 - + UCB0I2COA_L 0x5f0 - + UCB0I2COA_H 0x5f1 - + UCB0I2CSA 0x5f2 - + UCB0I2CSA_L 0x5f2 - + UCB0I2CSA_H 0x5f3 - + UCB0ICTL 0x5fc - + UCB0ICTL_L 0x5fc - + UCB0ICTL_H 0x5fd - + UCB0IV 0x5fe - + UCA1CTLW0 0x600 - + UCA1CTLW0_L 0x600 - + UCA1CTLW0_H 0x601 - + UCA1BRW 0x606 - + UCA1BRW_L 0x606 - + UCA1BRW_H 0x607 - + UCA1MCTL 0x608 - + UCA1STAT 0x60a - + UCA1RXBUF 0x60c - + UCA1TXBUF 0x60e - + UCA1ABCTL 0x610 - + UCA1IRCTL 0x612 - + UCA1IRCTL_L 0x612 - + UCA1IRCTL_H 0x613 - + UCA1ICTL 0x61c - + UCA1ICTL_L 0x61c - + UCA1ICTL_H 0x61d - + UCA1IV 0x61e - + UCB1CTLW0 0x620 - + UCB1CTLW0_L 0x620 - + UCB1CTLW0_H 0x621 - + UCB1BRW 0x626 - + UCB1BRW_L 0x626 - + UCB1BRW_H 0x627 - + UCB1STAT 0x62a - + UCB1RXBUF 0x62c - + UCB1TXBUF 0x62e - + UCB1I2COA 0x630 - + UCB1I2COA_L 0x630 - + UCB1I2COA_H 0x631 - + UCB1I2CSA 0x632 - + UCB1I2CSA_L 0x632 - + UCB1I2CSA_H 0x633 - + UCB1ICTL 0x63c - + UCB1ICTL_L 0x63c - + UCB1ICTL_H 0x63d - + UCB1IV 0x63e - + UCA2CTLW0 0x640 - + UCA2CTLW0_L 0x640 - + UCA2CTLW0_H 0x641 - + UCA2BRW 0x646 - + UCA2BRW_L 0x646 - + UCA2BRW_H 0x647 - + UCA2MCTL 0x648 - + UCA2STAT 0x64a - + UCA2RXBUF 0x64c - + UCA2TXBUF 0x64e - + UCA2ABCTL 0x650 - + UCA2IRCTL 0x652 - + UCA2IRCTL_L 0x652 - + UCA2IRCTL_H 0x653 - + UCA2ICTL 0x65c - + UCA2ICTL_L 0x65c - + UCA2ICTL_H 0x65d - + UCA2IV 0x65e - + UCB2CTLW0 0x660 - + UCB2CTLW0_L 0x660 - + UCB2CTLW0_H 0x661 - + UCB2BRW 0x666 - + UCB2BRW_L 0x666 - + UCB2BRW_H 0x667 - + UCB2STAT 0x66a - + UCB2RXBUF 0x66c - + UCB2TXBUF 0x66e - + UCB2I2COA 0x670 - + UCB2I2COA_L 0x670 - + UCB2I2COA_H 0x671 - + UCB2I2CSA 0x672 - + UCB2I2CSA_L 0x672 - + UCB2I2CSA_H 0x673 - + UCB2ICTL 0x67c - + UCB2ICTL_L 0x67c - + UCB2ICTL_H 0x67d - + UCB2IV 0x67e - + UCA3CTLW0 0x680 - + UCA3CTLW0_L 0x680 - + UCA3CTLW0_H 0x681 - + UCA3BRW 0x686 - + UCA3BRW_L 0x686 - + UCA3BRW_H 0x687 - + UCA3MCTL 0x688 - + UCA3STAT 0x68a - + UCA3RXBUF 0x68c - + UCA3TXBUF 0x68e - + UCA3ABCTL 0x690 - + UCA3IRCTL 0x692 - + UCA3IRCTL_L 0x692 - + UCA3IRCTL_H 0x693 - + UCA3ICTL 0x69c - + UCA3ICTL_L 0x69c - + UCA3ICTL_H 0x69d - + UCA3IV 0x69e - + UCB3CTLW0 0x6a0 - + UCB3CTLW0_L 0x6a0 - + UCB3CTLW0_H 0x6a1 - + UCB3BRW 0x6a6 - + UCB3BRW_L 0x6a6 - + UCB3BRW_H 0x6a7 - + UCB3STAT 0x6aa - + UCB3RXBUF 0x6ac - + UCB3TXBUF 0x6ae - + UCB3I2COA 0x6b0 - + UCB3I2COA_L 0x6b0 - + UCB3I2COA_H 0x6b1 - + UCB3I2CSA 0x6b2 - + UCB3I2CSA_L 0x6b2 - + UCB3I2CSA_H 0x6b3 - + UCB3ICTL 0x6bc - + UCB3ICTL_L 0x6bc - + UCB3ICTL_H 0x6bd - + UCB3IV 0x6be - + WDTCTL 0x15c - + WDTCTL_L 0x15c - + WDTCTL_H 0x15d - + __TI_CINIT_Base 0x5c64 - + __TI_CINIT_Limit 0x5c6c - + __TI_Handler_Table_Base 0x5c5c - + __TI_Handler_Table_Limit 0x5c64 - + __STACK_SIZE 0xa0 - + __STACK_END 0x5c00 - + __c_args__ 0xffffffff - + __TI_pprof_out_hndl 0xffffffff - + __TI_prof_data_start 0xffffffff - + __TI_prof_data_size 0xffffffff - + clock_init - 0x101e6 - + 0x1026c + - + Port_Init - 0x1020e - + 0x10294 + - + Clock_XT2_Init - 0x1017a - + 0x10200 + - + Clock_XT1_Init - 0x101b4 - + 0x1023a + - + SetVCoreUp - 0x100d2 - + 0x101ac + - + __TI_int60 0xfff8 - + rcv_can 0x1c03 - - - - dc_charge_mode - 0x1c06 - - - - main - 0x10076 - - - - timerB_init - 0x10234 - - - - timer_b0 - 0x5c00 - - - - send_can - 0x1c02 - - - - ac_charge_mode - 0x1c05 - - - - charge_mode - 0x1c07 - - - - can_full - 0x1c04 - + - status_flag - 0x1c00 - + dc_charge_mode + 0x1c06 + - cancomm_flag - 0x1c01 + main + 0x10150 + + + + timerB_init + 0x102ba + + + + timer_b0 + 0x5c00 + send_can + 0x1c02 + + + + ac_charge_mode + 0x1c05 + + + + charge_mode + 0x1c07 + + + + can_full + 0x1c04 + + + + status_flag + 0x1c00 + + + + cancomm_flag + 0x1c01 + + + + _stack + 0x5b60 + + + + _reset_vector + 0xfffe + + + + _c_int00_noargs_noexit + 0x5c2c + + + + __TI_decompress_none + 0x10300 + + + + __TI_decompress_rle24 + 0x10318 + + + + C$$EXIT + 0x10312 + + + + abort + 0x10312 + + + __TI_int41 0xffd2 - + __TI_int42 0xffd4 - + __TI_int43 0xffd6 - + __TI_int44 0xffd8 - + __TI_int45 0xffda - + __TI_int46 0xffdc - + __TI_int47 0xffde - + __TI_int48 0xffe0 - + __TI_int49 0xffe2 - + __TI_int50 0xffe4 - + __TI_int51 0xffe6 - + __TI_int52 0xffe8 - + __TI_int53 0xffea - + __TI_int54 0xffec - + __TI_int55 0xffee - + __TI_int56 0xfff0 - + __TI_int57 0xfff2 - + __TI_int58 0xfff4 - + __TI_int59 0xfff6 - + __TI_int61 0xfffa - + __TI_int62 0xfffc - + __TI_ISR_TRAP - 0x5c48 - + 0x5c46 + - - _stack - 0x5b60 - - - - _c_int00_noargs - 0x5c2c - - - - _reset_vector - 0xfffe - - - - __TI_auto_init_nobinit_nopinit_hold_wdt - 0x10126 - - - - _system_pre_init - 0x1027a - - - - _system_post_cinit - 0x1027e - - - - __TI_decompress_none - 0x10262 - - - - __TI_decompress_lzss - 0x10000 - - - - C$$EXIT - 0x10274 - - - - abort - 0x10274 - - - + memcpy - 0x1024e - + 0x102ec + + + + __mspabi_mpyi_f5hw + 0x102d4 + + + + _system_pre_init + 0x1031e + + + + _auto_init_hold_wdt + 0x10000 + + + + copy_in + 0x100ea + + + + _system_post_cinit + 0x10322 + + + + __TI_BINIT_Base + 0x0 + + + __TI_BINIT_Limit + 0x0 + + + __TI_INITARRAY_Base + 0x0 + + + __TI_INITARRAY_Limit + 0x0 Link successful diff --git a/Telem_Debug/Debug1/Debug/clock_init.d b/Telem_Debug/Debug1/Debug/clock_init.d index 0077614..6cf45c0 100644 --- a/Telem_Debug/Debug1/Debug/clock_init.d +++ b/Telem_Debug/Debug1/Debug/clock_init.d @@ -1,13 +1,13 @@ # FIXED clock_init.obj: ../clock_init.c -clock_init.obj: C:/TI_CCS/ccs/ccs_base/msp430/include/msp430x54xa.h -clock_init.obj: C:/TI_CCS/ccs/ccs_base/msp430/include/in430.h -clock_init.obj: C:/TI_CCS/ccs/tools/compiler/ti-cgt-msp430_20.2.2.LTS/include/intrinsics.h -clock_init.obj: C:/TI_CCS/ccs/tools/compiler/ti-cgt-msp430_20.2.2.LTS/include/intrinsics_legacy_undefs.h +clock_init.obj: C:/ti/ccsv6/ccs_base/msp430/include/msp430x54xa.h +clock_init.obj: C:/ti/ccsv6/ccs_base/msp430/include/in430.h +clock_init.obj: C:/ti/ccsv6/tools/compiler/msp430_15.12.3.LTS/include/intrinsics.h +clock_init.obj: C:/ti/ccsv6/tools/compiler/msp430_15.12.3.LTS/include/intrinsics_legacy_undefs.h ../clock_init.c: -C:/TI_CCS/ccs/ccs_base/msp430/include/msp430x54xa.h: -C:/TI_CCS/ccs/ccs_base/msp430/include/in430.h: -C:/TI_CCS/ccs/tools/compiler/ti-cgt-msp430_20.2.2.LTS/include/intrinsics.h: -C:/TI_CCS/ccs/tools/compiler/ti-cgt-msp430_20.2.2.LTS/include/intrinsics_legacy_undefs.h: +C:/ti/ccsv6/ccs_base/msp430/include/msp430x54xa.h: +C:/ti/ccsv6/ccs_base/msp430/include/in430.h: +C:/ti/ccsv6/tools/compiler/msp430_15.12.3.LTS/include/intrinsics.h: +C:/ti/ccsv6/tools/compiler/msp430_15.12.3.LTS/include/intrinsics_legacy_undefs.h: diff --git a/Telem_Debug/Debug1/Debug/clock_init.obj b/Telem_Debug/Debug1/Debug/clock_init.obj index 89488f0..54c733e 100644 Binary files a/Telem_Debug/Debug1/Debug/clock_init.obj and b/Telem_Debug/Debug1/Debug/clock_init.obj differ diff --git a/Telem_Debug/Debug1/Debug/main.d b/Telem_Debug/Debug1/Debug/main.d index 37b9fd0..994a2d3 100644 --- a/Telem_Debug/Debug1/Debug/main.d +++ b/Telem_Debug/Debug1/Debug/main.d @@ -1,49 +1,41 @@ # FIXED main.obj: ../main.c -main.obj: C:/TI_CCS/ccs/ccs_base/msp430/include/msp430.h -main.obj: C:/TI_CCS/ccs/ccs_base/msp430/include/msp430f5438a.h -main.obj: C:/TI_CCS/ccs/ccs_base/msp430/include/in430.h -main.obj: C:/TI_CCS/ccs/tools/compiler/ti-cgt-msp430_20.2.2.LTS/include/intrinsics.h -main.obj: C:/TI_CCS/ccs/tools/compiler/ti-cgt-msp430_20.2.2.LTS/include/intrinsics_legacy_undefs.h -main.obj: C:/TI_CCS/ccs/tools/compiler/ti-cgt-msp430_20.2.2.LTS/include/stdio.h -main.obj: C:/TI_CCS/ccs/tools/compiler/ti-cgt-msp430_20.2.2.LTS/include/_ti_config.h -main.obj: C:/TI_CCS/ccs/tools/compiler/ti-cgt-msp430_20.2.2.LTS/include/linkage.h -main.obj: C:/TI_CCS/ccs/tools/compiler/ti-cgt-msp430_20.2.2.LTS/include/stdarg.h -main.obj: C:/TI_CCS/ccs/tools/compiler/ti-cgt-msp430_20.2.2.LTS/include/sys/_types.h -main.obj: C:/TI_CCS/ccs/tools/compiler/ti-cgt-msp430_20.2.2.LTS/include/sys/cdefs.h -main.obj: C:/TI_CCS/ccs/tools/compiler/ti-cgt-msp430_20.2.2.LTS/include/machine/_types.h -main.obj: C:/TI_CCS/ccs/tools/compiler/ti-cgt-msp430_20.2.2.LTS/include/stdlib.h -main.obj: C:/TI_CCS/ccs/ccs_base/msp430/include/msp430x54xa.h -main.obj: C:/TI_CCS/ccs/tools/compiler/ti-cgt-msp430_20.2.2.LTS/include/ctype.h -main.obj: C:/TI_CCS/ccs/tools/compiler/ti-cgt-msp430_20.2.2.LTS/include/_isfuncdcl.h -main.obj: C:/TI_CCS/ccs/tools/compiler/ti-cgt-msp430_20.2.2.LTS/include/string.h -main.obj: C:/TI_CCS/ccs/tools/compiler/ti-cgt-msp430_20.2.2.LTS/include/math.h -main.obj: C:/TI_CCS/ccs/tools/compiler/ti-cgt-msp430_20.2.2.LTS/include/_defs.h -main.obj: C:/TI_CCS/ccs/tools/compiler/ti-cgt-msp430_20.2.2.LTS/include/machine/_limits.h -main.obj: C:/TI_CCS/ccs/tools/compiler/ti-cgt-msp430_20.2.2.LTS/include/float.h +main.obj: C:/ti/ccsv6/ccs_base/msp430/include/msp430.h +main.obj: C:/ti/ccsv6/ccs_base/msp430/include/msp430f5438a.h +main.obj: C:/ti/ccsv6/ccs_base/msp430/include/in430.h +main.obj: C:/ti/ccsv6/tools/compiler/msp430_15.12.3.LTS/include/intrinsics.h +main.obj: C:/ti/ccsv6/tools/compiler/msp430_15.12.3.LTS/include/intrinsics_legacy_undefs.h +main.obj: C:/ti/ccsv6/tools/compiler/msp430_15.12.3.LTS/include/stdio.h +main.obj: C:/ti/ccsv6/tools/compiler/msp430_15.12.3.LTS/include/linkage.h +main.obj: C:/ti/ccsv6/tools/compiler/msp430_15.12.3.LTS/include/stdarg.h +main.obj: C:/ti/ccsv6/tools/compiler/msp430_15.12.3.LTS/include/stdlib.h +main.obj: C:/ti/ccsv6/ccs_base/msp430/include/msp430x54xa.h +main.obj: C:/ti/ccsv6/tools/compiler/msp430_15.12.3.LTS/include/ctype.h +main.obj: C:/ti/ccsv6/tools/compiler/msp430_15.12.3.LTS/include/_isfuncdcl.h +main.obj: C:/ti/ccsv6/tools/compiler/msp430_15.12.3.LTS/include/string.h +main.obj: C:/ti/ccsv6/tools/compiler/msp430_15.12.3.LTS/include/math.h +main.obj: C:/ti/ccsv6/tools/compiler/msp430_15.12.3.LTS/include/_defs.h +main.obj: C:/ti/ccsv6/tools/compiler/msp430_15.12.3.LTS/include/float.h main.obj: ../SunseekerTelemetry2021.h +main.obj: C:/ti/ccsv6/tools/compiler/msp430_15.12.3.LTS/include/stdio.h ../main.c: -C:/TI_CCS/ccs/ccs_base/msp430/include/msp430.h: -C:/TI_CCS/ccs/ccs_base/msp430/include/msp430f5438a.h: -C:/TI_CCS/ccs/ccs_base/msp430/include/in430.h: -C:/TI_CCS/ccs/tools/compiler/ti-cgt-msp430_20.2.2.LTS/include/intrinsics.h: -C:/TI_CCS/ccs/tools/compiler/ti-cgt-msp430_20.2.2.LTS/include/intrinsics_legacy_undefs.h: -C:/TI_CCS/ccs/tools/compiler/ti-cgt-msp430_20.2.2.LTS/include/stdio.h: -C:/TI_CCS/ccs/tools/compiler/ti-cgt-msp430_20.2.2.LTS/include/_ti_config.h: -C:/TI_CCS/ccs/tools/compiler/ti-cgt-msp430_20.2.2.LTS/include/linkage.h: -C:/TI_CCS/ccs/tools/compiler/ti-cgt-msp430_20.2.2.LTS/include/stdarg.h: -C:/TI_CCS/ccs/tools/compiler/ti-cgt-msp430_20.2.2.LTS/include/sys/_types.h: -C:/TI_CCS/ccs/tools/compiler/ti-cgt-msp430_20.2.2.LTS/include/sys/cdefs.h: -C:/TI_CCS/ccs/tools/compiler/ti-cgt-msp430_20.2.2.LTS/include/machine/_types.h: -C:/TI_CCS/ccs/tools/compiler/ti-cgt-msp430_20.2.2.LTS/include/stdlib.h: -C:/TI_CCS/ccs/ccs_base/msp430/include/msp430x54xa.h: -C:/TI_CCS/ccs/tools/compiler/ti-cgt-msp430_20.2.2.LTS/include/ctype.h: -C:/TI_CCS/ccs/tools/compiler/ti-cgt-msp430_20.2.2.LTS/include/_isfuncdcl.h: -C:/TI_CCS/ccs/tools/compiler/ti-cgt-msp430_20.2.2.LTS/include/string.h: -C:/TI_CCS/ccs/tools/compiler/ti-cgt-msp430_20.2.2.LTS/include/math.h: -C:/TI_CCS/ccs/tools/compiler/ti-cgt-msp430_20.2.2.LTS/include/_defs.h: -C:/TI_CCS/ccs/tools/compiler/ti-cgt-msp430_20.2.2.LTS/include/machine/_limits.h: -C:/TI_CCS/ccs/tools/compiler/ti-cgt-msp430_20.2.2.LTS/include/float.h: +C:/ti/ccsv6/ccs_base/msp430/include/msp430.h: +C:/ti/ccsv6/ccs_base/msp430/include/msp430f5438a.h: +C:/ti/ccsv6/ccs_base/msp430/include/in430.h: +C:/ti/ccsv6/tools/compiler/msp430_15.12.3.LTS/include/intrinsics.h: +C:/ti/ccsv6/tools/compiler/msp430_15.12.3.LTS/include/intrinsics_legacy_undefs.h: +C:/ti/ccsv6/tools/compiler/msp430_15.12.3.LTS/include/stdio.h: +C:/ti/ccsv6/tools/compiler/msp430_15.12.3.LTS/include/linkage.h: +C:/ti/ccsv6/tools/compiler/msp430_15.12.3.LTS/include/stdarg.h: +C:/ti/ccsv6/tools/compiler/msp430_15.12.3.LTS/include/stdlib.h: +C:/ti/ccsv6/ccs_base/msp430/include/msp430x54xa.h: +C:/ti/ccsv6/tools/compiler/msp430_15.12.3.LTS/include/ctype.h: +C:/ti/ccsv6/tools/compiler/msp430_15.12.3.LTS/include/_isfuncdcl.h: +C:/ti/ccsv6/tools/compiler/msp430_15.12.3.LTS/include/string.h: +C:/ti/ccsv6/tools/compiler/msp430_15.12.3.LTS/include/math.h: +C:/ti/ccsv6/tools/compiler/msp430_15.12.3.LTS/include/_defs.h: +C:/ti/ccsv6/tools/compiler/msp430_15.12.3.LTS/include/float.h: ../SunseekerTelemetry2021.h: +C:/ti/ccsv6/tools/compiler/msp430_15.12.3.LTS/include/stdio.h: diff --git a/Telem_Debug/Debug1/Debug/main.obj b/Telem_Debug/Debug1/Debug/main.obj index 6bfbe06..777bd36 100644 Binary files a/Telem_Debug/Debug1/Debug/main.obj and b/Telem_Debug/Debug1/Debug/main.obj differ diff --git a/Telem_Debug/Debug1/Debug/makefile b/Telem_Debug/Debug1/Debug/makefile index c4be1e1..d073b0b 100644 --- a/Telem_Debug/Debug1/Debug/makefile +++ b/Telem_Debug/Debug1/Debug/makefile @@ -4,7 +4,7 @@ SHELL = cmd.exe -CG_TOOL_ROOT := C:/TI_CCS/ccs/tools/compiler/ti-cgt-msp430_20.2.2.LTS +CG_TOOL_ROOT := C:/ti/ccsv6/tools/compiler/msp430_15.12.3.LTS GEN_OPTS__FLAG := GEN_CMDS__FLAG := @@ -29,93 +29,93 @@ RMDIR := RMDIR /S/Q -include objects.mk ifneq ($(MAKECMDGOALS),clean) -ifneq ($(strip $(C55_DEPS)),) --include $(C55_DEPS) -endif -ifneq ($(strip $(C_UPPER_DEPS)),) --include $(C_UPPER_DEPS) -endif -ifneq ($(strip $(S67_DEPS)),) --include $(S67_DEPS) -endif -ifneq ($(strip $(S62_DEPS)),) --include $(S62_DEPS) -endif ifneq ($(strip $(S_DEPS)),) -include $(S_DEPS) endif -ifneq ($(strip $(OPT_DEPS)),) --include $(OPT_DEPS) -endif -ifneq ($(strip $(C??_DEPS)),) --include $(C??_DEPS) -endif -ifneq ($(strip $(ASM_UPPER_DEPS)),) --include $(ASM_UPPER_DEPS) -endif -ifneq ($(strip $(S??_DEPS)),) --include $(S??_DEPS) -endif -ifneq ($(strip $(C64_DEPS)),) --include $(C64_DEPS) -endif -ifneq ($(strip $(CXX_DEPS)),) --include $(CXX_DEPS) -endif -ifneq ($(strip $(S64_DEPS)),) --include $(S64_DEPS) -endif -ifneq ($(strip $(INO_DEPS)),) --include $(INO_DEPS) -endif -ifneq ($(strip $(CLA_DEPS)),) --include $(CLA_DEPS) -endif -ifneq ($(strip $(S55_DEPS)),) --include $(S55_DEPS) -endif -ifneq ($(strip $(SV7A_DEPS)),) --include $(SV7A_DEPS) -endif -ifneq ($(strip $(C62_DEPS)),) --include $(C62_DEPS) -endif -ifneq ($(strip $(C67_DEPS)),) --include $(C67_DEPS) -endif -ifneq ($(strip $(PDE_DEPS)),) --include $(PDE_DEPS) -endif -ifneq ($(strip $(K_DEPS)),) --include $(K_DEPS) -endif -ifneq ($(strip $(C_DEPS)),) --include $(C_DEPS) -endif -ifneq ($(strip $(CC_DEPS)),) --include $(CC_DEPS) -endif -ifneq ($(strip $(C++_DEPS)),) --include $(C++_DEPS) -endif -ifneq ($(strip $(C43_DEPS)),) --include $(C43_DEPS) -endif -ifneq ($(strip $(S43_DEPS)),) --include $(S43_DEPS) -endif -ifneq ($(strip $(ASM_DEPS)),) --include $(ASM_DEPS) -endif ifneq ($(strip $(S_UPPER_DEPS)),) -include $(S_UPPER_DEPS) endif +ifneq ($(strip $(S62_DEPS)),) +-include $(S62_DEPS) +endif +ifneq ($(strip $(C64_DEPS)),) +-include $(C64_DEPS) +endif +ifneq ($(strip $(ASM_DEPS)),) +-include $(ASM_DEPS) +endif +ifneq ($(strip $(CC_DEPS)),) +-include $(CC_DEPS) +endif +ifneq ($(strip $(SV7A_DEPS)),) +-include $(SV7A_DEPS) +endif +ifneq ($(strip $(S55_DEPS)),) +-include $(S55_DEPS) +endif +ifneq ($(strip $(C67_DEPS)),) +-include $(C67_DEPS) +endif +ifneq ($(strip $(CLA_DEPS)),) +-include $(CLA_DEPS) +endif +ifneq ($(strip $(C??_DEPS)),) +-include $(C??_DEPS) +endif ifneq ($(strip $(CPP_DEPS)),) -include $(CPP_DEPS) endif +ifneq ($(strip $(S??_DEPS)),) +-include $(S??_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +ifneq ($(strip $(C62_DEPS)),) +-include $(C62_DEPS) +endif +ifneq ($(strip $(CXX_DEPS)),) +-include $(CXX_DEPS) +endif +ifneq ($(strip $(C++_DEPS)),) +-include $(C++_DEPS) +endif +ifneq ($(strip $(ASM_UPPER_DEPS)),) +-include $(ASM_UPPER_DEPS) +endif +ifneq ($(strip $(K_DEPS)),) +-include $(K_DEPS) +endif +ifneq ($(strip $(C43_DEPS)),) +-include $(C43_DEPS) +endif +ifneq ($(strip $(INO_DEPS)),) +-include $(INO_DEPS) +endif +ifneq ($(strip $(S67_DEPS)),) +-include $(S67_DEPS) +endif ifneq ($(strip $(SA_DEPS)),) -include $(SA_DEPS) endif +ifneq ($(strip $(S43_DEPS)),) +-include $(S43_DEPS) +endif +ifneq ($(strip $(OPT_DEPS)),) +-include $(OPT_DEPS) +endif +ifneq ($(strip $(PDE_DEPS)),) +-include $(PDE_DEPS) +endif +ifneq ($(strip $(S64_DEPS)),) +-include $(S64_DEPS) +endif +ifneq ($(strip $(C_UPPER_DEPS)),) +-include $(C_UPPER_DEPS) +endif +ifneq ($(strip $(C55_DEPS)),) +-include $(C55_DEPS) +endif endif -include ../makefile.defs @@ -139,24 +139,23 @@ all: Debug1.out # Tool invocations Debug1.out: $(OBJS) $(CMD_SRCS) $(GEN_CMDS) - @echo 'Building target: "$@"' + @echo 'Building target: $@' @echo 'Invoking: MSP430 Linker' - "C:/TI_CCS/ccs/tools/compiler/ti-cgt-msp430_20.2.2.LTS/bin/cl430" -vmspx --data_model=restricted --use_hw_mpy=F5 --advice:power=all -g --define=__MSP430F5438A__ --display_error_number --diag_wrap=off --diag_warning=225 --silicon_errata=CPU21 --silicon_errata=CPU22 --silicon_errata=CPU23 --silicon_errata=CPU40 --printf_support=minimal -z -m"Debug1.map" --heap_size=160 --stack_size=160 --cinit_hold_wdt=on -i"C:/TI_CCS/ccs/ccs_base/msp430/include" -i"C:/TI_CCS/ccs/ccs_base/msp430/lib/5xx_6xx_FRxx" -i"C:/TI_CCS/ccs/tools/compiler/ti-cgt-msp430_20.2.2.LTS/lib" -i"C:/TI_CCS/ccs/tools/compiler/ti-cgt-msp430_20.2.2.LTS/include" --reread_libs --display_error_number --diag_wrap=off --warn_sections --xml_link_info="Debug1_linkInfo.xml" --use_hw_mpy=F5 --rom_model -o "Debug1.out" $(ORDERED_OBJS) - @echo 'Finished building target: "$@"' + "C:/ti/ccsv6/tools/compiler/msp430_15.12.3.LTS/bin/cl430" -vmspx --data_model=restricted --use_hw_mpy=F5 --advice:power=all -g --define=__MSP430F5438A__ --diag_warning=225 --diag_wrap=off --display_error_number --silicon_errata=CPU21 --silicon_errata=CPU22 --silicon_errata=CPU23 --silicon_errata=CPU40 --printf_support=minimal -z -m"Debug1.map" --stack_size=160 --heap_size=160 --cinit_hold_wdt=on -i"C:/ti/ccsv6/ccs_base/msp430/include" -i"C:/ti/ccsv6/ccs_base/msp430/lib/5xx_6xx_FRxx" -i"C:/ti/ccsv6/tools/compiler/msp430_15.12.3.LTS/lib" -i"C:/ti/ccsv6/tools/compiler/msp430_15.12.3.LTS/include" --reread_libs --warn_sections --display_error_number --diag_wrap=off --xml_link_info="Debug1_linkInfo.xml" --use_hw_mpy=F5 --rom_model -o "Debug1.out" $(ORDERED_OBJS) + @echo 'Finished building target: $@' @echo ' ' Debug1.hex: $(EXE_OUTPUTS) - @echo 'Building files: $(strip $(EXE_OUTPUTS__QUOTED))' @echo 'Invoking: MSP430 Hex Utility' - "C:/TI_CCS/ccs/tools/compiler/ti-cgt-msp430_20.2.2.LTS/bin/hex430" --memwidth=8 --romwidth=8 --diag_wrap=off -o "Debug1.hex" $(EXE_OUTPUTS__QUOTED) - @echo 'Finished building: $(strip $(EXE_OUTPUTS__QUOTED))' + "C:/ti/ccsv6/tools/compiler/msp430_15.12.3.LTS/bin/hex430" --memwidth=8 --romwidth=8 -o "Debug1.hex" $(EXE_OUTPUTS__QUOTED) + @echo 'Finished building: $@' @echo ' ' # Other Targets clean: - -$(RM) $(BIN_OUTPUTS__QUOTED)$(EXE_OUTPUTS__QUOTED) - -$(RM) "clock_init.obj" "main.obj" + -$(RM) $(EXE_OUTPUTS__QUOTED)$(BIN_OUTPUTS__QUOTED) -$(RM) "clock_init.d" "main.d" + -$(RM) "clock_init.obj" "main.obj" -@echo 'Finished clean' -@echo ' ' diff --git a/Telem_Debug/Debug1/Debug/sources.mk b/Telem_Debug/Debug1/Debug/sources.mk index fb4f5d4..49ec9b1 100644 --- a/Telem_Debug/Debug1/Debug/sources.mk +++ b/Telem_Debug/Debug1/Debug/sources.mk @@ -2,112 +2,112 @@ # Automatically-generated file. Do not edit! ################################################################################ -C55_SRCS := -A_SRCS := -ASM_UPPER_SRCS := -EXE_SRCS := -LDS_UPPER_SRCS := -CPP_SRCS := -CMD_SRCS := O_SRCS := -ELF_SRCS := -C??_SRCS := -C64_SRCS := -C67_SRCS := -SA_SRCS := -S64_SRCS := -OPT_SRCS := -CXX_SRCS := -S67_SRCS := -S??_SRCS := -PDE_SRCS := -SV7A_SRCS := +CPP_SRCS := K_SRCS := -CLA_SRCS := +LD_SRCS := +S67_SRCS := +LDS_SRCS := +CMD_SRCS := +EXE_SRCS := +CXX_SRCS := +CMD_UPPER_SRCS := +ELF_SRCS := +C43_SRCS := S55_SRCS := LD_UPPER_SRCS := +C62_SRCS := +S_UPPER_SRCS := +A_SRCS := +SA_SRCS := +C55_SRCS := +LDS_UPPER_SRCS := +C_UPPER_SRCS := OUT_SRCS := INO_SRCS := -LIB_SRCS := -ASM_SRCS := -S_UPPER_SRCS := -S43_SRCS := -LD_SRCS := -CMD_UPPER_SRCS := -C_UPPER_SRCS := -C++_SRCS := -C43_SRCS := OBJ_SRCS := -LDS_SRCS := -S_SRCS := -CC_SRCS := S62_SRCS := -C62_SRCS := +LIB_SRCS := +PDE_SRCS := +SV7A_SRCS := +ASM_SRCS := +ASM_UPPER_SRCS := +C++_SRCS := +CLA_SRCS := +S??_SRCS := C_SRCS := -C55_DEPS := -C_UPPER_DEPS := -S67_DEPS := -S62_DEPS := -S_DEPS := -OPT_DEPS := -C??_DEPS := -ASM_UPPER_DEPS := -S??_DEPS := -C64_DEPS := -CXX_DEPS := -S64_DEPS := -INO_DEPS := -CLA_DEPS := -S55_DEPS := -SV7A_DEPS := -EXE_OUTPUTS := -C62_DEPS := -C67_DEPS := -PDE_DEPS := -K_DEPS := -C_DEPS := -CC_DEPS := -BIN_OUTPUTS := -C++_DEPS := -C43_DEPS := -S43_DEPS := +C67_SRCS := +S_SRCS := +S43_SRCS := +OPT_SRCS := +C64_SRCS := +CC_SRCS := +C??_SRCS := +S64_SRCS := OBJS := -ASM_DEPS := +BIN_OUTPUTS := +S_DEPS := S_UPPER_DEPS := +S62_DEPS := +C64_DEPS := +ASM_DEPS := +CC_DEPS := +SV7A_DEPS := +S55_DEPS := +C67_DEPS := +CLA_DEPS := +C??_DEPS := CPP_DEPS := +S??_DEPS := +C_DEPS := +C62_DEPS := +EXE_OUTPUTS := +CXX_DEPS := +C++_DEPS := +ASM_UPPER_DEPS := +K_DEPS := +C43_DEPS := +INO_DEPS := +S67_DEPS := SA_DEPS := -C++_DEPS__QUOTED := -OPT_DEPS__QUOTED := -S_UPPER_DEPS__QUOTED := -SA_DEPS__QUOTED := -C??_DEPS__QUOTED := -S67_DEPS__QUOTED := -C55_DEPS__QUOTED := -CC_DEPS__QUOTED := -ASM_UPPER_DEPS__QUOTED := -SV7A_DEPS__QUOTED := -S??_DEPS__QUOTED := -OBJS__QUOTED := +S43_DEPS := +OPT_DEPS := +PDE_DEPS := +S64_DEPS := +C_UPPER_DEPS := +C55_DEPS := +CPP_DEPS__QUOTED := C67_DEPS__QUOTED := -K_DEPS__QUOTED := -S55_DEPS__QUOTED := INO_DEPS__QUOTED := +C??_DEPS__QUOTED := +S_UPPER_DEPS__QUOTED := +CLA_DEPS__QUOTED := +ASM_UPPER_DEPS__QUOTED := C62_DEPS__QUOTED := +CXX_DEPS__QUOTED := +EXE_OUTPUTS__QUOTED := +S67_DEPS__QUOTED := +BIN_OUTPUTS__QUOTED := C_DEPS__QUOTED := C_UPPER_DEPS__QUOTED := -C43_DEPS__QUOTED := -CPP_DEPS__QUOTED := -BIN_OUTPUTS__QUOTED := -C64_DEPS__QUOTED := -CXX_DEPS__QUOTED := -CLA_DEPS__QUOTED := +OPT_DEPS__QUOTED := S_DEPS__QUOTED := -ASM_DEPS__QUOTED := +K_DEPS__QUOTED := +S??_DEPS__QUOTED := +C64_DEPS__QUOTED := +C++_DEPS__QUOTED := +OBJS__QUOTED := +CC_DEPS__QUOTED := S43_DEPS__QUOTED := -EXE_OUTPUTS__QUOTED := -S64_DEPS__QUOTED := -S62_DEPS__QUOTED := +S55_DEPS__QUOTED := +SA_DEPS__QUOTED := +C55_DEPS__QUOTED := PDE_DEPS__QUOTED := +C43_DEPS__QUOTED := +S62_DEPS__QUOTED := +ASM_DEPS__QUOTED := +SV7A_DEPS__QUOTED := +S64_DEPS__QUOTED := # Every subdirectory with source files must be described here SUBDIRS := \ diff --git a/Telem_Debug/Debug1/Debug/subdir_rules.mk b/Telem_Debug/Debug1/Debug/subdir_rules.mk index ae46fc5..936ac56 100644 --- a/Telem_Debug/Debug1/Debug/subdir_rules.mk +++ b/Telem_Debug/Debug1/Debug/subdir_rules.mk @@ -2,14 +2,19 @@ # Automatically-generated file. Do not edit! ################################################################################ -SHELL = cmd.exe - # Each subdirectory must supply rules for building sources it contributes -%.obj: ../%.c $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) - @echo 'Building file: "$<"' +clock_init.obj: ../clock_init.c $(GEN_OPTS) | $(GEN_HDRS) + @echo 'Building file: $<' @echo 'Invoking: MSP430 Compiler' - "C:/TI_CCS/ccs/tools/compiler/ti-cgt-msp430_20.2.2.LTS/bin/cl430" -vmspx --data_model=restricted --use_hw_mpy=F5 --include_path="C:/TI_CCS/ccs/ccs_base/msp430/include" --include_path="C:/TI_CCS/ccs/tools/compiler/ti-cgt-msp430_20.2.2.LTS/include" --advice:power=all -g --define=__MSP430F5438A__ --display_error_number --diag_wrap=off --diag_warning=225 --silicon_errata=CPU21 --silicon_errata=CPU22 --silicon_errata=CPU23 --silicon_errata=CPU40 --printf_support=minimal --preproc_with_compile --preproc_dependency="$(basename $(