From 8beec99a2dd63f76d5ad0f8eeceeca8562193f89 Mon Sep 17 00:00:00 2001 From: William Miceli Date: Fri, 14 May 2021 15:30:32 -0400 Subject: [PATCH] Comment fixes/consistency improvements --- Telem_Debug/Debug1/clock_init.c | 81 ++++++++++++++++----------------- Telem_Debug/Debug2/clock_init.c | 81 ++++++++++++++++----------------- Telem_Debug/Debug3/clock_init.c | 81 ++++++++++++++++----------------- 3 files changed, 120 insertions(+), 123 deletions(-) diff --git a/Telem_Debug/Debug1/clock_init.c b/Telem_Debug/Debug1/clock_init.c index beff487..5c57f4e 100644 --- a/Telem_Debug/Debug1/clock_init.c +++ b/Telem_Debug/Debug1/clock_init.c @@ -24,74 +24,74 @@ void SetVCoreUp(unsigned int level); void clock_init(void) { - WDTCTL = WDTPW + WDTHOLD; //Stop watchdog timer + WDTCTL = WDTPW + WDTHOLD; //Stop watchdog timer - Port_Init(); //ensure clock pins are configured - - SetVCoreUp(1); //Configure MCU core voltage for HF clock - SetVCoreUp(2); // - SetVCoreUp(3); // + Port_Init(); //ensure clock pins are configured - Clock_XT1_Init(); //LF clock source init - Clock_XT2_Init(); //HF clock source init + SetVCoreUp(1); //Configure MCU core voltage for HF clock + SetVCoreUp(2); // + SetVCoreUp(3); // + + Clock_XT1_Init(); //LF clock source init + Clock_XT2_Init(); //HF clock source init } void Port_Init(void) { - //Clock Source TEST PINS ACLK/MCLK/SMCLK - P11DIR |= (1 << 0) | (1 << 1) | (1 << 2); //set P11.0:P11.2 as output ACLK/MCLK/SMCLK + //Clock Source TEST PINS ACLK/MCLK/SMCLK + P11DIR |= (1 << 0) | (1 << 1) | (1 << 2); //set P11.0:P11.2 as output ACLK/MCLK/SMCLK P11SEL |= (1 << 0) | (1 << 1) | (1 << 2); //set P11.0:P11.2 as ACLK/MCLK/SMCLK function - //XT1 ALTERNATE PIN CONFIG - P7SEL |= (1 << 0) | (1 << 1); //set P7.0 & P7.1 as XT1IN/XT1OUT periph - P7DIR |= (1 << 0) | (1 << 1); + //XT1 ALTERNATE PIN CONFIG + P7SEL |= (1 << 0) | (1 << 1); //set P7.0 & P7.1 as XT1IN/XT1OUT peripheral + P7DIR |= (1 << 0) | (1 << 1); - //XT2 ALTERNATE PIN CONFIG - P5SEL |= (1 << 2) | (1 << 3); //set P5.2 & P5.3 as XT2IN/XT2OUT periph + //XT2 ALTERNATE PIN CONFIG + P5SEL |= (1 << 2) | (1 << 3); //set P5.2 & P5.3 as XT2IN/XT2OUT peripheral P5DIR |= (1 << 2) | (1 << 3); } void Clock_XT1_Init(void) { - char i; + char i; - //XT1 CLOCK CONFIG - UCSCTL6 &= ~(XT1OFF); //Enable XT1 - UCSCTL6 &= ~(XT1DRIVE1 | XT1DRIVE0); //lowest drive current LF 32KHz oscillator + //XT1 CLOCK CONFIG + UCSCTL6 &= ~(XT1OFF); //Enable XT1 + UCSCTL6 &= ~(XT1DRIVE1 | XT1DRIVE0); //lowest drive current LF 32KHz oscillator - do - { - UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);//Clear XT2,XT1,DCO fault flags - SFRIFG1 &= ~OFIFG; //Clear fault flags - for(i=255;i>0;i--); //Delay for Osc to stabilize - } - while ((SFRIFG1 & OFIFG) != 0); //Test oscillator fault flag + do + { + UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);//Clear XT2,XT1,DCO fault flags + SFRIFG1 &= ~OFIFG; //Clear fault flags + for(i=255;i>0;i--); //Delay for Osc to stabilize + } + while ((SFRIFG1 & OFIFG) != 0); //Test oscillator fault flag - UCSCTL4 |= SELA__XT1CLK; //Clock Source ACLK = XT1 = 32kHz - UCSCTL5 |= DIVA_0; //Divide ACLK/1 = 32kHz + UCSCTL4 |= SELA__XT1CLK; //Clock Source ACLK = XT1 = 32kHz + UCSCTL5 |= DIVA_0; //Divide ACLK/1 = 32kHz } void Clock_XT2_Init(void) { - char i; + char i; - //XT2 CLOCK CONFIG - UCSCTL6 &= ~(XT2OFF); //Enable XT2 - UCSCTL6 |= XT2DRIVE_3; //Drive current 16-24 MHz Clock - UCSCTL6 &= ~XT2BYPASS; //XT2 Sourced Externally from pin - 16MHz + //XT2 CLOCK CONFIG + UCSCTL6 &= ~(XT2OFF); //Enable XT2 + UCSCTL6 |= XT2DRIVE_3; //Drive current 16-24 MHz Clock + UCSCTL6 &= ~XT2BYPASS; //XT2 Sourced Externally from pin - 20MHz do - { - UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);//Clear XT2,XT1,DCO fault flags - SFRIFG1 &= ~OFIFG; //Clear fault flags - for(i=255;i>0;i--); //Delay for Osc to stabilize - } + { + UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);//Clear XT2,XT1,DCO fault flags + SFRIFG1 &= ~OFIFG; //Clear fault flags + for(i=255;i>0;i--); //Delay for Osc to stabilize + } while ((SFRIFG1 & OFIFG) != 0); //Test oscillator fault flag - UCSCTL4 |= (SELS__XT2CLK | SELM__XT2CLK);//Clock Source SMCLK=MCLK = XT2 = 16MHz - UCSCTL5 |= DIVM_0 | DIVS_1; //MCLK:XT2/1 = 16MHz SMCLK:XT2/2 = 8MHz + UCSCTL4 |= (SELS__XT2CLK | SELM__XT2CLK);//Clock Source SMCLK=MCLK = XT2 = 20MHz + UCSCTL5 |= DIVM_0 | DIVS_1; //MCLK:XT2/1 = 20MHz SMCLK:XT2/2 = 10MHz } @@ -127,4 +127,3 @@ void SetVCoreUp (unsigned int level) // Lock PMM registers for write access PMMCTL0_H = 0x00; } - diff --git a/Telem_Debug/Debug2/clock_init.c b/Telem_Debug/Debug2/clock_init.c index a41ecf2..5c57f4e 100644 --- a/Telem_Debug/Debug2/clock_init.c +++ b/Telem_Debug/Debug2/clock_init.c @@ -24,74 +24,74 @@ void SetVCoreUp(unsigned int level); void clock_init(void) { - WDTCTL = WDTPW + WDTHOLD; //Stop watchdog timer + WDTCTL = WDTPW + WDTHOLD; //Stop watchdog timer - Port_Init(); //ensure clock pins are configured - - SetVCoreUp(1); //Configure MCU core voltage for HF clock - SetVCoreUp(2); // - SetVCoreUp(3); // + Port_Init(); //ensure clock pins are configured - Clock_XT1_Init(); //LF clock source init - Clock_XT2_Init(); //HF clock source init + SetVCoreUp(1); //Configure MCU core voltage for HF clock + SetVCoreUp(2); // + SetVCoreUp(3); // + + Clock_XT1_Init(); //LF clock source init + Clock_XT2_Init(); //HF clock source init } void Port_Init(void) { - //Clock Source TEST PINS ACLK/MCLK/SMCLK - P11DIR |= (1 << 0) | (1 << 1) | (1 << 2); //set P11.0:P11.2 as output ACLK/MCLK/SMCLK + //Clock Source TEST PINS ACLK/MCLK/SMCLK + P11DIR |= (1 << 0) | (1 << 1) | (1 << 2); //set P11.0:P11.2 as output ACLK/MCLK/SMCLK P11SEL |= (1 << 0) | (1 << 1) | (1 << 2); //set P11.0:P11.2 as ACLK/MCLK/SMCLK function - //XT1 ALTERNATE PIN CONFIG - P7SEL |= (1 << 0) | (1 << 1); //set P7.0 & P7.1 as XT1IN/XT1OUT periph - P7DIR |= (1 << 0) | (1 << 1); + //XT1 ALTERNATE PIN CONFIG + P7SEL |= (1 << 0) | (1 << 1); //set P7.0 & P7.1 as XT1IN/XT1OUT peripheral + P7DIR |= (1 << 0) | (1 << 1); - //XT2 ALTERNATE PIN CONFIG - P5SEL |= (1 << 2) | (1 << 3); //set P5.2 & P5.3 as XT2IN/XT2OUT periph + //XT2 ALTERNATE PIN CONFIG + P5SEL |= (1 << 2) | (1 << 3); //set P5.2 & P5.3 as XT2IN/XT2OUT peripheral P5DIR |= (1 << 2) | (1 << 3); } void Clock_XT1_Init(void) { - char i; + char i; - //XT1 CLOCK CONFIG - UCSCTL6 &= ~(XT1OFF); //Enable XT1 - UCSCTL6 &= ~(XT1DRIVE1 | XT1DRIVE0); //lowest drive current LF 32KHz oscillator + //XT1 CLOCK CONFIG + UCSCTL6 &= ~(XT1OFF); //Enable XT1 + UCSCTL6 &= ~(XT1DRIVE1 | XT1DRIVE0); //lowest drive current LF 32KHz oscillator - do - { - UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);//Clear XT2,XT1,DCO fault flags - SFRIFG1 &= ~OFIFG; //Clear fault flags - for(i=255;i>0;i--); //Delay for Osc to stabilize - } - while ((SFRIFG1 & OFIFG) != 0); //Test oscillator fault flag + do + { + UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);//Clear XT2,XT1,DCO fault flags + SFRIFG1 &= ~OFIFG; //Clear fault flags + for(i=255;i>0;i--); //Delay for Osc to stabilize + } + while ((SFRIFG1 & OFIFG) != 0); //Test oscillator fault flag - UCSCTL4 |= SELA__XT1CLK; //Clock Source ACLK = XT1 = 32kHz - UCSCTL5 |= DIVA_0; //Divide ACLK/1 = 32kHz + UCSCTL4 |= SELA__XT1CLK; //Clock Source ACLK = XT1 = 32kHz + UCSCTL5 |= DIVA_0; //Divide ACLK/1 = 32kHz } void Clock_XT2_Init(void) { - char i; + char i; - //XT2 CLOCK CONFIG - UCSCTL6 &= ~(XT2OFF); //Enable XT2 - UCSCTL6 |= XT2DRIVE_3; //Drive current 16-24 MHz Clock - UCSCTL6 &= ~XT2BYPASS; //XT2 Sourced Externally from pin - 20MHz + //XT2 CLOCK CONFIG + UCSCTL6 &= ~(XT2OFF); //Enable XT2 + UCSCTL6 |= XT2DRIVE_3; //Drive current 16-24 MHz Clock + UCSCTL6 &= ~XT2BYPASS; //XT2 Sourced Externally from pin - 20MHz do - { - UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);//Clear XT2,XT1,DCO fault flags - SFRIFG1 &= ~OFIFG; //Clear fault flags - for(i=255;i>0;i--); //Delay for Osc to stabilize - } + { + UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);//Clear XT2,XT1,DCO fault flags + SFRIFG1 &= ~OFIFG; //Clear fault flags + for(i=255;i>0;i--); //Delay for Osc to stabilize + } while ((SFRIFG1 & OFIFG) != 0); //Test oscillator fault flag - UCSCTL4 |= (SELS__XT2CLK | SELM__XT2CLK);//Clock Source SMCLK=MCLK = XT2 = 20MHz - UCSCTL5 |= DIVM_0 | DIVS_1; //MCLK:XT2/1 = 20MHz SMCLK:XT2/2 = 10MHz + UCSCTL4 |= (SELS__XT2CLK | SELM__XT2CLK);//Clock Source SMCLK=MCLK = XT2 = 20MHz + UCSCTL5 |= DIVM_0 | DIVS_1; //MCLK:XT2/1 = 20MHz SMCLK:XT2/2 = 10MHz } @@ -127,4 +127,3 @@ void SetVCoreUp (unsigned int level) // Lock PMM registers for write access PMMCTL0_H = 0x00; } - diff --git a/Telem_Debug/Debug3/clock_init.c b/Telem_Debug/Debug3/clock_init.c index a41ecf2..5c57f4e 100644 --- a/Telem_Debug/Debug3/clock_init.c +++ b/Telem_Debug/Debug3/clock_init.c @@ -24,74 +24,74 @@ void SetVCoreUp(unsigned int level); void clock_init(void) { - WDTCTL = WDTPW + WDTHOLD; //Stop watchdog timer + WDTCTL = WDTPW + WDTHOLD; //Stop watchdog timer - Port_Init(); //ensure clock pins are configured - - SetVCoreUp(1); //Configure MCU core voltage for HF clock - SetVCoreUp(2); // - SetVCoreUp(3); // + Port_Init(); //ensure clock pins are configured - Clock_XT1_Init(); //LF clock source init - Clock_XT2_Init(); //HF clock source init + SetVCoreUp(1); //Configure MCU core voltage for HF clock + SetVCoreUp(2); // + SetVCoreUp(3); // + + Clock_XT1_Init(); //LF clock source init + Clock_XT2_Init(); //HF clock source init } void Port_Init(void) { - //Clock Source TEST PINS ACLK/MCLK/SMCLK - P11DIR |= (1 << 0) | (1 << 1) | (1 << 2); //set P11.0:P11.2 as output ACLK/MCLK/SMCLK + //Clock Source TEST PINS ACLK/MCLK/SMCLK + P11DIR |= (1 << 0) | (1 << 1) | (1 << 2); //set P11.0:P11.2 as output ACLK/MCLK/SMCLK P11SEL |= (1 << 0) | (1 << 1) | (1 << 2); //set P11.0:P11.2 as ACLK/MCLK/SMCLK function - //XT1 ALTERNATE PIN CONFIG - P7SEL |= (1 << 0) | (1 << 1); //set P7.0 & P7.1 as XT1IN/XT1OUT periph - P7DIR |= (1 << 0) | (1 << 1); + //XT1 ALTERNATE PIN CONFIG + P7SEL |= (1 << 0) | (1 << 1); //set P7.0 & P7.1 as XT1IN/XT1OUT peripheral + P7DIR |= (1 << 0) | (1 << 1); - //XT2 ALTERNATE PIN CONFIG - P5SEL |= (1 << 2) | (1 << 3); //set P5.2 & P5.3 as XT2IN/XT2OUT periph + //XT2 ALTERNATE PIN CONFIG + P5SEL |= (1 << 2) | (1 << 3); //set P5.2 & P5.3 as XT2IN/XT2OUT peripheral P5DIR |= (1 << 2) | (1 << 3); } void Clock_XT1_Init(void) { - char i; + char i; - //XT1 CLOCK CONFIG - UCSCTL6 &= ~(XT1OFF); //Enable XT1 - UCSCTL6 &= ~(XT1DRIVE1 | XT1DRIVE0); //lowest drive current LF 32KHz oscillator + //XT1 CLOCK CONFIG + UCSCTL6 &= ~(XT1OFF); //Enable XT1 + UCSCTL6 &= ~(XT1DRIVE1 | XT1DRIVE0); //lowest drive current LF 32KHz oscillator - do - { - UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);//Clear XT2,XT1,DCO fault flags - SFRIFG1 &= ~OFIFG; //Clear fault flags - for(i=255;i>0;i--); //Delay for Osc to stabilize - } - while ((SFRIFG1 & OFIFG) != 0); //Test oscillator fault flag + do + { + UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);//Clear XT2,XT1,DCO fault flags + SFRIFG1 &= ~OFIFG; //Clear fault flags + for(i=255;i>0;i--); //Delay for Osc to stabilize + } + while ((SFRIFG1 & OFIFG) != 0); //Test oscillator fault flag - UCSCTL4 |= SELA__XT1CLK; //Clock Source ACLK = XT1 = 32kHz - UCSCTL5 |= DIVA_0; //Divide ACLK/1 = 32kHz + UCSCTL4 |= SELA__XT1CLK; //Clock Source ACLK = XT1 = 32kHz + UCSCTL5 |= DIVA_0; //Divide ACLK/1 = 32kHz } void Clock_XT2_Init(void) { - char i; + char i; - //XT2 CLOCK CONFIG - UCSCTL6 &= ~(XT2OFF); //Enable XT2 - UCSCTL6 |= XT2DRIVE_3; //Drive current 16-24 MHz Clock - UCSCTL6 &= ~XT2BYPASS; //XT2 Sourced Externally from pin - 20MHz + //XT2 CLOCK CONFIG + UCSCTL6 &= ~(XT2OFF); //Enable XT2 + UCSCTL6 |= XT2DRIVE_3; //Drive current 16-24 MHz Clock + UCSCTL6 &= ~XT2BYPASS; //XT2 Sourced Externally from pin - 20MHz do - { - UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);//Clear XT2,XT1,DCO fault flags - SFRIFG1 &= ~OFIFG; //Clear fault flags - for(i=255;i>0;i--); //Delay for Osc to stabilize - } + { + UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);//Clear XT2,XT1,DCO fault flags + SFRIFG1 &= ~OFIFG; //Clear fault flags + for(i=255;i>0;i--); //Delay for Osc to stabilize + } while ((SFRIFG1 & OFIFG) != 0); //Test oscillator fault flag - UCSCTL4 |= (SELS__XT2CLK | SELM__XT2CLK);//Clock Source SMCLK=MCLK = XT2 = 20MHz - UCSCTL5 |= DIVM_0 | DIVS_1; //MCLK:XT2/1 = 20MHz SMCLK:XT2/2 = 10MHz + UCSCTL4 |= (SELS__XT2CLK | SELM__XT2CLK);//Clock Source SMCLK=MCLK = XT2 = 20MHz + UCSCTL5 |= DIVM_0 | DIVS_1; //MCLK:XT2/1 = 20MHz SMCLK:XT2/2 = 10MHz } @@ -127,4 +127,3 @@ void SetVCoreUp (unsigned int level) // Lock PMM registers for write access PMMCTL0_H = 0x00; } -