From 8cd4c6962c05ed7cb23667a1aa4c648ed8d396d1 Mon Sep 17 00:00:00 2001 From: William Miceli Date: Mon, 7 Jun 2021 17:14:43 -0400 Subject: [PATCH] Initialization is complete --- Telem_Debug/Debug_UART-USB/usci.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/Telem_Debug/Debug_UART-USB/usci.c b/Telem_Debug/Debug_UART-USB/usci.c index 180c3ef..dd2722d 100644 --- a/Telem_Debug/Debug_UART-USB/usci.c +++ b/Telem_Debug/Debug_UART-USB/usci.c @@ -22,7 +22,6 @@ void usci_A0_init(void){ /******************************** USCI A1 ********************************/ /*************************************************************************/ - void usci_A1_init(void){ } @@ -32,7 +31,7 @@ void usci_A1_init(void){ /*************************************************************************/ void usci_A2_init(void){ - UCA2CTL1 |= UCSWRST; // Software Reset Enable - Set high, disabling the USCI module; Register options can only be set when the UCSWRST bit = 1 + UCA2CTL1 |= UCSWRST; // Software Reset Enable - Set high, disabling the USCI module; USCI configuration changes can only be made when the UCSWRST bit = 1 UCA2CTL1 &= ~0b11000000; // Reset both UCSSELx bits so the USCI Clock Source Select bits are more predictable UCA2CTL1 |= UCSSEL__SMCLK; // USCI Clock Source Select - SMCLK UCA2CTL1 &= ~UCRXEIE; // Receive Erroneous-Character Interrupt Enable - Disabled @@ -47,7 +46,11 @@ void usci_A2_init(void){ UCA2CTL0 &= ~UCMODE1; // USCI Mode [2 Bits Required] - UART mode selected UCA2CTL0 &= ~UCMODE0; // USCI Mode [2 Bits Required] - UART mode selected UCA2CTL0 &= ~UCSYNC; // Synchronous Mode Enable - Asynchronous mode selected - + UCA2BRW = 10; // Clock Prescalar + UCA2MCTL &= ~0b11111111; // Reset entire register + UCA2MCTL |= 0x0 << 4; // First Modulation Stage Select + UCA2MCTL |= 0x0 << 1; // Second Modulation Stage Select + UCA2MCTL |= 0x0; // Oversampling Mode Enable - Disabled } void usci_A2_enable(void){