101 lines
4.5 KiB
C
101 lines
4.5 KiB
C
#include "clock_init.h"
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void clock_init(void)
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{
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WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer; `WDTPW` is the "WatchDog Timer PassWord", required for all `WDTCTL` operations
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Port_Init(); //ensure clock pins are configured
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SetVCoreUp(1); //Configure MCU core voltage for HF clock
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SetVCoreUp(2); //
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SetVCoreUp(3); //
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Clock_XT1_Init(); //LF clock source init
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Clock_XT2_Init(); //HF clock source init
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}
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void Port_Init(void)
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{
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//Clock Source TEST PINS ACLK/MCLK/SMCLK
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P11DIR |= ACLK_TEST | MCLK_TEST | SMCLK_TEST; // Set P11.0:P11.2 as output ACLK/MCLK/SMCLK
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P11SEL |= ACLK_TEST | MCLK_TEST | SMCLK_TEST; // Set P11.0:P11.2 as ACLK/MCLK/SMCLK function
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//XT1 ALTERNATE PIN CONFIG
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P7SEL |= XT1IN | XT1OUT; // Set P7.0 & P7.1 as XT1IN/XT1OUT peripheral
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P7DIR |= XT1IN | XT1OUT;
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//XT2 ALTERNATE PIN CONFIG
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P5SEL |= XT2IN | XT2OUT; // Set P5.2 & P5.3 as XT2IN/XT2OUT peripheral
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P5DIR |= XT2IN | XT2OUT;
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}
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void Clock_XT1_Init(void)
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{
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char i;
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//XT1 CLOCK CONFIG
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UCSCTL6 &= ~(XT1OFF); // Enable XT1
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UCSCTL6 &= ~(XT1DRIVE1 | XT1DRIVE0); // Lowest drive current LF 32KHz oscillator
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do{
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UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG); // Clear XT2,XT1,DCO fault flags
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SFRIFG1 &= ~OFIFG; // Clear fault flags
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for(i=255;i>0;i--){ // Delay for oscillator to stabilize
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_NOP(); // "No Operation"
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}
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}
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while((SFRIFG1 & OFIFG) != 0); // Test oscillator fault flag
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UCSCTL4 |= SELA__XT1CLK; // Clock Source ACLK = XT1 = 32kHz
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UCSCTL5 |= DIVA_0; // Divide ACLK/1 = 32kHz
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}
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void Clock_XT2_Init(void)
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{
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char i;
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//XT2 CLOCK CONFIG
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UCSCTL6 &= ~(XT2OFF); // Enable XT2
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UCSCTL6 |= XT2DRIVE_3; // Drive current 16-24 MHz Clock
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UCSCTL6 &= ~XT2BYPASS; // XT2 Sourced Externally from pin - 20MHz
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do{
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UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG); // Clear XT2,XT1,DCO fault flags
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SFRIFG1 &= ~OFIFG; // Clear fault flags
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for(i=255;i>0;i--){ // Delay for oscillator to stabilize
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_NOP(); // "No Operation"
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}
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}
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while((SFRIFG1 & OFIFG) != 0); // Test oscillator fault flag
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UCSCTL4 |= (SELS__XT2CLK | SELM__XT2CLK); // Clock Source SMCLK=MCLK = XT2 = 20MHz
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UCSCTL5 |= DIVM_0 | DIVS_1; // MCLK:XT2/1 = 20MHz SMCLK:XT2/2 = 10MHz
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}
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/*************************************************************
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/ Name: SetVCoreUp
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/ IN: int Level
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/ OUT: void
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/ DESC: This function is used to set the voltage of the VCORE to
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/ The level specified in input
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/ Reference: Users Guide page 74
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************************************************************/
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void SetVCoreUp (unsigned int level)
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{
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PMMCTL0_H = 0xA5; // Open PMM registers for write access
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SVSMHCTL = SVSHE + SVSHRVL0 * level + SVMHE + SVSMHRRL0 * level; // Set SVS/SVM high side new level
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SVSMLCTL = SVSLE + SVMLE + SVSMLRRL0 * level; // Set SVM low side to new level
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while((PMMIFG & SVSMLDLYIFG) == 0); // Wait till SVM is settled
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PMMIFG &= ~(SVMLVLRIFG + SVMLIFG); // Clear already set flags
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PMMCTL0_L = PMMCOREV0 * level; // Set VCore to new level
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if(PMMIFG & SVMLIFG){
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while((PMMIFG & SVMLVLRIFG) == 0); // Wait till new level reached
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}
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SVSMLCTL = SVSLE + SVSLRVL0 * level + SVMLE + SVSMLRRL0 * level; // Set SVS/SVM low side to new level
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while((PMMIFG & SVSMLDLYIFG) == 0); // Wait till SVM is settled
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PMMCTL0_H = 0x00; // Lock PMM registers for write access
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}
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