131 lines
3.8 KiB
C
131 lines
3.8 KiB
C
/*
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* Clock Initialization Code MSP430F5438A
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* Initialize Clock Source XT1 @ 32768 Hz
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* Initialize Clock Source XT2 @ 20MHz
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*
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* Sunseeker Telemetry 2021
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*
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* Last modified October 2015 by Scott Haver
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* Last modified May 2021 by B. Bazuin
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*
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* Main CLK : MCLK = XT2 = 20 MHz
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* Sub-Main CLK : SMCLK = XT2/2 = 10 MHz
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* Aux CLK : ACLK = XT1 = 32.768 kHz
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*
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*/
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#include <msp430x54xa.h>
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void Port_Init(void);
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void Clock_XT1_Init(void);
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void Clock_XT2_Init(void);
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void SetVCoreUp(unsigned int level);
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void clock_init(void)
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{
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WDTCTL = WDTPW + WDTHOLD; //Stop watchdog timer
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Port_Init(); //ensure clock pins are configured
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SetVCoreUp(1); //Configure MCU core voltage for HF clock
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SetVCoreUp(2); //
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SetVCoreUp(3); //
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Clock_XT1_Init(); //LF clock source init
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Clock_XT2_Init(); //HF clock source init
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}
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void Port_Init(void)
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{
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//Clock Source TEST PINS ACLK/MCLK/SMCLK
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P11DIR |= (1 << 0) | (1 << 1) | (1 << 2); //set P11.0:P11.2 as output ACLK/MCLK/SMCLK
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P11SEL |= (1 << 0) | (1 << 1) | (1 << 2); //set P11.0:P11.2 as ACLK/MCLK/SMCLK function
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//XT1 ALTERNATE PIN CONFIG
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P7SEL |= (1 << 0) | (1 << 1); //set P7.0 & P7.1 as XT1IN/XT1OUT periph
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P7DIR |= (1 << 0) | (1 << 1);
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//XT2 ALTERNATE PIN CONFIG
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P5SEL |= (1 << 2) | (1 << 3); //set P5.2 & P5.3 as XT2IN/XT2OUT periph
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P5DIR |= (1 << 2) | (1 << 3);
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}
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void Clock_XT1_Init(void)
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{
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char i;
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//XT1 CLOCK CONFIG
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UCSCTL6 &= ~(XT1OFF); //Enable XT1
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UCSCTL6 &= ~(XT1DRIVE1 | XT1DRIVE0); //lowest drive current LF 32KHz oscillator
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do
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{
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UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);//Clear XT2,XT1,DCO fault flags
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SFRIFG1 &= ~OFIFG; //Clear fault flags
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for(i=255;i>0;i--); //Delay for Osc to stabilize
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}
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while ((SFRIFG1 & OFIFG) != 0); //Test oscillator fault flag
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UCSCTL4 |= SELA__XT1CLK; //Clock Source ACLK = XT1 = 32kHz
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UCSCTL5 |= DIVA_0; //Divide ACLK/1 = 32kHz
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}
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void Clock_XT2_Init(void)
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{
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char i;
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//XT2 CLOCK CONFIG
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UCSCTL6 &= ~(XT2OFF); //Enable XT2
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UCSCTL6 |= XT2DRIVE_3; //Drive current 16-24 MHz Clock
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UCSCTL6 &= ~XT2BYPASS; //XT2 Sourced Externally from pin - 20MHz
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do
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{
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UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);//Clear XT2,XT1,DCO fault flags
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SFRIFG1 &= ~OFIFG; //Clear fault flags
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for(i=255;i>0;i--); //Delay for Osc to stabilize
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}
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while ((SFRIFG1 & OFIFG) != 0); //Test oscillator fault flag
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UCSCTL4 |= (SELS__XT2CLK | SELM__XT2CLK);//Clock Source SMCLK=MCLK = XT2 = 20MHz
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UCSCTL5 |= DIVM_0 | DIVS_1; //MCLK:XT2/1 = 20MHz SMCLK:XT2/2 = 10MHz
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}
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/*************************************************************
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/ Name: SetVCoreUp
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/ IN: int Level
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/ OUT: void
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/ DESC: This function is used to set the voltage of the VCORE to
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/ The level specified in input
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/ Reference: Users Guide page 74
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************************************************************/
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void SetVCoreUp (unsigned int level)
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{
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// Open PMM registers for write access
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PMMCTL0_H = 0xA5;
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// Set SVS/SVM high side new level
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SVSMHCTL = SVSHE + SVSHRVL0 * level + SVMHE + SVSMHRRL0 * level;
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// Set SVM low side to new level
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SVSMLCTL = SVSLE + SVMLE + SVSMLRRL0 * level;
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// Wait till SVM is settled
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while ((PMMIFG & SVSMLDLYIFG) == 0);
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// Clear already set flags
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PMMIFG &= ~(SVMLVLRIFG + SVMLIFG);
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// Set VCore to new level
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PMMCTL0_L = PMMCOREV0 * level;
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// Wait till new level reached
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if ((PMMIFG & SVMLIFG))
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while ((PMMIFG & SVMLVLRIFG) == 0);
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// Set SVS/SVM low side to new level
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SVSMLCTL = SVSLE + SVSLRVL0 * level + SVMLE + SVSMLRRL0 * level;
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// Wait till SVM is settled
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while ((PMMIFG & SVSMLDLYIFG) == 0);
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// Lock PMM registers for write access
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PMMCTL0_H = 0x00;
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}
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