575 lines
18 KiB
C
575 lines
18 KiB
C
/*
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* Tritium MCP2515 CAN Interface
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* Copyright (c) 2006, Tritium Pty Ltd. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* - Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
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* - Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer
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* in the documentation and/or other materials provided with the distribution.
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* - Neither the name of Tritium Pty Ltd nor the names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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* OF SUCH DAMAGE.
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*
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* Last Modified: J.Kennedy, Tritium Pty Ltd, 18 December 2006
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*
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* - Implements the following CAN interface functions
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* - can0_init
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* - can0_transmit
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* - can0_receive
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*
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* Modified for tranmist errors, B. Bazuin 7/2012
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*
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*/
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// Include files
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#include "Sunseeker2021.h"
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#include "can.h"
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// Public variables
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can_variables can;
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// Private variables
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unsigned char buffer[16];
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/**************************************************************************************************
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* PUBLIC FUNCTIONS
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*************************************************************************************************/
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/*
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* Initialises MCP2515 CAN controller
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* - Resets MCP2515 via SPI port (switches to config mode, clears errors)
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* - Changes CLKOUT to /4 rate (4 MHz)
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* - Sets up bit timing
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* - originally 1 Mbit operation
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* - modified for 250 kbps operation (buffer[2] setting below)
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* - Sets up receive filters and masks
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* - Rx Filter 0 = Motor controller velocity
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* - Rx Filter 1 = Unused
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* - Rx Filter 2 = Driver controls packets (for remote frame requests)
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* - Rx Filter 3 = Unused
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* - Rx Filter 4 = Unused
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* - Rx Filter 5 = Unused
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* - Rx Mask 0 = Exact message must match (all 11 bits)
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* - Rx Mask 1 = Block address must match (upper 6 bits)
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* - Enables ERROR and RX interrupts on IRQ pin
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* - Switches to normal (operating) mode
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*/
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void can0_init( void )
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{
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// Set up reset and clocking
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can0_reset();
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can0_mod( CANCTRL, 0x03, 0x02 ); // CANCTRL register, modify lower 2 bits, CLK = /4
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// Set up bit timing & interrupts
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buffer[0] = 0x02; // CNF3 register: PHSEG2 = 3Tq, No wakeup, CLKOUT = CLK
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buffer[1] = 0xC9; // CNF2 register: set PHSEG2 in CNF3, Triple sample, PHSEG1= 2Tq, PROP = 2Tq
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// buffer[2] = 0x00; // CNF1 register: SJW = 1Tq, BRP = 0 > 1Mbps
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buffer[2] = 0x03; // CNF1 register: SJW = 1Tq, BRP = 3 > 250 kbps
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buffer[3] = 0xA3; // CANINTE register: enable MERRE, ERROR, RX0 & RX1 interrupts on IRQ pin
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// buffer[3] = 0x23; // CANINTE register: enable ERROR, RX0 & RX1 interrupts on IRQ pin
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buffer[4] = 0x00; // CANINTF register: clear all IRQ flags
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buffer[5] = 0x00; // EFLG register: clear all user-changable error flags
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can0_write( CNF3, &buffer[0], 6); // Write to registers
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// Set up receive filtering & masks
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// RXF0 - Buffer 0
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buffer[ 0] = (unsigned char)((DC_CAN_BASE + DC_SWITCH) >> 3);
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buffer[ 1] = (unsigned char)((DC_CAN_BASE + DC_SWITCH) << 5);
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buffer[ 2] = 0x00;
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buffer[ 3] = 0x00;
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// RXF1 - Buffer 0
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buffer[ 4] = (unsigned char)((AC_CAN_BASE + AC_BP_CHARGE) >> 3);
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buffer[ 5] = (unsigned char)((AC_CAN_BASE + AC_BP_CHARGE) >> 3);
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buffer[ 6] = 0x00;
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buffer[ 7] = 0x00;
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// RXF2 - Buffer 1
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buffer[ 8] = (unsigned char)((BP_CAN_BASE) >> 3);
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buffer[ 9] = (unsigned char)((BP_CAN_BASE) << 5);
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buffer[10] = 0x00;
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buffer[11] = 0x00;
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can0_write( RXF0SIDH, &buffer[0], 12 );
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// RXF3 - Buffer 1
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buffer[ 0] = 0x00;
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buffer[ 1] = 0x00;
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buffer[ 2] = 0x00;
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buffer[ 3] = 0x00;
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// RXF4 - Buffer 1
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buffer[ 4] = 0x00;
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buffer[ 5] = 0x00;
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buffer[ 6] = 0x00;
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buffer[ 7] = 0x00;
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// RXF5 - Buffer 1
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buffer[ 8] = 0x00;
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buffer[ 9] = 0x00;
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buffer[10] = 0x00;
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buffer[11] = 0x00;
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can0_write( RXF3SIDH, &buffer[0], 12 );
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// RXM0 - Buffer 0
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buffer[ 0] = 0xFF; // Match entire 11 bit ID (ID is left-justified in 32-bit mask register)
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buffer[ 1] = 0xE0;
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buffer[ 2] = 0x00;
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buffer[ 3] = 0x00;
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// RXM1 - Buffer 1
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buffer[ 4] = 0xFC; // Match upper 6 bits of ID - don't care about lower 5 bits (block address)
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buffer[ 5] = 0x00;
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buffer[ 6] = 0x00;
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buffer[ 7] = 0x00;
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can0_write( RXM0SIDH, &buffer[0], 8 );
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buffer[0] = 0x04; //enable filters & rollover
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can0_write(RXB0CTRL, &buffer[0], 1);
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buffer[0] = 0x04; //enable filters
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can0_write(RXB1CTRL, &buffer[0], 1);
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buffer[0] = 0x0F; //enable RX0BINT and RX1BINT pins
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can0_write(BFPCTRL, &buffer[0], 1);
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// Switch out of config mode into normal operating mode
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// can0_mod( CANCTRL, 0x08, 0x08 ); // CANCTRL register,One-SHot Mode for Transmission
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// Switch out of config mode into normal operating mode
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can0_mod( CANCTRL, 0xE0, 0x00 ); // CANCTRL register, modify upper 3 bits, mode = Normal
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}
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/*
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* Receives a CAN message from the MCP2515
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* - Run this routine when an IRQ is received
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* - Query the controller to identify the source of the IRQ
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* - If it was an ERROR IRQ, read & clear the Error Flag register, and return it
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* - If it was an RX IRQ, read the message and address, and return them
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* - If both, handle the error preferentially to the message
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* - Clear the appropriate IRQ flag bits
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*/
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void can0_receive( void )
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{
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unsigned char flags;
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// Read out the interrupt flags register
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can0_read( CANINTF, &flags, 1 );
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// Check for errors
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if(( flags & MCP_IRQ_ERR ) != 0x00 ){
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// Read error flags and counters
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can0_read( EFLAG, &buffer[0], 1 );
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can0_read( TEC, &buffer[1], 2 );
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// Clear error flags
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can0_mod( EFLAG, buffer[0], 0x00 ); // Modify (to '0') all bits that were set
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// Return error code, a blank address field, and error registers in data field
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can.status = CAN_ERROR;
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can.address = 0x0000;
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can.data.data_u8[0] = flags; // CANINTF
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can.data.data_u8[1] = buffer[0]; // EFLG
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can.data.data_u8[2] = buffer[1]; // TEC
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can.data.data_u8[3] = buffer[2]; // REC
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// Clear the IRQ flag
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can0_mod( CANINTF, MCP_IRQ_ERR, 0x00 );
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}
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// No error, check for received messages, buffer 0
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else if(( flags & MCP_IRQ_RXB0 ) != 0x00 ){
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// Read in the info, address & message data
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can0_read( RXB0CTRL, &buffer[0], 14 );
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// Fill out return structure
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// check for Remote Frame requests and indicate the status correctly
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if(( buffer[0] & MCP_RXB0_RTR ) == 0x00 ){
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// We've received a standard data packet
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can.status = CAN_OK;
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// Fill in the data
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can.data.data_u8[0] = buffer[ 6];
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can.data.data_u8[1] = buffer[ 7];
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can.data.data_u8[2] = buffer[ 8];
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can.data.data_u8[3] = buffer[ 9];
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can.data.data_u8[4] = buffer[10];
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can.data.data_u8[5] = buffer[11];
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can.data.data_u8[6] = buffer[12];
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can.data.data_u8[7] = buffer[13];
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}
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else{
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// We've received a remote frame request
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// Data is irrelevant with an RTR
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can.status = CAN_RTR;
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}
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// Fill in the address
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can.address = buffer[1];
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can.address = can.address << 3;
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buffer[2] = buffer[2] >> 5;
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can.address = can.address | buffer[2];
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// Clear the IRQ flag
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can0_mod( CANINTF, MCP_IRQ_RXB0, 0x00 );
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}
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// No error, check for received messages, buffer 1
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else if(( flags & MCP_IRQ_RXB1 ) != 0x00 ){
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// Read in the info, address & message data
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can0_read( RXB1CTRL, &buffer[0], 14 );
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// Fill out return structure
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// check for Remote Frame requests and indicate the status correctly
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if(( buffer[0] & MCP_RXB1_RTR ) == 0x00 ){
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// We've received a standard data packet
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can.status = CAN_OK;
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// Fill in the data
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can.data.data_u8[0] = buffer[ 6];
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can.data.data_u8[1] = buffer[ 7];
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can.data.data_u8[2] = buffer[ 8];
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can.data.data_u8[3] = buffer[ 9];
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can.data.data_u8[4] = buffer[10];
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can.data.data_u8[5] = buffer[11];
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can.data.data_u8[6] = buffer[12];
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can.data.data_u8[7] = buffer[13];
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}
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else{
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// We've received a remote frame request
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// Data is irrelevant with an RTR
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can.status = CAN_RTR;
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}
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// Fill in the address
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can.address = buffer[1];
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can.address = can.address << 3;
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buffer[2] = buffer[2] >> 5;
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can.address = can.address | buffer[2];
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// Clear the IRQ flag
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can0_mod( CANINTF, MCP_IRQ_RXB1, 0x00 );
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}
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// If multiple receive then clear that error
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else if(( flags & MCP_IRQ_MERR) != 0x00 ){
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// Read error flags and counters
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can0_read( EFLAG, &buffer[0], 1 );
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can0_read( TEC, &buffer[1], 2 );
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// Clear error flags
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can0_mod( EFLAG, buffer[0], 0x00 ); // Modify (to '0') all bits that were set
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// Return error code, a blank address field, and error registers in data field
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can.status = CAN_MERROR;
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can.address = 0x0000;
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can.data.data_u8[0] = flags; // CANINTF
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can.data.data_u8[1] = buffer[0]; // EFLG
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can.data.data_u8[2] = buffer[1]; // TEC
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can.data.data_u8[3] = buffer[2]; // REC
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// Clear the IRQ flag
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can0_mod( CANINTF, MCP_IRQ_MERR, 0x00 );
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}
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else{
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can.status = CAN_FERROR;
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can.address = 0x0001;
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can.data.data_u8[0] = flags; // CANINTF
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// Clear all IRQ flag
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can0_mod( CANINTF, 0xFF, 0x00 );
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}
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//added to tritum code to account for the fact that we could have more then one intrrupt pending at a given time
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//NOTE: YOU MUST CLEAR THE MAIN_MODE STATUS BEFORE ENTERING THIS FUNCTION OR YOU WILL CLEAR THE RETURN FLAG
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can0_read(CANINTF, &flags, 1 );
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if((( flags & MCP_IRQ_ERR ) ||( flags & MCP_IRQ_MERR )) != 0x00 )
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{
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can0_read(EFLAG, &buffer[0], 1 );
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can0_read(TEC, &buffer[1], 2 );
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// Clear error flags
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can0_mod(EFLAG, buffer[0], 0x00 ); // Modify (to '0') all bits that were set
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// Clear the IRQ flag
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can0_mod(CANINTF, 0XA3, 0x00 );
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}
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}
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/*
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* Transmits a CAN message to the bus
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* - Accepts address and data payload via can_interface structure
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* - Busy waits while message is sent to CAN controller
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* - Uses all available transmit buffers (3 available in CAN controller) to maximise throughput
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* - Only modifies address information if it's different from what is already set up in CAN controller
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* - Assumes constant 8-byte data length value
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*/
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int can0_transmit( void )
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{
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unsigned int wait_count;
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static unsigned int buf_addr[3] = {0xFFFF, 0xFFFF, 0xFFFF};
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extern unsigned char can_full; //used for CAN transmission status
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// Fill data into buffer, it's used by any address
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// Allow room at the start of the buffer for the address info if needed
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buffer[ 5] = can.data.data_u8[0];
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buffer[ 6] = can.data.data_u8[1];
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buffer[ 7] = can.data.data_u8[2];
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buffer[ 8] = can.data.data_u8[3];
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buffer[ 9] = can.data.data_u8[4];
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buffer[10] = can.data.data_u8[5];
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buffer[11] = can.data.data_u8[6];
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buffer[12] = can.data.data_u8[7];
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// Check if the incoming address has already been configured in a mailbox
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if( can.address == buf_addr[0] ){
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// Mailbox 0 setup matches our new message
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// Write to TX Buffer 0, start at data registers, and initiate transmission
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can0_write_tx( 0x01, &buffer[5] );
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can0_rts( 0 );
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}
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else if( can.address == buf_addr[1] ){
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// Mailbox 1 setup matches our new message
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// Write to TX Buffer 1, start at data registers, and initiate transmission
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can0_write_tx( 0x03, &buffer[5] );
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can0_rts( 1 );
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}
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else if( can.address == buf_addr[2] ){
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// Mailbox 2 setup matches our new message
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// Write to TX Buffer 2, start at data registers, and initiate transmission
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can0_write_tx( 0x05, &buffer[5] );
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can0_rts( 2 );
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}
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else{
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// No matches in existing mailboxes
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// No mailboxes already configured, so we'll need to load an address - set it up
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buffer[0] = (unsigned char)(can.address >> 3);
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buffer[1] = (unsigned char)(can.address << 5);
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buffer[2] = 0x00; // EID8
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buffer[3] = 0x00; // EID0
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buffer[4] = 0x08; // DLC = 8 bytes
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// Check if we've got any un-setup mailboxes free and use them
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// Otherwise, find a non-busy mailbox and set it up with our new address
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if( buf_addr[0] == 0xFFFF ){ // Mailbox 0 is free
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// Write to TX Buffer 0, start at address registers, and initiate transmission
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can0_write_tx( 0x00, &buffer[0] );
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can0_rts( 0 );
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buf_addr[0] = can.address;
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}
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else if( buf_addr[1] == 0xFFFF ){ // Mailbox 1 is free
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// Write to TX Buffer 1, start at address registers, and initiate transmission
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can0_write_tx( 0x02, &buffer[0] );
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can0_rts( 1 );
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buf_addr[1] = can.address;
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}
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else if( buf_addr[2] == 0xFFFF ){ // Mailbox 2 is free
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// Write to TX Buffer 2, start at address registers, and initiate transmission
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can0_write_tx( 0x04, &buffer[0] );
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can0_rts( 2 );
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buf_addr[2] = can.address;
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}
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else {
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// No mailboxes free, wait until at least one is not busy
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wait_count = 0;
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while((( can0_read_status() & 0x54 ) == 0x54) && (wait_count<2))
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{
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delay();
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wait_count++;
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}
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// Continue without sending ...
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// if(( can0_read_status() & 0x54 ) == 0x54) {
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// can0_full = TRUE;
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// }
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// else {
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// Is it mailbox 0?
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if(( can0_read_status() & 0x04 ) == 0x00) {
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// Setup mailbox 0 and send the message
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can0_write_tx( 0x00, &buffer[0] );
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can0_rts( 0 );
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buf_addr[0] = can.address;
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}
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// Is it mailbox 1?
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else if(( can0_read_status() & 0x10 ) == 0x00) {
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// Setup mailbox 1 and send the message
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can0_write_tx( 0x02, &buffer[0] );
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can0_rts( 1 );
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buf_addr[1] = can.address;
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}
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// Is it mailbox 2?
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else if(( can0_read_status() & 0x40 ) == 0x00) {
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// Setup mailbox 2 and send the message
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can0_write_tx( 0x04, &buffer[0] );
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can0_rts( 2 );
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buf_addr[2] = can.address;
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}
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// }
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}
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}
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return(0);
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}
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/*
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* Read CAN Status flags
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*/
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void can0_flag_check( void )
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{
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extern unsigned char can_CANINTF, can0_FLAGS[3];
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can0_read( CANINTF, &can_CANINTF, 1 );
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// Check for errors
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can0_read( EFLAG, &can0_FLAGS[0], 1 );
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can0_read( TEC, &can0_FLAGS[1], 2 );
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}
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/**************************************************************************************************
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* PRIVATE FUNCTIONS
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*************************************************************************************************/
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/*
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* Resets MCP2515 CAN controller via SPI port
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* - SPI port must be already initialised
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*/
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void can0_reset( void )
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{
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can0_select;
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can0spi_transmit( MCP_RESET );
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can0_deselect;
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}
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/*
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* Reads data bytes from the MCP2515
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* - Pass in starting address, pointer to array of bytes for return data, and number of bytes to read
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*/
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void can0_read( unsigned char address, unsigned char *ptr, unsigned char bytes )
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{
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unsigned char i;
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can0_select;
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can0spi_transmit( MCP_READ );
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can0spi_transmit( address );
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for( i = 0; i < bytes; i++ ) *ptr++ = can0spi_exchange( 0x00 );
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can0_deselect;
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}
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/*
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* Reads data bytes from receive buffers
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* - Pass in buffer number and start position as defined in MCP2515 datasheet
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* - For starting at data, returns 8 bytes
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* - For starting at address, returns 13 bytes
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*/
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void can0_read_rx( unsigned char address, unsigned char *ptr )
|
|
{
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|
unsigned char i;
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|
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address &= 0x03; // Force upper bits of address to be zero (they're invalid)
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|
address <<= 1; // Shift input bits to correct location in command byte
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address |= MCP_READ_RX; // Construct command byte for MCP2515
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|
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can0_select;
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can0spi_transmit( address );
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|
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if(( address & 0x02 ) == 0x00 ){ // Start at address registers
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for( i = 0; i < 13; i++ ){
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*ptr++ = can0spi_exchange( 0x00 );
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|
}
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|
}
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else{ // Start at data registers
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for( i = 0; i < 8; i++ ){
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*ptr++ = can0spi_exchange( 0x00 );
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}
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|
}
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|
can0_deselect;
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|
}
|
|
|
|
/*
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* Writes data bytes to the MCP2515
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* - Pass in starting address, pointer to array of bytes, and number of bytes to write
|
|
*/
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|
void can0_write( unsigned char address, unsigned char *ptr, unsigned char bytes )
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|
{
|
|
unsigned char i;
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|
|
|
can0_select;
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|
can0spi_transmit( MCP_WRITE );
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|
can0spi_transmit( address );
|
|
for( i = 0; i < (bytes-1); i++ ){
|
|
can0spi_transmit( *ptr++ );
|
|
}
|
|
can0spi_transmit( *ptr );
|
|
can0_deselect;
|
|
}
|
|
|
|
/*
|
|
* Writes data bytes to transmit buffers
|
|
* - Pass in buffer number and start position as defined in MCP2515 datasheet
|
|
* - For starting at data, accepts 8 bytes
|
|
* - For starting at address, accepts 13 bytes
|
|
*/
|
|
void can0_write_tx( unsigned char address, unsigned char *ptr )
|
|
{
|
|
unsigned char i;
|
|
|
|
address &= 0x07; // Force upper bits of address to be zero (they're invalid)
|
|
address |= MCP_WRITE_TX; // Construct command byte for MCP2515
|
|
|
|
can0_select;
|
|
can0spi_transmit( address );
|
|
|
|
if(( address & 0x01 ) == 0x00 ){ // Start at address registers
|
|
for( i = 0; i < 13; i++ ){
|
|
can0spi_transmit( *ptr++ );
|
|
}
|
|
}
|
|
else{ // Start at data registers
|
|
for( i = 0; i < 8; i++ ){
|
|
can0spi_transmit( *ptr++ );
|
|
}
|
|
}
|
|
can0_deselect;
|
|
}
|
|
|
|
/*
|
|
* Request to send selected transmit buffer
|
|
* - Pass in address of buffer to transmit: 0, 1 or 2
|
|
*/
|
|
void can0_rts( unsigned char address )
|
|
{
|
|
unsigned char i;
|
|
|
|
// Set up address bits in command byte
|
|
i = MCP_RTS;
|
|
if( address == 0 ) i |= 0x01;
|
|
else if( address == 1 ) i |= 0x02;
|
|
else if( address == 2 ) i |= 0x04;
|
|
|
|
// Write command
|
|
can0_select;
|
|
can0spi_transmit( i );
|
|
can0_deselect;
|
|
}
|
|
|
|
/*
|
|
* Reads MCP2515 status register
|
|
*/
|
|
unsigned char can0_read_status( void )
|
|
{
|
|
unsigned char status;
|
|
|
|
can0_select;
|
|
can0spi_transmit( MCP_STATUS );
|
|
status = can0spi_exchange( 0x00 );
|
|
can0_deselect;
|
|
return status;
|
|
}
|
|
|
|
/*
|
|
* Reads MCP2515 RX status (filter match) register
|
|
*/
|
|
unsigned char can0_read_filter( void )
|
|
{
|
|
unsigned char status;
|
|
|
|
can0_select;
|
|
can0spi_transmit( MCP_FILTER );
|
|
status = can0spi_exchange( 0x00 );
|
|
can0_deselect;
|
|
return status;
|
|
}
|
|
|
|
/*
|
|
* Modifies selected register in MCP2515
|
|
* - Pass in register to be modified, bit mask, and bit data
|
|
*/
|
|
void can0_mod( unsigned char address, unsigned char mask, unsigned char data )
|
|
{
|
|
can0_select;
|
|
can0spi_transmit( MCP_MODIFY );
|
|
can0spi_transmit( address );
|
|
can0spi_transmit( mask );
|
|
can0spi_transmit( data );
|
|
can0_deselect;
|
|
}
|