# compile verilog/system verilog design source files
verilog xil_defaultlib  \
"../../../../lab2CA.srcs/sources_1/new/ALU.v" \
"../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \
"../../../../lab2CA.srcs/sources_1/new/ControlUnit.v" \
"../../../../lab2CA.srcs/sources_1/new/EMModule.v" \
"../../../../lab2CA.srcs/sources_1/new/FDModule.v" \
"../../../../lab2CA.srcs/sources_1/new/FetchUnit.v" \
"../../../../lab2CA.srcs/sources_1/new/RegFile.v" \
"../../../../lab2CA.srcs/sources_1/new/WMUdule.v" \
"../../../../lab2CA.srcs/sources_1/new/dataMemory.v" \
"../../../../lab2CA.srcs/sources_1/new/instructionMemory.v" \
"../../../../lab2CA.srcs/sources_1/new/CPU9bits.v" \

# compile glbl module
verilog xil_defaultlib "glbl.v"

# Do not sort compile order
nosort
