// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.3 (win64) Build 2405991 Thu Dec  6 23:38:27 MST 2018
// Date        : Sat Feb 16 17:29:30 2019
// Host        : DESKTOP-8QFGS52 running 64-bit major release  (build 9200)
// Command     : write_verilog -mode timesim -nolib -sdf_anno true -force -file
//               C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/impl/timing/xsim/regFile_tb_time_impl.v
// Design      : FetchUnit
// Purpose     : This verilog netlist is a timing simulation representation of the design and should not be modified or
//               synthesized. Please ensure that this netlist is used with the corresponding SDF file.
// Device      : xc7k160tifbg484-2L
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
`define XIL_TIMING

(* ECO_CHECKSUM = "fb52d5c" *) 
(* NotValidForBitStream *)
module FetchUnit
   (clk,
    reset,
    op_idx,
    AddrIn,
    AddrOut);
  input clk;
  input reset;
  input op_idx;
  input [8:0]AddrIn;
  output [8:0]AddrOut;

  wire [8:0]AddrIn;
  wire [8:0]AddrIn_IBUF;
  wire [8:0]AddrOut;
  wire [8:0]AddrOut_OBUF;
  wire clk;
  wire clk_IBUF;
  wire clk_IBUF_BUFG;
  wire op_idx;
  wire op_idx_IBUF;
  wire reset;
  wire reset_IBUF;

initial begin
 $sdf_annotate("regFile_tb_time_impl.sdf",,,,"tool_control");
end
  IBUF \AddrIn_IBUF[0]_inst 
       (.I(AddrIn[0]),
        .O(AddrIn_IBUF[0]));
  IBUF \AddrIn_IBUF[1]_inst 
       (.I(AddrIn[1]),
        .O(AddrIn_IBUF[1]));
  IBUF \AddrIn_IBUF[2]_inst 
       (.I(AddrIn[2]),
        .O(AddrIn_IBUF[2]));
  IBUF \AddrIn_IBUF[3]_inst 
       (.I(AddrIn[3]),
        .O(AddrIn_IBUF[3]));
  IBUF \AddrIn_IBUF[4]_inst 
       (.I(AddrIn[4]),
        .O(AddrIn_IBUF[4]));
  IBUF \AddrIn_IBUF[5]_inst 
       (.I(AddrIn[5]),
        .O(AddrIn_IBUF[5]));
  IBUF \AddrIn_IBUF[6]_inst 
       (.I(AddrIn[6]),
        .O(AddrIn_IBUF[6]));
  IBUF \AddrIn_IBUF[7]_inst 
       (.I(AddrIn[7]),
        .O(AddrIn_IBUF[7]));
  IBUF \AddrIn_IBUF[8]_inst 
       (.I(AddrIn[8]),
        .O(AddrIn_IBUF[8]));
  OBUF \AddrOut_OBUF[0]_inst 
       (.I(AddrOut_OBUF[0]),
        .O(AddrOut[0]));
  OBUF \AddrOut_OBUF[1]_inst 
       (.I(AddrOut_OBUF[1]),
        .O(AddrOut[1]));
  OBUF \AddrOut_OBUF[2]_inst 
       (.I(AddrOut_OBUF[2]),
        .O(AddrOut[2]));
  OBUF \AddrOut_OBUF[3]_inst 
       (.I(AddrOut_OBUF[3]),
        .O(AddrOut[3]));
  OBUF \AddrOut_OBUF[4]_inst 
       (.I(AddrOut_OBUF[4]),
        .O(AddrOut[4]));
  OBUF \AddrOut_OBUF[5]_inst 
       (.I(AddrOut_OBUF[5]),
        .O(AddrOut[5]));
  OBUF \AddrOut_OBUF[6]_inst 
       (.I(AddrOut_OBUF[6]),
        .O(AddrOut[6]));
  OBUF \AddrOut_OBUF[7]_inst 
       (.I(AddrOut_OBUF[7]),
        .O(AddrOut[7]));
  OBUF \AddrOut_OBUF[8]_inst 
       (.I(AddrOut_OBUF[8]),
        .O(AddrOut[8]));
  register PC
       (.AddrIn_IBUF(AddrIn_IBUF),
        .AddrOut_OBUF(AddrOut_OBUF),
        .clk_IBUF_BUFG(clk_IBUF_BUFG),
        .op_idx_IBUF(op_idx_IBUF),
        .reset_IBUF(reset_IBUF));
  BUFG clk_IBUF_BUFG_inst
       (.I(clk_IBUF),
        .O(clk_IBUF_BUFG));
  IBUF clk_IBUF_inst
       (.I(clk),
        .O(clk_IBUF));
  IBUF op_idx_IBUF_inst
       (.I(op_idx),
        .O(op_idx_IBUF));
  IBUF reset_IBUF_inst
       (.I(reset),
        .O(reset_IBUF));
endmodule

module register
   (AddrOut_OBUF,
    reset_IBUF,
    clk_IBUF_BUFG,
    op_idx_IBUF,
    AddrIn_IBUF);
  output [8:0]AddrOut_OBUF;
  input reset_IBUF;
  input clk_IBUF_BUFG;
  input op_idx_IBUF;
  input [8:0]AddrIn_IBUF;

  wire [8:0]AddrIn_IBUF;
  wire [8:0]AddrOut_OBUF;
  wire \AddrOut_OBUF[8]_inst_i_2_n_0 ;
  wire \Dout[8]_i_2_n_0 ;
  wire clk_IBUF_BUFG;
  wire op_idx_IBUF;
  wire [8:0]out;
  wire [8:0]progC_out;
  wire reset_IBUF;

  LUT1 #(
    .INIT(2'h1)) 
    \AddrOut_OBUF[0]_inst_i_1 
       (.I0(progC_out[0]),
        .O(AddrOut_OBUF[0]));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \AddrOut_OBUF[1]_inst_i_1 
       (.I0(progC_out[0]),
        .I1(progC_out[1]),
        .O(AddrOut_OBUF[1]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \AddrOut_OBUF[2]_inst_i_1 
       (.I0(progC_out[2]),
        .I1(progC_out[0]),
        .I2(progC_out[1]),
        .O(AddrOut_OBUF[2]));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \AddrOut_OBUF[3]_inst_i_1 
       (.I0(progC_out[1]),
        .I1(progC_out[0]),
        .I2(progC_out[2]),
        .I3(progC_out[3]),
        .O(AddrOut_OBUF[3]));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \AddrOut_OBUF[4]_inst_i_1 
       (.I0(progC_out[4]),
        .I1(progC_out[1]),
        .I2(progC_out[0]),
        .I3(progC_out[2]),
        .I4(progC_out[3]),
        .O(AddrOut_OBUF[4]));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \AddrOut_OBUF[5]_inst_i_1 
       (.I0(progC_out[5]),
        .I1(progC_out[3]),
        .I2(progC_out[2]),
        .I3(progC_out[0]),
        .I4(progC_out[1]),
        .I5(progC_out[4]),
        .O(AddrOut_OBUF[5]));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \AddrOut_OBUF[6]_inst_i_1 
       (.I0(progC_out[6]),
        .I1(progC_out[4]),
        .I2(\AddrOut_OBUF[8]_inst_i_2_n_0 ),
        .I3(progC_out[5]),
        .O(AddrOut_OBUF[6]));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \AddrOut_OBUF[7]_inst_i_1 
       (.I0(progC_out[7]),
        .I1(progC_out[5]),
        .I2(\AddrOut_OBUF[8]_inst_i_2_n_0 ),
        .I3(progC_out[4]),
        .I4(progC_out[6]),
        .O(AddrOut_OBUF[7]));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \AddrOut_OBUF[8]_inst_i_1 
       (.I0(progC_out[8]),
        .I1(progC_out[6]),
        .I2(progC_out[4]),
        .I3(\AddrOut_OBUF[8]_inst_i_2_n_0 ),
        .I4(progC_out[5]),
        .I5(progC_out[7]),
        .O(AddrOut_OBUF[8]));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \AddrOut_OBUF[8]_inst_i_2 
       (.I0(progC_out[3]),
        .I1(progC_out[2]),
        .I2(progC_out[0]),
        .I3(progC_out[1]),
        .O(\AddrOut_OBUF[8]_inst_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT3 #(
    .INIT(8'h74)) 
    \Dout[0]_i_1 
       (.I0(progC_out[0]),
        .I1(op_idx_IBUF),
        .I2(AddrIn_IBUF[0]),
        .O(out[0]));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT4 #(
    .INIT(16'h6F60)) 
    \Dout[1]_i_1 
       (.I0(progC_out[0]),
        .I1(progC_out[1]),
        .I2(op_idx_IBUF),
        .I3(AddrIn_IBUF[1]),
        .O(out[1]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT5 #(
    .INIT(32'h6AFF6A00)) 
    \Dout[2]_i_1 
       (.I0(progC_out[2]),
        .I1(progC_out[0]),
        .I2(progC_out[1]),
        .I3(op_idx_IBUF),
        .I4(AddrIn_IBUF[2]),
        .O(out[2]));
  LUT6 #(
    .INIT(64'h7F80FFFF7F800000)) 
    \Dout[3]_i_1 
       (.I0(progC_out[1]),
        .I1(progC_out[0]),
        .I2(progC_out[2]),
        .I3(progC_out[3]),
        .I4(op_idx_IBUF),
        .I5(AddrIn_IBUF[3]),
        .O(out[3]));
  LUT4 #(
    .INIT(16'h6F60)) 
    \Dout[4]_i_1 
       (.I0(progC_out[4]),
        .I1(\AddrOut_OBUF[8]_inst_i_2_n_0 ),
        .I2(op_idx_IBUF),
        .I3(AddrIn_IBUF[4]),
        .O(out[4]));
  LUT5 #(
    .INIT(32'h6AFF6A00)) 
    \Dout[5]_i_1 
       (.I0(progC_out[5]),
        .I1(\AddrOut_OBUF[8]_inst_i_2_n_0 ),
        .I2(progC_out[4]),
        .I3(op_idx_IBUF),
        .I4(AddrIn_IBUF[5]),
        .O(out[5]));
  LUT6 #(
    .INIT(64'h6AAAFFFF6AAA0000)) 
    \Dout[6]_i_1 
       (.I0(progC_out[6]),
        .I1(progC_out[4]),
        .I2(\AddrOut_OBUF[8]_inst_i_2_n_0 ),
        .I3(progC_out[5]),
        .I4(op_idx_IBUF),
        .I5(AddrIn_IBUF[6]),
        .O(out[6]));
  LUT5 #(
    .INIT(32'h6AFF6A00)) 
    \Dout[7]_i_1 
       (.I0(progC_out[7]),
        .I1(\Dout[8]_i_2_n_0 ),
        .I2(progC_out[6]),
        .I3(op_idx_IBUF),
        .I4(AddrIn_IBUF[7]),
        .O(out[7]));
  LUT6 #(
    .INIT(64'h6AAAFFFF6AAA0000)) 
    \Dout[8]_i_1 
       (.I0(progC_out[8]),
        .I1(progC_out[6]),
        .I2(\Dout[8]_i_2_n_0 ),
        .I3(progC_out[7]),
        .I4(op_idx_IBUF),
        .I5(AddrIn_IBUF[8]),
        .O(out[8]));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \Dout[8]_i_2 
       (.I0(progC_out[5]),
        .I1(progC_out[3]),
        .I2(progC_out[2]),
        .I3(progC_out[0]),
        .I4(progC_out[1]),
        .I5(progC_out[4]),
        .O(\Dout[8]_i_2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \Dout_reg[0] 
       (.C(clk_IBUF_BUFG),
        .CE(1'b1),
        .D(out[0]),
        .Q(progC_out[0]),
        .R(reset_IBUF));
  FDRE #(
    .INIT(1'b0)) 
    \Dout_reg[1] 
       (.C(clk_IBUF_BUFG),
        .CE(1'b1),
        .D(out[1]),
        .Q(progC_out[1]),
        .R(reset_IBUF));
  FDRE #(
    .INIT(1'b0)) 
    \Dout_reg[2] 
       (.C(clk_IBUF_BUFG),
        .CE(1'b1),
        .D(out[2]),
        .Q(progC_out[2]),
        .R(reset_IBUF));
  FDRE #(
    .INIT(1'b0)) 
    \Dout_reg[3] 
       (.C(clk_IBUF_BUFG),
        .CE(1'b1),
        .D(out[3]),
        .Q(progC_out[3]),
        .R(reset_IBUF));
  FDRE #(
    .INIT(1'b0)) 
    \Dout_reg[4] 
       (.C(clk_IBUF_BUFG),
        .CE(1'b1),
        .D(out[4]),
        .Q(progC_out[4]),
        .R(reset_IBUF));
  FDRE #(
    .INIT(1'b0)) 
    \Dout_reg[5] 
       (.C(clk_IBUF_BUFG),
        .CE(1'b1),
        .D(out[5]),
        .Q(progC_out[5]),
        .R(reset_IBUF));
  FDRE #(
    .INIT(1'b0)) 
    \Dout_reg[6] 
       (.C(clk_IBUF_BUFG),
        .CE(1'b1),
        .D(out[6]),
        .Q(progC_out[6]),
        .R(reset_IBUF));
  FDRE #(
    .INIT(1'b0)) 
    \Dout_reg[7] 
       (.C(clk_IBUF_BUFG),
        .CE(1'b1),
        .D(out[7]),
        .Q(progC_out[7]),
        .R(reset_IBUF));
  FDRE #(
    .INIT(1'b0)) 
    \Dout_reg[8] 
       (.C(clk_IBUF_BUFG),
        .CE(1'b1),
        .D(out[8]),
        .Q(progC_out[8]),
        .R(reset_IBUF));
endmodule
`ifndef GLBL
`define GLBL
`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;

//--------   STARTUP Globals --------------
    wire GSR;
    wire GTS;
    wire GWE;
    wire PRLD;
    tri1 p_up_tmp;
    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;

    wire PROGB_GLBL;
    wire CCLKO_GLBL;
    wire FCSBO_GLBL;
    wire [3:0] DO_GLBL;
    wire [3:0] DI_GLBL;
   
    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;
    reg JTAG_RUNTEST_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (strong1, weak0) GSR = GSR_int;
    assign (strong1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

endmodule
`endif
