diff --git a/lab2CA.srcs/sources_1/new/BasicModules.v b/lab2CA.srcs/sources_1/new/BasicModules.v
index 328f5c7..eaf0013 100644
--- a/lab2CA.srcs/sources_1/new/BasicModules.v
+++ b/lab2CA.srcs/sources_1/new/BasicModules.v
@@ -305,11 +305,6 @@ module gen_clock();
     end
 endmodule
 
-//testbench
-module gen_clock_tb();
-    reg clk;
-   gen
-
 module mux_2_1 tb0(
     input wire switch,
     input wire [8:0] A,B,