diff --git a/CPU9bits_tb_behav.wcfg b/CPU9bits_tb_behav.wcfg
index 8ff185f..56a2585 100644
--- a/CPU9bits_tb_behav.wcfg
+++ b/CPU9bits_tb_behav.wcfg
@@ -11,27 +11,45 @@
-
-
-
+
+
+
-
-
+
+
-
+
+
+ Program Counter
+ label
+
+ clk
+ clk
+
+
+ reset
+ reset
+
+
+ En
+ En
+
+
+ Din[8:0]
+ Din[8:0]
+ UNSIGNEDDECRADIX
+
+
+ Dout[8:0]
+ Dout[8:0]
+ UNSIGNEDDECRADIX
+
+
Fetch Unit
label
-
- clk
- clk
-
-
- reset
- reset
-
op_idx
op_idx
@@ -39,10 +57,12 @@
AddrIn[8:0]
AddrIn[8:0]
+ UNSIGNEDDECRADIX
AddrOut[8:0]
AddrOut[8:0]
+ UNSIGNEDDECRADIX
progC_out[8:0]
@@ -63,7 +83,6 @@
instIn[3:0]
instIn[3:0]
-
functBit
@@ -76,7 +95,6 @@
FU[2:0]
FU[2:0]
-
bank[1:0]
@@ -111,41 +129,9 @@
js
-
- Divider
+
+ Registers
label
-
-
- Instruction Memory
- label
-
-
- address[8:0]
- address[8:0]
- UNSIGNEDDECRADIX
-
-
- readData[8:0]
- readData[8:0]
- BINARYRADIX
-
-
- memory[8:0][8:0]
- memory[8:0][8:0]
-
-
-
- RF
- label
-
-
- clk
- clk
-
-
- reset
- reset
-
En
En
@@ -180,25 +166,285 @@
op1[8:0]
UNSIGNEDDECRADIX
+
+ decOut[3:0]
+ decOut[3:0]
+ UNSIGNEDDECRADIX
+
r0_out[8:0]
r0_out[8:0]
- UNSIGNEDDECRADIX
+ SIGNEDDECRADIX
r1_out[8:0]
r1_out[8:0]
- UNSIGNEDDECRADIX
+ SIGNEDDECRADIX
r2_out[8:0]
r2_out[8:0]
- UNSIGNEDDECRADIX
+ SIGNEDDECRADIX
r3_out[8:0]
r3_out[8:0]
+ SIGNEDDECRADIX
+
+
+
+ Banks
+ label
+
+ En
+ En
+
+
+ write_index[1:0]
+ write_index[1:0]
+
+
+ op0_idx[1:0]
+ op0_idx[1:0]
+
+
+ op1_idx[1:0]
+ op1_idx[1:0]
+
+
+ write_data[8:0]
+ write_data[8:0]
+
+
+ op0[8:0]
+ op0[8:0]
+
+
+ op1[8:0]
+ op1[8:0]
+
+
+ decOut[3:0]
+ decOut[3:0]
+
+
+ r0_out[8:0]
+ r0_out[8:0]
+ SIGNEDDECRADIX
+
+
+ r1_out[8:0]
+ r1_out[8:0]
+ SIGNEDDECRADIX
+
+
+ r2_out[8:0]
+ r2_out[8:0]
+ SIGNEDDECRADIX
+
+
+ r3_out[8:0]
+ r3_out[8:0]
+ SIGNEDDECRADIX
+
+
+
+ Divider
+ label
+
+
+ Instruction Memory
+ label
+
+ address[8:0]
+ address[8:0]
UNSIGNEDDECRADIX
+
+ readData[8:0]
+ readData[8:0]
+ BINARYRADIX
+
+
+ memory[100:0][8:0]
+ memory[100:0][8:0]
+
+
+ switch
+ switch
+
+
+ A[8:0]
+ A[8:0]
+
+
+ B[8:0]
+ B[8:0]
+
+
+ out[8:0]
+ out[8:0]
+
+
+ switch
+ switch
+
+
+ A
+ A
+
+
+ B
+ B
+
+
+ out
+ out
+
+
+ clk
+ clk
+
+
+ reset
+ reset
+
+
+ En
+ En
+
+
+ Din[50:0]
+ Din[50:0]
+
+
+ Dout[50:0]
+ Dout[50:0]
+
+
+
+ Data Memory
+ label
+
+ clk
+ clk
+
+
+ writeEnable
+ writeEnable
+
+
+ address[8:0]
+ address[8:0]
+ UNSIGNEDDECRADIX
+
+
+ writeData[8:0]
+ writeData[8:0]
+
+
+ readData[8:0]
+ readData[8:0]
+
+
+ memory[100:0][8:0]
+ memory[100:0][8:0]
+
+
+
+ Divider
+ label
+
+
+ Mux 3
+ label
+
+ switch
+ switch
+
+
+ A[8:0]
+ A[8:0]
+ SIGNEDDECRADIX
+
+
+ B[8:0]
+ B[8:0]
+ SIGNEDDECRADIX
+
+
+ out[8:0]
+ out[8:0]
+ SIGNEDDECRADIX
+
+
+
+ Mux 4
+ label
+
+ switch
+ switch
+
+
+ A[8:0]
+ A[8:0]
+ SIGNEDDECRADIX
+
+
+ B[8:0]
+ B[8:0]
+ SIGNEDDECRADIX
+
+
+ out[8:0]
+ out[8:0]
+ SIGNEDDECRADIX
+
+
+
+ Mux 5
+ label
+
+ switch
+ switch
+
+
+ A[8:0]
+ A[8:0]
+ SIGNEDDECRADIX
+
+
+ B[8:0]
+ B[8:0]
+ SIGNEDDECRADIX
+
+
+ out[8:0]
+ out[8:0]
+ SIGNEDDECRADIX
+
+
+
+ Mux 6
+ label
+
+ switch
+ switch
+
+
+ A[8:0]
+ A[8:0]
+ SIGNEDDECRADIX
+
+
+ B[8:0]
+ B[8:0]
+ SIGNEDDECRADIX
+
+
+ out[8:0]
+ out[8:0]
+ SIGNEDDECRADIX
+
diff --git a/lab2CA.srcs/sources_1/new/ControlUnit.v b/lab2CA.srcs/sources_1/new/ControlUnit.v
index 93f605d..7e17462 100644
--- a/lab2CA.srcs/sources_1/new/ControlUnit.v
+++ b/lab2CA.srcs/sources_1/new/ControlUnit.v
@@ -7,7 +7,7 @@ module ControlUnit(
output reg [2:0] FU,
output reg [1:0] bank,
output reg addi, mem, dataMemEn, RegEn, halt, link, js, compare0, compare1
- );
+ );
always @(instIn, functBit)
begin
diff --git a/lab2CA.xpr b/lab2CA.xpr
index 1161452..f36c02f 100644
--- a/lab2CA.xpr
+++ b/lab2CA.xpr
@@ -3,7 +3,7 @@
-
+
@@ -31,7 +31,7 @@
-
+