From 335280ccd532843a2eb808e75eacb61070a95325 Mon Sep 17 00:00:00 2001
From: "jose.rodriguezlabra" <jkz5178@wmich.edu>
Date: Sun, 24 Mar 2019 16:35:59 -0400
Subject: [PATCH 1/2] Added Binary Search Code

---
 Bank_behav1.wcfg                              |   8 +-
 lab2CA.runs/impl_1/gen_run.xml                |  14 +-
 lab2CA.sim/sim_1/behav/xsim/xelab.pb          | Bin 4381 -> 5421 bytes
 .../webtalk/xsim_webtalk.tcl                  |  40 +++--
 .../xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem  | Bin 19590 -> 19925 bytes
 lab2CA.sim/sim_1/behav/xsim/xvlog.pb          | Bin 8668 -> 8668 bytes
 lab2CA.srcs/sources_1/new/dataMemory.v        |  57 +++++--
 lab2CA.srcs/sources_1/new/instructionMemory.v | 150 +++++++++++++-----
 lab2CA.xpr                                    |   4 +-
 9 files changed, 186 insertions(+), 87 deletions(-)

diff --git a/Bank_behav1.wcfg b/Bank_behav1.wcfg
index 234d01c..123f0ad 100644
--- a/Bank_behav1.wcfg
+++ b/Bank_behav1.wcfg
@@ -11,13 +11,13 @@
       </db_ref>
    </db_ref_list>
    <zoom_setting>
-      <ZoomStartTime time="60476450fs"></ZoomStartTime>
-      <ZoomEndTime time="128876451fs"></ZoomEndTime>
-      <Cursor1Time time="515000000fs"></Cursor1Time>
+      <ZoomStartTime time="0fs"></ZoomStartTime>
+      <ZoomEndTime time="124700001fs"></ZoomEndTime>
+      <Cursor1Time time="68400000fs"></Cursor1Time>
    </zoom_setting>
    <column_width_setting>
       <NameColumnWidth column_width="175"></NameColumnWidth>
-      <ValueColumnWidth column_width="138"></ValueColumnWidth>
+      <ValueColumnWidth column_width="134"></ValueColumnWidth>
    </column_width_setting>
    <WVObjectSize size="33" />
    <wvobject fp_name="/CPU9bits_tb/clk" type="logic">
diff --git a/lab2CA.runs/impl_1/gen_run.xml b/lab2CA.runs/impl_1/gen_run.xml
index 2c0c43a..063b89e 100644
--- a/lab2CA.runs/impl_1/gen_run.xml
+++ b/lab2CA.runs/impl_1/gen_run.xml
@@ -1,14 +1,14 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <GenRun Id="impl_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1553093609">
+  <File Type="BITSTR-BMM" Name="CPU9bits_bd.bmm"/>
   <File Type="ROUTE-PWR" Name="CPU9bits_power_routed.rpt"/>
   <File Type="PA-TCL" Name="CPU9bits.tcl"/>
-  <File Type="BITSTR-BMM" Name="CPU9bits_bd.bmm"/>
+  <File Type="OPT-DCP" Name="CPU9bits_opt.dcp"/>
   <File Type="ROUTE-PWR-SUM" Name="CPU9bits_power_summary_routed.pb"/>
   <File Type="REPORTS-TCL" Name="CPU9bits_reports.tcl"/>
-  <File Type="OPT-DCP" Name="CPU9bits_opt.dcp"/>
   <File Type="OPT-HWDEF" Name="CPU9bits.hwdef"/>
-  <File Type="PWROPT-DCP" Name="CPU9bits_pwropt.dcp"/>
   <File Type="BG-BGN" Name="CPU9bits.bgn"/>
+  <File Type="PWROPT-DCP" Name="CPU9bits_pwropt.dcp"/>
   <File Type="PLACE-DCP" Name="CPU9bits_placed.dcp"/>
   <File Type="PLACE-PRE-SIMILARITY" Name="CPU9bits_incremental_reuse_pre_placed.rpt"/>
   <File Type="POSTPLACE-PWROPT-DCP" Name="CPU9bits_postplace_pwropt.dcp"/>
@@ -18,12 +18,12 @@
   <File Type="ROUTE-ERROR-DCP" Name="CPU9bits_routed_error.dcp"/>
   <File Type="ROUTE-DCP" Name="CPU9bits_routed.dcp"/>
   <File Type="ROUTE-BLACKBOX-DCP" Name="CPU9bits_routed_bb.dcp"/>
-  <File Type="BITSTR-LTX" Name="CPU9bits.ltx"/>
   <File Type="ROUTE-DRC-RPX" Name="CPU9bits_drc_routed.rpx"/>
-  <File Type="BITSTR-MMI" Name="CPU9bits.mmi"/>
+  <File Type="BITSTR-LTX" Name="CPU9bits.ltx"/>
   <File Type="ROUTE-METHODOLOGY-DRC" Name="CPU9bits_methodology_drc_routed.rpt"/>
-  <File Type="BITSTR-SYSDEF" Name="CPU9bits.sysdef"/>
+  <File Type="BITSTR-MMI" Name="CPU9bits.mmi"/>
   <File Type="ROUTE-METHODOLOGY-DRC-PB" Name="CPU9bits_methodology_drc_routed.pb"/>
+  <File Type="BITSTR-SYSDEF" Name="CPU9bits.sysdef"/>
   <File Type="ROUTE-TIMING-PB" Name="CPU9bits_timing_summary_routed.pb"/>
   <File Type="POSTROUTE-PHYSOPT-DCP" Name="CPU9bits_postroute_physopt.dcp"/>
   <File Type="POSTROUTE-PHYSOPT-BLACKBOX-DCP" Name="CPU9bits_postroute_physopt_bb.dcp"/>
@@ -31,8 +31,8 @@
   <File Type="BITSTR-RBT" Name="CPU9bits.rbt"/>
   <File Type="BITSTR-NKY" Name="CPU9bits.nky"/>
   <File Type="BG-DRC" Name="CPU9bits.drc"/>
-  <File Type="RDI-RDI" Name="CPU9bits.vdi"/>
   <File Type="ROUTE-CLK" Name="CPU9bits_clock_utilization_routed.rpt"/>
+  <File Type="RDI-RDI" Name="CPU9bits.vdi"/>
   <File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>
   <File Type="OPT-DRC" Name="CPU9bits_drc_opted.rpt"/>
   <File Type="PLACE-UTIL" Name="CPU9bits_utilization_placed.rpt"/>
diff --git a/lab2CA.sim/sim_1/behav/xsim/xelab.pb b/lab2CA.sim/sim_1/behav/xsim/xelab.pb
index 175ab9378d8334a5b87ce9004cf48bab7b237e57..3887e53ecf87a57e1ebbbae2995afbcdd9aa9197 100644
GIT binary patch
delta 1027
zcmbQMv{q}wA12TLj9gm9sX3|1B?_5&DXA3-s>MJ?Nxp)*YO%UPX0bwkX^BF9nnF^3
zX<kaP0Gkwxv5}>z7I#H)W^P$(QD$0ZvXK}UlcCu}1F`zt)ZF}{N+b4^)U?FXoDwS-
z!zhBw$=OOjv^ce>Sl=tZIMp*fFEKeYU*FkL!6z|EKPNHC$k|b^xG1?;zc|0NC^@w_
z-cUa;wOl_Xu_VzKY^q+F03#NYCAgSO%mtXhGW95yS}-~=MzI?j=o*_Fm}W2(uvM^4
zU}O+r;-Z$9&C#7R(SdECg1};6g1}-B1%c(j1cBw?2?A3CXb>n6$_SgkF{$$b0FA>x
AH~;_u

delta 12
TcmZ3hHCJiFAEwPb?23E<A<hIk

diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
index 41c6e18..ce99532 100644
--- a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
+++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
@@ -1,10 +1,10 @@
-webtalk_init -webtalk_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/
+webtalk_init -webtalk_dir C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/
 webtalk_register_client -client project
-webtalk_add_data -client project -key date_generated -value "Sun Mar 24 16:09:25 2019" -context "software_version_and_target_device"
+webtalk_add_data -client project -key date_generated -value "Sun Mar 24 16:34:26 2019" -context "software_version_and_target_device"
 webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device"
 webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device"
 webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device"
-webtalk_add_data -client project -key registration_id -value "174150793_174150794_210688225_140" -context "software_version_and_target_device"
+webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device"
 webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device"
 webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device"
 webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device"
@@ -12,21 +12,31 @@ webtalk_add_data -client project -key target_family -value "not_applicable" -con
 webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device"
 webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device"
 webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device"
-webtalk_add_data -client project -key random_id -value "4e917e26-7591-4435-9135-15bd446b0238" -context "software_version_and_target_device"
+webtalk_add_data -client project -key random_id -value "17336daf-0d92-4f07-b4a4-ff1c52043edb" -context "software_version_and_target_device"
 webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device"
-webtalk_add_data -client project -key project_iteration -value "97" -context "software_version_and_target_device"
+webtalk_add_data -client project -key project_iteration -value "82" -context "software_version_and_target_device"
 webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment"
 webtalk_add_data -client project -key os_release -value "major release  (build 9200)" -context "user_environment"
-webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) CPU E5-1620 v3 @ 3.50GHz" -context "user_environment"
-webtalk_add_data -client project -key cpu_speed -value "3492 MHz" -context "user_environment"
+webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i5-3230M CPU @ 2.60GHz" -context "user_environment"
+webtalk_add_data -client project -key cpu_speed -value "2594 MHz" -context "user_environment"
 webtalk_add_data -client project -key total_processors -value "1" -context "user_environment"
-webtalk_add_data -client project -key system_ram -value "34.000 GB" -context "user_environment"
+webtalk_add_data -client project -key system_ram -value "8.000 GB" -context "user_environment"
 webtalk_register_client -client xsim
-webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options"
-webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage"
-webtalk_add_data -client xsim -key runtime -value "520 ns" -context "xsim\\usage"
-webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage"
-webtalk_add_data -client xsim -key Simulation_Time -value "0.03_sec" -context "xsim\\usage"
-webtalk_add_data -client xsim -key Simulation_Memory -value "6444_KB" -context "xsim\\usage"
-webtalk_transmit -clientid 1317412355 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
+webtalk_add_data -client xsim -key File_Counter -value "9" -context "xsim\\command_line_options"
+webtalk_add_data -client xsim -key Command -value "xelab" -context "xsim\\command_line_options"
+webtalk_add_data -client xsim -key Vhdl2008 -value "false" -context "xsim\\command_line_options"
+webtalk_add_data -client xsim -key GenDLL -value "false" -context "xsim\\command_line_options"
+webtalk_add_data -client xsim -key SDFModeling -value "false" -context "xsim\\command_line_options"
+webtalk_add_data -client xsim -key HWCosim -value "false" -context "xsim\\command_line_options"
+webtalk_add_data -client xsim -key DPI_Used -value "false" -context "xsim\\command_line_options"
+webtalk_add_data -client xsim -key Debug -value "typical" -context "xsim\\command_line_options"
+webtalk_add_data -client xsim -key Simulation_Image_Code -value "109 KB" -context "xsim\\usage"
+webtalk_add_data -client xsim -key Simulation_Image_Data -value "19 KB" -context "xsim\\usage"
+webtalk_add_data -client xsim -key Total_Nets -value "0" -context "xsim\\usage"
+webtalk_add_data -client xsim -key Total_Processes -value "281" -context "xsim\\usage"
+webtalk_add_data -client xsim -key Total_Instances -value "144" -context "xsim\\usage"
+webtalk_add_data -client xsim -key Xilinx_HDL_Libraries_Used -value "secureip unimacro_ver unisims_ver " -context "xsim\\usage"
+webtalk_add_data -client xsim -key Compiler_Time -value "1.19_sec" -context "xsim\\usage"
+webtalk_add_data -client xsim -key Compiler_Memory -value "49056_KB" -context "xsim\\usage"
+webtalk_transmit -clientid 4125363012 -regid "" -xml C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
 webtalk_terminate
diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
index 32c1368078dfd772a78f27f019e5e23243b27ff0..e0224a8ea2ee24f7f975d5187575a46556b7a54f 100644
GIT binary patch
literal 19925
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zwKui*=46*t%c5UN8nYl8eIf4aD^ge7F7<QG{FYTRIQIignJexD(v67Icy|_0OQx&%
zOwD3I_XF#^B^-%AwPpN%ZE@drP@;Yq{IEP#&rr-ZL>@|TK^jn!m(CXk<ZD@w0)7T|
zzSNI|*f|k09CMVa1vvEaWtjeZIKPAvwQ<&=xQ+2p;puvKxr1^{L9C%xTiE-72dL*0
zfq`$l@@e<d+sM5okKvK!^$_(!Lr34^>!dbT4Nl@x=Cu;xOT|}(pmxC1QC6NNhkqHk
z;LLNWIM%d@X`1u1!LKUfc%}_R*~ISUdFxee6{m!4;@Z9QdFQPHRr<(Sf#iZxE3)sK
zp_t`=Mz$=4ufDCaT;?r<N{3<A7kZRg+GWsVtj>th1ZAi0QG3n6<%|K?X#3jk_UQxD
zfl9wZBD~}j>u$TdnOz_Fc-HKK@9eYr+oR$M{;Sg$9Z%ghhqow3)P#E;t#ZEWe&TE&
zPj6VL&zwW|^?aYM!pRi2WB+!WAf>v3kA>N2be*SxYrtD<>DV3vHAWJzQ+~y@i%Cv$
zHiRRkGSC4t+0r{|Cqr|$i&f=^6l!(}&!x|el<pmV5zunlNigr><PKqc>lWiAt=3ip
zLDRXPk1mnE*bBCFwc4HaTZq|lzh%7f<DJ8gyY9YyYoOtt8>gS0G?NI)I&(O#D=li?
zmL(_!ar|sIw}-dkui~>BIY({o?k-82zhg-pxqkP@y+y^Ei`(1;k-n<qyJVxDU+Kyz
zEve}K`u>qDqv5X<<A{KOx9T%L-LW}upYVqU==el*5AQp9r(PvhVamT@!ok;|<yrc}
z+06E7<%~($`uE)<6S{K&(bLvY3+J!B2To4U?%wkf&40)AB{%ov_3lB@`zQA$)M^|b
zwUBVSoN|KaRCs=i`8J8ewC+c-ceJKx-N(e0og&W&SDW`7DL$yk)Vz0M%5Gi7Zc4ZR
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zARg(Bb<%L(;`3<wO6hU*GU9kptKF?fF)?p^o)XNBES)|l={Td~s#Fc@4JO1Ti1LhA
z&v!fY4H8K99{)V^*)`TZI6SFPbEUeoYDd{j(c9cBu%-bXOVUF8ahr!RKgx`9AMFx0
zoAX@lWHj{m`j4&D)M}h9;#ZobTtBT~a?{fCEkshE?EOBqFwdYu38x-@_lvopL|Rmd
zF8v^_iO}cpq~DidQeSWw)+2}3#oi6L+1}^%+`;UfZ=kBL?vq8vMSs7i#|GYJIP@*@
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z7m<tbrI9TIyD`<)V@B`1*5}O=2J`N5xGhwto~okY)%Dw>+D3N*mF8zL#{*3FXru&c
zH7QLwdW15wx;hRj&CZaK&_cHc|MwFenU_<wVbso%#up0Hx4bng+*-@Vkh%d`w4bB|
P(VtOS+-)ORJ(2$pET9|{

diff --git a/lab2CA.sim/sim_1/behav/xsim/xvlog.pb b/lab2CA.sim/sim_1/behav/xsim/xvlog.pb
index e2015574ec4c26acedc8bb07947d6680eebb0c5b..b4146de3776acc2ac5f64e808a41bb57cecb0e37 100644
GIT binary patch
delta 236
zcmccPe8+i07Qa`1ajIu}USe`)zP_`g!ejv^xsB7a7}3Qy3oyBeq6>l)Z*CNC!cYyC
xFp#XlE^$+;47)^)3>Q|3$u%-OllRL?FqxW6zA5_+t26${O~I;n^IipcMgT=)ODg~X

delta 236
zcmccPe8+i07Jq7TYEEL3zN@pVv8lO%?qmTbxsB7a7}3Qy3oyBeq6>l)Z*CNC!cYyC
xFp#XlE^$+;47)^)3>Q|3$u%-OllRL?Fc}+8zA5_+t26${O~I;n^IipcMgZeWL<|4`

diff --git a/lab2CA.srcs/sources_1/new/dataMemory.v b/lab2CA.srcs/sources_1/new/dataMemory.v
index b9c116e..d88881c 100644
--- a/lab2CA.srcs/sources_1/new/dataMemory.v
+++ b/lab2CA.srcs/sources_1/new/dataMemory.v
@@ -9,23 +9,46 @@ module dataMemory(
     reg [8:0] memory [15:0];
     
     initial begin
-        // String Compare Memory
-        memory[0] <= 9'b000000100;
-        memory[1] <= 9'b000001000;
-        memory[2] <= 9'b000001100;
-        memory[3] <= 9'b010101010;
-        memory[4] <= 9'b000001111;
-        memory[5] <= 9'b000000100;
-        memory[6] <= 9'b000000011;
-        memory[7] <= 9'b000000000;
-        memory[8] <= 9'b000001111;
-        memory[9] <= 9'b000000100;
-        memory[10] <= 9'b000000010;
-        memory[11] <= 9'b000000000;
-        memory[12] <= 9'b000000000;
-        memory[13] <= 9'b000000000;
-        memory[14] <= 9'b000000000;
-        memory[15] <= 9'b000000000;
+//        // String Compare Memory
+//        memory[0] <= 9'b000000100;
+//        memory[1] <= 9'b000001000;
+//        memory[2] <= 9'b000001100;
+//        memory[3] <= 9'b010101010;
+//        memory[4] <= 9'b000001111;
+//        memory[5] <= 9'b000000100;
+//        memory[6] <= 9'b000000011;
+//        memory[7] <= 9'b000000000;
+//        memory[8] <= 9'b000001111;
+//        memory[9] <= 9'b000000100;
+//        memory[10] <= 9'b000000010;
+//        memory[11] <= 9'b000000000;
+//        memory[12] <= 9'b000000000;
+//        memory[13] <= 9'b000000000;
+//        memory[14] <= 9'b000000000;
+//        memory[15] <= 9'b000000000;
+
+        // Binary Search Memory
+         memory[0] <= 9'b000000000;
+         memory[1] <= 9'b000000111;
+         memory[2] <= 9'b000000001;
+         memory[3] <= 9'b000000010;
+         memory[4] <= 9'b000000011;
+         memory[5] <= 9'b000000100;
+         memory[6] <= 9'b000000101;
+         memory[7] <= 9'b000000110;
+         memory[8] <= 9'b000000111;
+         memory[9] <= 9'b000001000;
+        memory[10] <= 9'b000001001;
+        memory[11] <= 9'b000001010;
+        memory[12] <= 9'b000001011;
+        memory[13] <= 9'b000001100;
+        memory[14] <= 9'b000001101;
+        memory[15] <= 9'b000001110;
+        memory[16] <= 9'b000001111;
+        memory[17] <= 9'b000010000;
+        memory[18] <= 9'b000010001;
+        memory[19] <= 9'b000010010;
+        
     end
 
     always@(address, clk, memory)begin
diff --git a/lab2CA.srcs/sources_1/new/instructionMemory.v b/lab2CA.srcs/sources_1/new/instructionMemory.v
index 7347372..e6210eb 100644
--- a/lab2CA.srcs/sources_1/new/instructionMemory.v
+++ b/lab2CA.srcs/sources_1/new/instructionMemory.v
@@ -34,51 +34,117 @@ module instructionMemory(
         
         
         //String Compare
-        memory[0] <= 9'b000000000;
-        memory[1] <= 9'b010000000;
-        memory[2] <= 9'b010001000;
-        memory[3] <= 9'b010010000;
-        memory[4] <= 9'b010011000;
-        memory[5] <= 9'b000100000;
-        memory[6] <= 9'b011001001;
-        memory[7] <= 9'b000101010;
-        memory[8] <= 9'b011010010;
-        memory[9] <= 9'b000110100;
-        memory[10] <= 9'b011011011;
-        memory[11] <= 9'b000111110;
-        memory[12] <= 9'b101010000;
-        memory[13] <= 9'b101000010;
-        memory[14] <= 9'b101001100;
-        memory[15] <= 9'b101011110; //ends initialization
-        memory[16] <= 9'b101000011;
-        memory[17] <= 9'b101001101;
-        memory[18] <= 9'b000110000;
-        memory[19] <= 9'b000111010;
-        memory[20] <= 9'b110010001;
-        memory[21] <= 9'b100100001;
-        memory[22] <= 9'b100110000;
-        memory[23] <= 9'b110011001;
-        memory[24] <= 9'b100100001;
-        memory[25] <= 9'b100101101;
-        memory[26] <= 9'b011000001;
-        memory[27] <= 9'b011001001;
-        memory[28] <= 9'b101000010;
-        memory[29] <= 9'b101001100;
-        memory[30] <= 9'b010110111;
-        memory[31] <= 9'b110010001;
-        memory[32] <= 9'b101110010;
-        memory[33] <= 9'b101000000;
-        memory[34] <= 9'b101001110;
-        memory[35] <= 9'b001001000;
-        memory[36] <= 9'b011000001;
-        memory[37] <= 9'b101000000;
-        memory[38] <= 9'b101111000;
-        memory[39] <= 9'b000000000;
-        
+//         memory[0] <= 9'b000000000;
+//         memory[1] <= 9'b010000000;
+//         memory[2] <= 9'b010001000;
+//         memory[3] <= 9'b010010000;
+//         memory[4] <= 9'b010011000;
+//         memory[5] <= 9'b000100000;
+//         memory[6] <= 9'b011001001;
+//         memory[7] <= 9'b000101010;
+//         memory[8] <= 9'b011010010;
+//         memory[9] <= 9'b000110100;
+//        memory[10] <= 9'b011011011;
+//        memory[11] <= 9'b000111110;
+//        memory[12] <= 9'b101010000;
+//        memory[13] <= 9'b101000010;
+//        memory[14] <= 9'b101001100;
+//        memory[15] <= 9'b101011110; //ends initialization
+//        memory[16] <= 9'b101000011;
+//        memory[17] <= 9'b101001101;
+//        memory[18] <= 9'b000110000;
+//        memory[19] <= 9'b000111010;
+//        memory[20] <= 9'b110010001;
+//        memory[21] <= 9'b100100001;
+//        memory[22] <= 9'b100110000;
+//        memory[23] <= 9'b110011001;
+//        memory[24] <= 9'b100100001;
+//        memory[25] <= 9'b100101101;
+//        memory[26] <= 9'b011000001;
+//        memory[27] <= 9'b011001001;
+//        memory[28] <= 9'b101000010;
+//        memory[29] <= 9'b101001100;
+//        memory[30] <= 9'b010110111;
+//        memory[31] <= 9'b110010001;
+//        memory[32] <= 9'b101110010;
+//        memory[33] <= 9'b101000000;
+//        memory[34] <= 9'b101001110;
+//        memory[35] <= 9'b001001000;
+//        memory[36] <= 9'b011000001;
+//        memory[37] <= 9'b101000000;
+//        memory[38] <= 9'b101111000;
+//        memory[39] <= 9'b000000000;
+
+         // Binary Search  
         
+ 
+           memory[0] <= 9'b000000000;
+           memory[1] <= 9'b000000000; 
+           memory[2] <= 9'b000000000; 
+           memory[3] <= 9'b000000000; 
+           memory[4] <= 9'b000000000; 
+           memory[5] <= 9'b000000000; 
+           memory[6] <= 9'b011001011; //addi R1, 3 (N = 3)  
+           memory[7] <= 9'b011001011; //addi R1, 3 (N = 3) 
+           memory[8] <= 9'b011001011; //addi R1, 3 (N = 3) 
+           memory[9] <= 9'b011001011; //addi R1, 3 (N = 3) 
+          memory[10] <= 9'b011001011; //addi R1, 3 (N = 3) 
+          memory[11] <= 9'b011010010; //addi R2, 2 (inputAddr = 2)
+          memory[12] <= 9'b000111110; //lb R3, R3                 
+          memory[13] <= 9'b101011010; //banks R3, 1               
+          memory[14] <= 9'b011001011; //addi R1, 3 (N = 3)        
+          memory[15] <= 9'b101000000; //loop: banks R0, 0         
+          memory[16] <= 9'b011100010; //slt R0, R1                
+          memory[17] <= 9'b110000001; //beq R0, Exit              
+          memory[18] <= 9'b100100001; //j Skip0                   
+          memory[19] <= 9'b100101110; //Exit: j Loose             
+          memory[20] <= 9'b010101000; //Skip0: add R2, R0         
+          memory[21] <= 9'b010101010; //add R2, R1                
+          memory[22] <= 9'b111110000; //sll R2                    
+          memory[23] <= 9'b101011011; //bankl R3,1                
+          memory[24] <= 9'b010111100; //add R3, R2                
+          memory[25] <= 9'b101001100; //banks R1, 2               
+          memory[26] <= 9'b000100110; //lb R0, R3                 
+          memory[27] <= 9'b010001000; //zero R1                   
+          memory[28] <= 9'b011001010; //addi R1, 1 (numAddr = 1)  
+          memory[29] <= 9'b000101010; //lb R1, R1                 
+          memory[30] <= 9'b100100001; //j SkipU                   
+          memory[31] <= 9'b101110001; //j TransLoop               
+          memory[32] <= 9'b101010110; //SkipU: banks R2, 3        
+          memory[33] <= 9'b100100001; //j SkipD                   
+          memory[34] <= 9'b100110111; //j TransLoose              
+          memory[35] <= 9'b010010000; //SkipD: zero R2            
+          memory[36] <= 9'b010110010; //add R2, R1                
+          memory[37] <= 9'b010101001; //sub R1, R0                
+          memory[38] <= 9'b110001001; //beq R1, Go1               
+          memory[39] <= 9'b100100001; //j Skip1                   
+          memory[40] <= 9'b100101001; //Go1: j Win                
+          memory[41] <= 9'b010001000; //Skip1: zero R1            
+          memory[42] <= 9'b010101100; //add R1, R2                
+          memory[43] <= 9'b011100010; //slt R0, R1                
+          memory[44] <= 9'b110001001; //beq R1, Go2               
+          memory[45] <= 9'b100100110; //j Skip2                   
+          memory[46] <= 9'b010000000; //Go2: zero R0              
+          memory[47] <= 9'b011000010; //addi R0, 1                
+          memory[48] <= 9'b101001111; //bankl R1,3                
+          memory[49] <= 9'b010100010; //add R0, R1                
+          memory[50] <= 9'b101001101; //bankl R1,2                
+          memory[51] <= 9'b101110101; //j loop                    
+          memory[52] <= 9'b010001000; //Skip2: zero R1            
+          memory[53] <= 9'b011001111; //addi R1, -1               
+          memory[54] <= 9'b101000111; //bankl R0, 3               
+          memory[55] <= 9'b010101000; //add R1, R0                
+          memory[56] <= 9'b101000001; //bankl R0,0                
+          memory[57] <= 9'b101111011; //j loop                    
+          memory[58] <= 9'b010000000; //Loose: zero R0            
+          memory[59] <= 9'b011000111; //addi R0, -1               
+          memory[60] <= 9'b101000110; //banks R0, 3               
+          memory[61] <= 9'b100100000; //j Win                     
+          memory[62] <= 9'b000000000; //Win: halt                 
+          
+ 
     end
     
-    
     always@(address)begin
         readData <= memory[address];
     end
diff --git a/lab2CA.xpr b/lab2CA.xpr
index d15e3f5..9a80179 100644
--- a/lab2CA.xpr
+++ b/lab2CA.xpr
@@ -3,7 +3,7 @@
 <!--                                                         -->
 <!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.   -->
 
-<Project Version="7" Minor="39" Path="C:/Users/ecelab/ECE3570-Lab/lab2CA.xpr">
+<Project Version="7" Minor="39" Path="C:/Users/JoseIgnacio/CA Lab/lab2CA.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
     <Option Name="Id" Val="0a5803efda44405bb28bbf43ba22e808"/>
@@ -31,7 +31,7 @@
     <Option Name="EnableBDX" Val="FALSE"/>
     <Option Name="DSAVendor" Val="xilinx"/>
     <Option Name="DSANumComputeUnits" Val="60"/>
-    <Option Name="WTXSimLaunchSim" Val="295"/>
+    <Option Name="WTXSimLaunchSim" Val="296"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>

From 8e724093865fe73728b1ce3743d7e269068975a7 Mon Sep 17 00:00:00 2001
From: WilliamMiceli <git@williammiceli.me>
Date: Sun, 24 Mar 2019 16:54:06 -0400
Subject: [PATCH 2/2] Added Bubble Sort instructions and initial data memory

---
 lab2CA.srcs/sources_1/new/dataMemory.v        |  67 +++++--
 lab2CA.srcs/sources_1/new/instructionMemory.v | 177 +++++++++++-------
 2 files changed, 160 insertions(+), 84 deletions(-)

diff --git a/lab2CA.srcs/sources_1/new/dataMemory.v b/lab2CA.srcs/sources_1/new/dataMemory.v
index d88881c..95b0a21 100644
--- a/lab2CA.srcs/sources_1/new/dataMemory.v
+++ b/lab2CA.srcs/sources_1/new/dataMemory.v
@@ -27,27 +27,54 @@ module dataMemory(
 //        memory[14] <= 9'b000000000;
 //        memory[15] <= 9'b000000000;
 
+        // Bubble Sort Initial Memory
+        
+           memory[0] <= 9'b000011000;
+           memory[1] <= 9'b000000000;
+           memory[2] <= 9'b000100000;
+           memory[3] <= 9'b010001000;
+           memory[4] <= 9'b010010000;
+           memory[5] <= 9'b010011000;
+           memory[6] <= 9'b101001000;
+           memory[7] <= 9'b101001010;
+           memory[8] <= 9'b000100011;
+           memory[9] <= 9'b101001001;
+          memory[10] <= 9'b011001001;
+          memory[11] <= 9'b001001000;
+          memory[12] <= 9'b101001001;
+          memory[13] <= 9'b011101000;
+          memory[14] <= 9'b110001010;
+          memory[15] <= 9'b000100001;
+          memory[16] <= 9'b100110100;
+          memory[17] <= 9'b000001001;
+          memory[18] <= 9'b011001001;
+          memory[19] <= 9'b000110010;
+          memory[20] <= 9'b000000001;
+          memory[21] <= 9'b000111010;
+          memory[22] <= 9'b101011110;
+          memory[23] <= 9'b011111100;
+
         // Binary Search Memory
-         memory[0] <= 9'b000000000;
-         memory[1] <= 9'b000000111;
-         memory[2] <= 9'b000000001;
-         memory[3] <= 9'b000000010;
-         memory[4] <= 9'b000000011;
-         memory[5] <= 9'b000000100;
-         memory[6] <= 9'b000000101;
-         memory[7] <= 9'b000000110;
-         memory[8] <= 9'b000000111;
-         memory[9] <= 9'b000001000;
-        memory[10] <= 9'b000001001;
-        memory[11] <= 9'b000001010;
-        memory[12] <= 9'b000001011;
-        memory[13] <= 9'b000001100;
-        memory[14] <= 9'b000001101;
-        memory[15] <= 9'b000001110;
-        memory[16] <= 9'b000001111;
-        memory[17] <= 9'b000010000;
-        memory[18] <= 9'b000010001;
-        memory[19] <= 9'b000010010;
+//         memory[0] <= 9'b000000000;
+//         memory[1] <= 9'b000000111;
+//         memory[2] <= 9'b000000001;
+//         memory[3] <= 9'b000000010;
+//         memory[4] <= 9'b000000011;
+//         memory[5] <= 9'b000000100;
+//         memory[6] <= 9'b000000101;
+//         memory[7] <= 9'b000000110;
+//         memory[8] <= 9'b000000111;
+//         memory[9] <= 9'b000001000;
+//        memory[10] <= 9'b000001001;
+//        memory[11] <= 9'b000001010;
+//        memory[12] <= 9'b000001011;
+//        memory[13] <= 9'b000001100;
+//        memory[14] <= 9'b000001101;
+//        memory[15] <= 9'b000001110;
+//        memory[16] <= 9'b000001111;
+//        memory[17] <= 9'b000010000;
+//        memory[18] <= 9'b000010001;
+//        memory[19] <= 9'b000010010;
         
     end
 
diff --git a/lab2CA.srcs/sources_1/new/instructionMemory.v b/lab2CA.srcs/sources_1/new/instructionMemory.v
index e6210eb..2071903 100644
--- a/lab2CA.srcs/sources_1/new/instructionMemory.v
+++ b/lab2CA.srcs/sources_1/new/instructionMemory.v
@@ -75,72 +75,121 @@ module instructionMemory(
 //        memory[38] <= 9'b101111000;
 //        memory[39] <= 9'b000000000;
 
+
+    // Bubble Sort
+           memory[0] <= 9'b000000001;
+           memory[1] <= 9'b010000000;
+           memory[2] <= 9'b000100000;
+           memory[3] <= 9'b010001000;
+           memory[4] <= 9'b010010000;
+           memory[5] <= 9'b010011000;
+           memory[6] <= 9'b101001000;
+           memory[7] <= 9'b101001010;
+           memory[8] <= 9'b100100011;
+           memory[9] <= 9'b101001001;
+          memory[10] <= 9'b011001001;
+          memory[11] <= 9'b101001000;
+          memory[12] <= 9'b101001001;
+          memory[13] <= 9'b011101000;
+          memory[14] <= 9'b110001010;
+          memory[15] <= 9'b100100001;
+          memory[16] <= 9'b100110100;
+          memory[17] <= 9'b101001001;
+          memory[18] <= 9'b011001001;
+          memory[19] <= 9'b000110010;
+          memory[20] <= 9'b011001001;
+          memory[21] <= 9'b000111010;
+          memory[22] <= 9'b101011110;
+          memory[23] <= 9'b011111100;
+          memory[24] <= 9'b110011010;
+          memory[25] <= 9'b100100001;
+          memory[26] <= 9'b101110010;
+          memory[27] <= 9'b101001001;
+          memory[28] <= 9'b011001001;
+          memory[29] <= 9'b101011111;
+          memory[30] <= 9'b001011010;
+          memory[31] <= 9'b011001001;
+          memory[32] <= 9'b001010010;
+          memory[33] <= 9'b010001000;
+          memory[34] <= 9'b011001001;
+          memory[35] <= 9'b101001010;
+          memory[36] <= 9'b101111100;
+          memory[37] <= 9'b101001011;
+          memory[38] <= 9'b110001001;
+          memory[39] <= 9'b100100001;
+          memory[40] <= 9'b100100011;
+          memory[41] <= 9'b010001000;
+          memory[42] <= 9'b101001000;
+          memory[43] <= 9'b101111011;
+          memory[44] <= 9'b000000000;
+
+
          // Binary Search  
         
- 
-           memory[0] <= 9'b000000000;
-           memory[1] <= 9'b000000000; 
-           memory[2] <= 9'b000000000; 
-           memory[3] <= 9'b000000000; 
-           memory[4] <= 9'b000000000; 
-           memory[5] <= 9'b000000000; 
-           memory[6] <= 9'b011001011; //addi R1, 3 (N = 3)  
-           memory[7] <= 9'b011001011; //addi R1, 3 (N = 3) 
-           memory[8] <= 9'b011001011; //addi R1, 3 (N = 3) 
-           memory[9] <= 9'b011001011; //addi R1, 3 (N = 3) 
-          memory[10] <= 9'b011001011; //addi R1, 3 (N = 3) 
-          memory[11] <= 9'b011010010; //addi R2, 2 (inputAddr = 2)
-          memory[12] <= 9'b000111110; //lb R3, R3                 
-          memory[13] <= 9'b101011010; //banks R3, 1               
-          memory[14] <= 9'b011001011; //addi R1, 3 (N = 3)        
-          memory[15] <= 9'b101000000; //loop: banks R0, 0         
-          memory[16] <= 9'b011100010; //slt R0, R1                
-          memory[17] <= 9'b110000001; //beq R0, Exit              
-          memory[18] <= 9'b100100001; //j Skip0                   
-          memory[19] <= 9'b100101110; //Exit: j Loose             
-          memory[20] <= 9'b010101000; //Skip0: add R2, R0         
-          memory[21] <= 9'b010101010; //add R2, R1                
-          memory[22] <= 9'b111110000; //sll R2                    
-          memory[23] <= 9'b101011011; //bankl R3,1                
-          memory[24] <= 9'b010111100; //add R3, R2                
-          memory[25] <= 9'b101001100; //banks R1, 2               
-          memory[26] <= 9'b000100110; //lb R0, R3                 
-          memory[27] <= 9'b010001000; //zero R1                   
-          memory[28] <= 9'b011001010; //addi R1, 1 (numAddr = 1)  
-          memory[29] <= 9'b000101010; //lb R1, R1                 
-          memory[30] <= 9'b100100001; //j SkipU                   
-          memory[31] <= 9'b101110001; //j TransLoop               
-          memory[32] <= 9'b101010110; //SkipU: banks R2, 3        
-          memory[33] <= 9'b100100001; //j SkipD                   
-          memory[34] <= 9'b100110111; //j TransLoose              
-          memory[35] <= 9'b010010000; //SkipD: zero R2            
-          memory[36] <= 9'b010110010; //add R2, R1                
-          memory[37] <= 9'b010101001; //sub R1, R0                
-          memory[38] <= 9'b110001001; //beq R1, Go1               
-          memory[39] <= 9'b100100001; //j Skip1                   
-          memory[40] <= 9'b100101001; //Go1: j Win                
-          memory[41] <= 9'b010001000; //Skip1: zero R1            
-          memory[42] <= 9'b010101100; //add R1, R2                
-          memory[43] <= 9'b011100010; //slt R0, R1                
-          memory[44] <= 9'b110001001; //beq R1, Go2               
-          memory[45] <= 9'b100100110; //j Skip2                   
-          memory[46] <= 9'b010000000; //Go2: zero R0              
-          memory[47] <= 9'b011000010; //addi R0, 1                
-          memory[48] <= 9'b101001111; //bankl R1,3                
-          memory[49] <= 9'b010100010; //add R0, R1                
-          memory[50] <= 9'b101001101; //bankl R1,2                
-          memory[51] <= 9'b101110101; //j loop                    
-          memory[52] <= 9'b010001000; //Skip2: zero R1            
-          memory[53] <= 9'b011001111; //addi R1, -1               
-          memory[54] <= 9'b101000111; //bankl R0, 3               
-          memory[55] <= 9'b010101000; //add R1, R0                
-          memory[56] <= 9'b101000001; //bankl R0,0                
-          memory[57] <= 9'b101111011; //j loop                    
-          memory[58] <= 9'b010000000; //Loose: zero R0            
-          memory[59] <= 9'b011000111; //addi R0, -1               
-          memory[60] <= 9'b101000110; //banks R0, 3               
-          memory[61] <= 9'b100100000; //j Win                     
-          memory[62] <= 9'b000000000; //Win: halt                 
+
+//           memory[0] <= 9'b000000000;
+//           memory[1] <= 9'b000000000; 
+//           memory[2] <= 9'b000000000; 
+//           memory[3] <= 9'b000000000; 
+//           memory[4] <= 9'b000000000; 
+//           memory[5] <= 9'b000000000; 
+//           memory[6] <= 9'b011001011; //addi R1, 3 (N = 3)  
+//           memory[7] <= 9'b011001011; //addi R1, 3 (N = 3) 
+//           memory[8] <= 9'b011001011; //addi R1, 3 (N = 3) 
+//           memory[9] <= 9'b011001011; //addi R1, 3 (N = 3) 
+//          memory[10] <= 9'b011001011; //addi R1, 3 (N = 3) 
+//          memory[11] <= 9'b011010010; //addi R2, 2 (inputAddr = 2)
+//          memory[12] <= 9'b000111110; //lb R3, R3                 
+//          memory[13] <= 9'b101011010; //banks R3, 1               
+//          memory[14] <= 9'b011001011; //addi R1, 3 (N = 3)        
+//          memory[15] <= 9'b101000000; //loop: banks R0, 0         
+//          memory[16] <= 9'b011100010; //slt R0, R1                
+//          memory[17] <= 9'b110000001; //beq R0, Exit              
+//          memory[18] <= 9'b100100001; //j Skip0                   
+//          memory[19] <= 9'b100101110; //Exit: j Loose             
+//          memory[20] <= 9'b010101000; //Skip0: add R2, R0         
+//          memory[21] <= 9'b010101010; //add R2, R1                
+//          memory[22] <= 9'b111110000; //sll R2                    
+//          memory[23] <= 9'b101011011; //bankl R3,1                
+//          memory[24] <= 9'b010111100; //add R3, R2                
+//          memory[25] <= 9'b101001100; //banks R1, 2               
+//          memory[26] <= 9'b000100110; //lb R0, R3                 
+//          memory[27] <= 9'b010001000; //zero R1                   
+//          memory[28] <= 9'b011001010; //addi R1, 1 (numAddr = 1)  
+//          memory[29] <= 9'b000101010; //lb R1, R1                 
+//          memory[30] <= 9'b100100001; //j SkipU                   
+//          memory[31] <= 9'b101110001; //j TransLoop               
+//          memory[32] <= 9'b101010110; //SkipU: banks R2, 3        
+//          memory[33] <= 9'b100100001; //j SkipD                   
+//          memory[34] <= 9'b100110111; //j TransLoose              
+//          memory[35] <= 9'b010010000; //SkipD: zero R2            
+//          memory[36] <= 9'b010110010; //add R2, R1                
+//          memory[37] <= 9'b010101001; //sub R1, R0                
+//          memory[38] <= 9'b110001001; //beq R1, Go1               
+//          memory[39] <= 9'b100100001; //j Skip1                   
+//          memory[40] <= 9'b100101001; //Go1: j Win                
+//          memory[41] <= 9'b010001000; //Skip1: zero R1            
+//          memory[42] <= 9'b010101100; //add R1, R2                
+//          memory[43] <= 9'b011100010; //slt R0, R1                
+//          memory[44] <= 9'b110001001; //beq R1, Go2               
+//          memory[45] <= 9'b100100110; //j Skip2                   
+//          memory[46] <= 9'b010000000; //Go2: zero R0              
+//          memory[47] <= 9'b011000010; //addi R0, 1                
+//          memory[48] <= 9'b101001111; //bankl R1,3                
+//          memory[49] <= 9'b010100010; //add R0, R1                
+//          memory[50] <= 9'b101001101; //bankl R1,2                
+//          memory[51] <= 9'b101110101; //j loop                    
+//          memory[52] <= 9'b010001000; //Skip2: zero R1            
+//          memory[53] <= 9'b011001111; //addi R1, -1               
+//          memory[54] <= 9'b101000111; //bankl R0, 3               
+//          memory[55] <= 9'b010101000; //add R1, R0                
+//          memory[56] <= 9'b101000001; //bankl R0,0                
+//          memory[57] <= 9'b101111011; //j loop                    
+//          memory[58] <= 9'b010000000; //Loose: zero R0            
+//          memory[59] <= 9'b011000111; //addi R0, -1               
+//          memory[60] <= 9'b101000110; //banks R0, 3               
+//          memory[61] <= 9'b100100000; //j Win                     
+//          memory[62] <= 9'b000000000; //Win: halt                 
           
  
     end