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jose.rodriguezlabra
2019-03-14 14:37:58 -04:00
parent 11a1d99e92
commit 08e3659ba3
50 changed files with 114 additions and 2909 deletions
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lab2CA.runs/synth_1/CPU9bits.vds
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#-----------------------------------------------------------
# Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Wed Mar 13 12:44:56 2019
# Process ID: 10868
# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1
# Command line: vivado.exe -log CPU9bits.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl
# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1/CPU9bits.vds
# Journal file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1\vivado.jou
#-----------------------------------------------------------
source CPU9bits.tcl -notrace
Command: synth_design -top CPU9bits -part xc7k160tifbg484-2L
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160ti'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160ti'
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 9000
---------------------------------------------------------------------------------
Starting Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 364.543 ; gain = 101.914
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'CPU9bits' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
INFO: [Synth 8-6157] synthesizing module 'RegFile' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/RegFile.v:3]
INFO: [Synth 8-6157] synthesizing module 'decoder' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261]
INFO: [Synth 8-226] default block is never used [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:268]
INFO: [Synth 8-6155] done synthesizing module 'decoder' (1#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261]
INFO: [Synth 8-6157] synthesizing module 'register' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:777]
INFO: [Synth 8-6155] done synthesizing module 'register' (2#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:777]
INFO: [Synth 8-6157] synthesizing module 'mux_4_1' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:407]
INFO: [Synth 8-226] default block is never used [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:412]
INFO: [Synth 8-6155] done synthesizing module 'mux_4_1' (3#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:407]
INFO: [Synth 8-6155] done synthesizing module 'RegFile' (4#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/RegFile.v:3]
INFO: [Synth 8-6157] synthesizing module 'FetchUnit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
INFO: [Synth 8-6157] synthesizing module 'add_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56]
INFO: [Synth 8-6157] synthesizing module 'add_1bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
INFO: [Synth 8-6155] done synthesizing module 'add_1bit' (5#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
INFO: [Synth 8-6155] done synthesizing module 'add_9bit' (6#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56]
INFO: [Synth 8-6157] synthesizing module 'mux_2_1' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:336]
INFO: [Synth 8-226] default block is never used [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:342]
INFO: [Synth 8-6155] done synthesizing module 'mux_2_1' (7#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:336]
INFO: [Synth 8-6155] done synthesizing module 'FetchUnit' (8#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3]
INFO: [Synth 8-6157] synthesizing module 'ALU' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
INFO: [Synth 8-6157] synthesizing module 'sub_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:964]
INFO: [Synth 8-6157] synthesizing module 'twos_compliment_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1029]
INFO: [Synth 8-6157] synthesizing module 'not_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:687]
INFO: [Synth 8-6155] done synthesizing module 'not_9bit' (9#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:687]
INFO: [Synth 8-6155] done synthesizing module 'twos_compliment_9bit' (10#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1029]
INFO: [Synth 8-6155] done synthesizing module 'sub_9bit' (11#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:964]
INFO: [Synth 8-6157] synthesizing module 'or_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:724]
INFO: [Synth 8-6155] done synthesizing module 'or_9bit' (12#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:724]
INFO: [Synth 8-6157] synthesizing module 'nor_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:643]
INFO: [Synth 8-6155] done synthesizing module 'nor_9bit' (13#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:643]
INFO: [Synth 8-6157] synthesizing module 'and_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175]
INFO: [Synth 8-6155] done synthesizing module 'and_9bit' (14#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175]
INFO: [Synth 8-6157] synthesizing module 'shift_left' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:853]
INFO: [Synth 8-6155] done synthesizing module 'shift_left' (15#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:853]
INFO: [Synth 8-6157] synthesizing module 'shift_right_logical' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890]
INFO: [Synth 8-6155] done synthesizing module 'shift_right_logical' (16#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890]
INFO: [Synth 8-6157] synthesizing module 'shift_right_arithmetic' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:927]
INFO: [Synth 8-6155] done synthesizing module 'shift_right_arithmetic' (17#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:927]
INFO: [Synth 8-6157] synthesizing module 'less_than' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:320]
INFO: [Synth 8-6155] done synthesizing module 'less_than' (18#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:320]
INFO: [Synth 8-6157] synthesizing module 'BEQ' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1078]
INFO: [Synth 8-6155] done synthesizing module 'BEQ' (19#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1078]
INFO: [Synth 8-6157] synthesizing module 'mux_16_1' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:535]
INFO: [Synth 8-226] default block is never used [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:541]
INFO: [Synth 8-6155] done synthesizing module 'mux_16_1' (20#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:535]
WARNING: [Synth 8-3848] Net result_L in module/entity ALU does not have driver. [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
WARNING: [Synth 8-3848] Net result_M in module/entity ALU does not have driver. [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
WARNING: [Synth 8-3848] Net result_N in module/entity ALU does not have driver. [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
WARNING: [Synth 8-3848] Net result_O in module/entity ALU does not have driver. [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
WARNING: [Synth 8-3848] Net result_P in module/entity ALU does not have driver. [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:11]
INFO: [Synth 8-6155] done synthesizing module 'ALU' (21#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
INFO: [Synth 8-6157] synthesizing module 'ControlUnit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3]
INFO: [Synth 8-6155] done synthesizing module 'ControlUnit' (22#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3]
INFO: [Synth 8-6157] synthesizing module 'bit1_mux_2_1' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:350]
INFO: [Synth 8-226] default block is never used [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:356]
INFO: [Synth 8-6155] done synthesizing module 'bit1_mux_2_1' (23#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:350]
INFO: [Synth 8-6155] done synthesizing module 'CPU9bits' (24#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3]
WARNING: [Synth 8-3331] design shift_right_arithmetic has unconnected port A[0]
WARNING: [Synth 8-3331] design shift_right_logical has unconnected port A[0]
WARNING: [Synth 8-3331] design shift_left has unconnected port A[8]
---------------------------------------------------------------------------------
Finished Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 420.887 ; gain = 158.258
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 420.887 ; gain = 158.258
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7k160tifbg484-2L
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 420.887 ; gain = 158.258
INFO: [Device 21-403] Loading part xc7k160tifbg484-2L
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 420.887 ; gain = 158.258
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
No constraint files found.
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 144
+---Registers :
9 Bit Registers := 5
+---Muxes :
4 Input 9 Bit Muxes := 2
2 Input 9 Bit Muxes := 5
2 Input 4 Bit Muxes := 1
4 Input 4 Bit Muxes := 1
2 Input 3 Bit Muxes := 2
13 Input 3 Bit Muxes := 1
13 Input 1 Bit Muxes := 4
2 Input 1 Bit Muxes := 1
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
Hierarchical RTL Component report
Module decoder
Detailed RTL Component Info :
+---Muxes :
2 Input 4 Bit Muxes := 1
4 Input 4 Bit Muxes := 1
Module register
Detailed RTL Component Info :
+---Registers :
9 Bit Registers := 1
Module mux_4_1
Detailed RTL Component Info :
+---Muxes :
4 Input 9 Bit Muxes := 1
Module add_1bit
Detailed RTL Component Info :
+---XORs :
2 Input 1 Bit XORs := 2
Module mux_2_1
Detailed RTL Component Info :
+---Muxes :
2 Input 9 Bit Muxes := 1
Module ControlUnit
Detailed RTL Component Info :
+---Muxes :
2 Input 3 Bit Muxes := 2
13 Input 3 Bit Muxes := 1
13 Input 1 Bit Muxes := 4
Module bit1_mux_2_1
Detailed RTL Component Info :
+---Muxes :
2 Input 1 Bit Muxes := 1
---------------------------------------------------------------------------------
Finished RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 600 (col length:100)
BRAMs: 650 (col length: RAMB18 100 RAMB36 50)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
No constraint files found.
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
Warning: Parallel synthesis criteria is not met
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 577.246 ; gain = 314.617
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
No constraint files found.
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 577.246 ; gain = 314.617
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 577.246 ; gain = 314.617
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 577.246 ; gain = 314.617
---------------------------------------------------------------------------------
Report Check Netlist:
+------+------------------+-------+---------+-------+------------------+
| |Item |Errors |Warnings |Status |Description |
+------+------------------+-------+---------+-------+------------------+
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 577.246 ; gain = 314.617
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 577.246 ; gain = 314.617
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 577.246 ; gain = 314.617
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 577.246 ; gain = 314.617
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 577.246 ; gain = 314.617
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+-----+------+
| |Cell |Count |
+------+-----+------+
|1 |LUT4 | 1|
|2 |IBUF | 4|
|3 |OBUF | 1|
+------+-----+------+
Report Instance Areas:
+------+---------+------------+------+
| |Instance |Module |Cells |
+------+---------+------------+------+
|1 |top | | 6|
|2 | CU |ControlUnit | 1|
+------+---------+------------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 577.246 ; gain = 314.617
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 8 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 577.246 ; gain = 314.617
Synthesis Optimization Complete : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 577.246 ; gain = 314.617
INFO: [Project 1-571] Translating synthesized netlist
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 681.730 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
INFO: [Common 17-83] Releasing license: Synthesis
60 Infos, 8 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 681.730 ; gain = 431.730
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 681.730 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint 'C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1/CPU9bits.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Wed Mar 13 12:45:16 2019...