Better Sim

lab2CA.srcs/sources_1/new/ALU.v

@@ -18,6 +18,7 @@ module ALU(
         .Cin(1'b0),
         .Sum(result_A),
         .Cout(cout));
+    
     // B (0001) - Subtract
     sub_9bit sub0(
         .A(operand0),

lab2CA.srcs/sources_1/new/BasicModules.v

@@ -782,7 +782,7 @@ module register(
                 
     always @(posedge clk) begin
         if (reset == 1'b1) begin
-            Dout = 9'b000000000;
+            Dout <= 9'b000000000;
         end
         else if (En == 1'b0) begin
             Dout = Din;

lab2CA.srcs/sources_1/new/CPU9bits.v

@@ -2,8 +2,7 @@
 
 module CPU9bits(input wire [8:0] instr,
         input wire reset, clk,
-        output wire done,
-        output wire [8:0] reg0
+        output wire done
     );
     
     wire [8:0] op1, op0, FUAddr,FUJB,PCout,JBRes,FUJ,FUB,AddiOut,AluOut,RFIn, loadMux, dataMemOut;
@@ -120,12 +119,11 @@ module CPU9bits_tb();
         .done(done));
         
     initial begin
+        instruction = 9'b000100000;
         reset = 1'b1;
         #10
         reset = 1'b0;
         #10
-        instruction = 9'b000100000;
-        #10
         instruction = 9'b000101000;
         #10
         instruction = 9'b010100010;

lab2CA.srcs/sources_1/new/FetchUnit.v

@@ -6,7 +6,7 @@ module FetchUnit(input wire clk, reset,
                  output wire [8:0] AddrOut);
   
     //Wires from mux(result_m) to PC (progC_out) to adder then back to mux (result_a) 
-    wire [8:0] progC_out, result_a, result_m;
+    wire [8:0] progC_out, result_m;
     wire cout;
     
     register PC(