Better Sim

2019-03-14 14:37:58 -04:00
parent 11a1d99e92
commit 08e3659ba3
50 changed files with 114 additions and 2909 deletions
--- a/lab2CA.srcs/sources_1/new/BasicModules.v
+++ b/lab2CA.srcs/sources_1/new/BasicModules.v
@@ -782,7 +782,7 @@ module register(
                
    always @(posedge clk) begin
        if (reset == 1'b1) begin
-            Dout = 9'b000000000;
+            Dout <= 9'b000000000;
        end
        else if (En == 1'b0) begin
            Dout = Din;