Better Sim

2019-03-14 14:37:58 -04:00
parent 11a1d99e92
commit 08e3659ba3
50 changed files with 114 additions and 2909 deletions
--- a/lab2CA.srcs/sources_1/new/CPU9bits.v
+++ b/lab2CA.srcs/sources_1/new/CPU9bits.v
@@ -2,8 +2,7 @@

 module CPU9bits(input wire [8:0] instr,
        input wire reset, clk,
-        output wire done,
-        output wire [8:0] reg0
+        output wire done
    );
    
    wire [8:0] op1, op0, FUAddr,FUJB,PCout,JBRes,FUJ,FUB,AddiOut,AluOut,RFIn, loadMux, dataMemOut;
@@ -120,12 +119,11 @@ module CPU9bits_tb();
        .done(done));
        
    initial begin
+        instruction = 9'b000100000;
        reset = 1'b1;
        #10
        reset = 1'b0;
        #10
-        instruction = 9'b000100000;
-        #10
        instruction = 9'b000101000;
        #10
        instruction = 9'b010100010;