Better Sim

2019-03-14 14:37:58 -04:00
parent 11a1d99e92
commit 08e3659ba3
50 changed files with 114 additions and 2909 deletions
--- a/lab2CA.srcs/sources_1/new/FetchUnit.v
+++ b/lab2CA.srcs/sources_1/new/FetchUnit.v
@@ -6,7 +6,7 @@ module FetchUnit(input wire clk, reset,
                 output wire [8:0] AddrOut);
  
    //Wires from mux(result_m) to PC (progC_out) to adder then back to mux (result_a) 
-    wire [8:0] progC_out, result_a, result_m;
+    wire [8:0] progC_out, result_m;
    wire cout;
    
    register PC(