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jose.rodriguezlabra
2019-02-15 12:38:07 -05:00
parent 7aa2cfff2a
commit 0b358a6c41
57 changed files with 3092 additions and 86 deletions
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lab2CA.runs/synth_1/RegFile.vds Normal file
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#-----------------------------------------------------------
# Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
# Start of session at: Fri Feb 15 12:29:57 2019
# Process ID: 16780
# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1
# Command line: vivado.exe -log RegFile.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source RegFile.tcl
# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1/RegFile.vds
# Journal file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1\vivado.jou
#-----------------------------------------------------------
source RegFile.tcl -notrace
Command: synth_design -top RegFile -part xc7k160tifbg484-2L
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160ti'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160ti'
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 1552
---------------------------------------------------------------------------------
Starting Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 364.203 ; gain = 101.098
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'RegFile' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/RegFile.v:23]
INFO: [Synth 8-6157] synthesizing module 'register' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:37]
INFO: [Synth 8-6155] done synthesizing module 'register' (1#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:37]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/RegFile.v:60]
INFO: [Synth 8-6157] synthesizing module 'mux' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:57]
INFO: [Synth 8-6155] done synthesizing module 'mux' (2#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:57]
WARNING: [Synth 8-350] instance 'm0' of module 'mux' requires 6 connections, but only 5 given [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/RegFile.v:60]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/RegFile.v:67]
WARNING: [Synth 8-350] instance 'm1' of module 'mux' requires 6 connections, but only 5 given [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/RegFile.v:67]
WARNING: [Synth 8-3848] Net op0 in module/entity RegFile does not have driver. [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/RegFile.v:26]
WARNING: [Synth 8-3848] Net op1 in module/entity RegFile does not have driver. [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/RegFile.v:26]
INFO: [Synth 8-6155] done synthesizing module 'RegFile' (3#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/RegFile.v:23]
WARNING: [Synth 8-3331] design RegFile has unconnected port op0[8]
WARNING: [Synth 8-3331] design RegFile has unconnected port op0[7]
WARNING: [Synth 8-3331] design RegFile has unconnected port op0[6]
WARNING: [Synth 8-3331] design RegFile has unconnected port op0[5]
WARNING: [Synth 8-3331] design RegFile has unconnected port op0[4]
WARNING: [Synth 8-3331] design RegFile has unconnected port op0[3]
WARNING: [Synth 8-3331] design RegFile has unconnected port op0[2]
WARNING: [Synth 8-3331] design RegFile has unconnected port op0[1]
WARNING: [Synth 8-3331] design RegFile has unconnected port op0[0]
WARNING: [Synth 8-3331] design RegFile has unconnected port op1[8]
WARNING: [Synth 8-3331] design RegFile has unconnected port op1[7]
WARNING: [Synth 8-3331] design RegFile has unconnected port op1[6]
WARNING: [Synth 8-3331] design RegFile has unconnected port op1[5]
WARNING: [Synth 8-3331] design RegFile has unconnected port op1[4]
WARNING: [Synth 8-3331] design RegFile has unconnected port op1[3]
WARNING: [Synth 8-3331] design RegFile has unconnected port op1[2]
WARNING: [Synth 8-3331] design RegFile has unconnected port op1[1]
WARNING: [Synth 8-3331] design RegFile has unconnected port op1[0]
---------------------------------------------------------------------------------
Finished Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 420.734 ; gain = 157.629
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 420.734 ; gain = 157.629
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7k160tifbg484-2L
INFO: [Device 21-403] Loading part xc7k160tifbg484-2L
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 420.734 ; gain = 157.629
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 420.734 ; gain = 157.629
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
No constraint files found.
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Registers :
9 Bit Registers := 4
+---Muxes :
2 Input 9 Bit Muxes := 4
5 Input 9 Bit Muxes := 2
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
Hierarchical RTL Component report
Module register
Detailed RTL Component Info :
+---Registers :
9 Bit Registers := 1
+---Muxes :
2 Input 9 Bit Muxes := 1
Module mux
Detailed RTL Component Info :
+---Muxes :
5 Input 9 Bit Muxes := 1
---------------------------------------------------------------------------------
Finished RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 600 (col length:100)
BRAMs: 650 (col length: RAMB18 100 RAMB36 50)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
No constraint files found.
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
Warning: Parallel synthesis criteria is not met
WARNING: [Synth 8-3330] design RegFile has an empty top module
WARNING: [Synth 8-3331] design RegFile has unconnected port op0[8]
WARNING: [Synth 8-3331] design RegFile has unconnected port op0[7]
WARNING: [Synth 8-3331] design RegFile has unconnected port op0[6]
WARNING: [Synth 8-3331] design RegFile has unconnected port op0[5]
WARNING: [Synth 8-3331] design RegFile has unconnected port op0[4]
WARNING: [Synth 8-3331] design RegFile has unconnected port op0[3]
WARNING: [Synth 8-3331] design RegFile has unconnected port op0[2]
WARNING: [Synth 8-3331] design RegFile has unconnected port op0[1]
WARNING: [Synth 8-3331] design RegFile has unconnected port op0[0]
WARNING: [Synth 8-3331] design RegFile has unconnected port op1[8]
WARNING: [Synth 8-3331] design RegFile has unconnected port op1[7]
WARNING: [Synth 8-3331] design RegFile has unconnected port op1[6]
WARNING: [Synth 8-3331] design RegFile has unconnected port op1[5]
WARNING: [Synth 8-3331] design RegFile has unconnected port op1[4]
WARNING: [Synth 8-3331] design RegFile has unconnected port op1[3]
WARNING: [Synth 8-3331] design RegFile has unconnected port op1[2]
WARNING: [Synth 8-3331] design RegFile has unconnected port op1[1]
WARNING: [Synth 8-3331] design RegFile has unconnected port op1[0]
WARNING: [Synth 8-3331] design RegFile has unconnected port clk
WARNING: [Synth 8-3331] design RegFile has unconnected port reset
WARNING: [Synth 8-3331] design RegFile has unconnected port write_index[1]
WARNING: [Synth 8-3331] design RegFile has unconnected port write_index[0]
WARNING: [Synth 8-3331] design RegFile has unconnected port op0_idx[1]
WARNING: [Synth 8-3331] design RegFile has unconnected port op0_idx[0]
WARNING: [Synth 8-3331] design RegFile has unconnected port op1_idx[1]
WARNING: [Synth 8-3331] design RegFile has unconnected port op1_idx[0]
WARNING: [Synth 8-3331] design RegFile has unconnected port write_data[8]
WARNING: [Synth 8-3331] design RegFile has unconnected port write_data[7]
WARNING: [Synth 8-3331] design RegFile has unconnected port write_data[6]
WARNING: [Synth 8-3331] design RegFile has unconnected port write_data[5]
WARNING: [Synth 8-3331] design RegFile has unconnected port write_data[4]
WARNING: [Synth 8-3331] design RegFile has unconnected port write_data[3]
WARNING: [Synth 8-3331] design RegFile has unconnected port write_data[2]
WARNING: [Synth 8-3331] design RegFile has unconnected port write_data[1]
WARNING: [Synth 8-3331] design RegFile has unconnected port write_data[0]
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 558.852 ; gain = 295.746
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
No constraint files found.
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 558.852 ; gain = 295.746
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 567.527 ; gain = 304.422
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 567.527 ; gain = 304.422
---------------------------------------------------------------------------------
Report Check Netlist:
+------+------------------+-------+---------+-------+------------------+
| |Item |Errors |Warnings |Status |Description |
+------+------------------+-------+---------+-------+------------------+
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 567.527 ; gain = 304.422
---------------------------------------------------------------------------------
Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 567.527 ; gain = 304.422
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 567.527 ; gain = 304.422
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 567.527 ; gain = 304.422
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 567.527 ; gain = 304.422
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+------+------+
| |Cell |Count |
+------+------+------+
|1 |OBUFT | 18|
+------+------+------+
Report Instance Areas:
+------+---------+-------+------+
| |Instance |Module |Cells |
+------+---------+-------+------+
|1 |top | | 18|
+------+---------+-------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 567.527 ; gain = 304.422
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 60 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 567.527 ; gain = 304.422
Synthesis Optimization Complete : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 567.527 ; gain = 304.422
INFO: [Project 1-571] Translating synthesized netlist
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 674.148 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
INFO: [Common 17-83] Releasing license: Synthesis
13 Infos, 60 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 674.148 ; gain = 424.316
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 674.148 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint 'C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1/RegFile.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file RegFile_utilization_synth.rpt -pb RegFile_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Fri Feb 15 12:30:22 2019...