Set some comments

lab2CA.srcs/sources_1/new/BasicModules.v

@@ -24,19 +24,16 @@ module BasicModules();
 endmodule
 
 module gen_clock();
-
     reg clk;
-    
     initial begin
         clk = 1'b0;
     end
-    
     always begin
         #5 clk = ~clk; // Period to be determined
     end
-
 endmodule
 
+//To enable register, input 00 to En, register is always outputting contents
 module register(input wire clk, reset,
                 input wire [1:0] En,
                 input wire [8:0] Din,
@@ -56,6 +53,7 @@ module register(input wire clk, reset,
 
 endmodule
 
+//Mux follows intuitive switching
 module mux(input wire [1:0] switch,
            input wire [8:0] A,B,C,D,
            output reg [8:0] out);
@@ -67,12 +65,15 @@ module mux(input wire [1:0] switch,
         else if (switch == 2'b01) begin
             out = B;
         end
-        else if (switch == 2'b11) begin
+        else if (switch == 2'b10) begin
             out = C;
         end
-        else begin
+        else if (switch == 2'b11) begin
             out = D;
         end
+        else begin
+            out = "ZZZZZZZZZ";
+        end
     end
 
 endmodule