Erased weird numbers
This commit is contained in:
jose.rodriguezlabra
@@ -30,7 +30,7 @@ set_property ip_output_repo {c:/Users/JoseIgnacio/CA Lab/lab2CA.cache/ip} [curre
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set_property ip_cache_permissions {read write} [current_project]
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read_verilog -library xil_defaultlib {
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{C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v}
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{C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/RegFile.v}
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{C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v}
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}
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# Mark all dcp files as not used in implementation to prevent them from being
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# stitched into the results of this synthesis run. Any black boxes in the
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@@ -43,12 +43,12 @@ foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
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set_param ips.enableIPCacheLiteLoad 1
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close [open __synthesis_is_running__ w]
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synth_design -top RegFile -part xc7k160tifbg484-2L
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synth_design -top ALU -part xc7k160tifbg484-2L
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# disable binary constraint mode for synth run checkpoints
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set_param constraints.enableBinaryConstraints false
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write_checkpoint -force -noxdef RegFile.dcp
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create_report "synth_1_synth_report_utilization_0" "report_utilization -file RegFile_utilization_synth.rpt -pb RegFile_utilization_synth.pb"
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write_checkpoint -force -noxdef ALU.dcp
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create_report "synth_1_synth_report_utilization_0" "report_utilization -file ALU_utilization_synth.rpt -pb ALU_utilization_synth.pb"
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file delete __synthesis_is_running__
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close [open __synthesis_is_complete__ w]
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49
lab2CA.runs/synth_1/ALU.vds
Normal file
49
lab2CA.runs/synth_1/ALU.vds
Normal file
@@ -0,0 +1,49 @@
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#-----------------------------------------------------------
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# Vivado v2018.3 (64-bit)
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# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
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# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
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# Start of session at: Sat Feb 16 12:49:31 2019
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# Process ID: 18228
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# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1
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# Command line: vivado.exe -log ALU.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source ALU.tcl
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# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1/ALU.vds
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# Journal file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1\vivado.jou
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#-----------------------------------------------------------
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source ALU.tcl -notrace
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Command: synth_design -top ALU -part xc7k160tifbg484-2L
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Starting synth_design
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Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160ti'
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INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160ti'
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INFO: Launching helper process for spawning children vivado processes
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INFO: Helper process launched with PID 8848
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---------------------------------------------------------------------------------
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Starting Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 363.309 ; gain = 101.105
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---------------------------------------------------------------------------------
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INFO: [Synth 8-6157] synthesizing module 'ALU' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
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INFO: [Synth 8-6157] synthesizing module 'add_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:15]
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INFO: [Synth 8-6157] synthesizing module 'add_1bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'add_1bit' (1#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'add_9bit' (2#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:15]
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WARNING: [Synth 8-350] instance 'add0' of module 'add_9bit' requires 5 connections, but only 4 given [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:14]
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INFO: [Synth 8-6157] synthesizing module 'sub_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:483]
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WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:490]
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INFO: [Synth 8-6157] synthesizing module 'twos_compliment_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:502]
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INFO: [Synth 8-6157] synthesizing module 'not_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:319]
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INFO: [Synth 8-6157] synthesizing module 'not_1bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:311]
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INFO: [Synth 8-6155] done synthesizing module 'not_1bit' (3#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:311]
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INFO: [Synth 8-6155] done synthesizing module 'not_9bit' (4#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:319]
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WARNING: [Synth 8-350] instance 'add0' of module 'add_9bit' requires 5 connections, but only 4 given [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:512]
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INFO: [Synth 8-6155] done synthesizing module 'twos_compliment_9bit' (5#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:502]
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ERROR: [Synth 8-448] named port connection 'C' does not exist for instance 'two_comp0' of module 'twos_compliment_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:492]
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WARNING: [Synth 8-350] instance 'add0' of module 'add_9bit' requires 5 connections, but only 4 given [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:494]
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ERROR: [Synth 8-6156] failed synthesizing module 'sub_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:483]
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ERROR: [Synth 8-6156] failed synthesizing module 'ALU' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:3]
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---------------------------------------------------------------------------------
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Finished Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 419.434 ; gain = 157.230
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---------------------------------------------------------------------------------
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synthesize failed
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INFO: [Common 17-83] Releasing license: Synthesis
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14 Infos, 4 Warnings, 0 Critical Warnings and 4 Errors encountered.
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synth_design failed
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ERROR: [Common 17-69] Command failed: Vivado Synthesis failed
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INFO: [Common 17-206] Exiting Vivado at Sat Feb 16 12:49:41 2019...
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Binary file not shown.
@@ -1,295 +0,0 @@
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#-----------------------------------------------------------
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# Vivado v2018.3 (64-bit)
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# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
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# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
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# Start of session at: Fri Feb 15 12:29:57 2019
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# Process ID: 16780
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# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1
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# Command line: vivado.exe -log RegFile.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source RegFile.tcl
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# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1/RegFile.vds
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# Journal file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1\vivado.jou
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#-----------------------------------------------------------
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source RegFile.tcl -notrace
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Command: synth_design -top RegFile -part xc7k160tifbg484-2L
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Starting synth_design
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Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160ti'
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INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160ti'
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INFO: Launching helper process for spawning children vivado processes
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INFO: Helper process launched with PID 1552
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---------------------------------------------------------------------------------
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Starting Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 364.203 ; gain = 101.098
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---------------------------------------------------------------------------------
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INFO: [Synth 8-6157] synthesizing module 'RegFile' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/RegFile.v:23]
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INFO: [Synth 8-6157] synthesizing module 'register' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:37]
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INFO: [Synth 8-6155] done synthesizing module 'register' (1#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:37]
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WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/RegFile.v:60]
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INFO: [Synth 8-6157] synthesizing module 'mux' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:57]
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INFO: [Synth 8-6155] done synthesizing module 'mux' (2#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:57]
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WARNING: [Synth 8-350] instance 'm0' of module 'mux' requires 6 connections, but only 5 given [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/RegFile.v:60]
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WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/RegFile.v:67]
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WARNING: [Synth 8-350] instance 'm1' of module 'mux' requires 6 connections, but only 5 given [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/RegFile.v:67]
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WARNING: [Synth 8-3848] Net op0 in module/entity RegFile does not have driver. [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/RegFile.v:26]
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WARNING: [Synth 8-3848] Net op1 in module/entity RegFile does not have driver. [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/RegFile.v:26]
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INFO: [Synth 8-6155] done synthesizing module 'RegFile' (3#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/RegFile.v:23]
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WARNING: [Synth 8-3331] design RegFile has unconnected port op0[8]
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WARNING: [Synth 8-3331] design RegFile has unconnected port op0[7]
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WARNING: [Synth 8-3331] design RegFile has unconnected port op0[6]
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WARNING: [Synth 8-3331] design RegFile has unconnected port op0[5]
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WARNING: [Synth 8-3331] design RegFile has unconnected port op0[4]
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WARNING: [Synth 8-3331] design RegFile has unconnected port op0[3]
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WARNING: [Synth 8-3331] design RegFile has unconnected port op0[2]
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WARNING: [Synth 8-3331] design RegFile has unconnected port op0[1]
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WARNING: [Synth 8-3331] design RegFile has unconnected port op0[0]
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WARNING: [Synth 8-3331] design RegFile has unconnected port op1[8]
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WARNING: [Synth 8-3331] design RegFile has unconnected port op1[7]
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WARNING: [Synth 8-3331] design RegFile has unconnected port op1[6]
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WARNING: [Synth 8-3331] design RegFile has unconnected port op1[5]
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WARNING: [Synth 8-3331] design RegFile has unconnected port op1[4]
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WARNING: [Synth 8-3331] design RegFile has unconnected port op1[3]
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WARNING: [Synth 8-3331] design RegFile has unconnected port op1[2]
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WARNING: [Synth 8-3331] design RegFile has unconnected port op1[1]
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WARNING: [Synth 8-3331] design RegFile has unconnected port op1[0]
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---------------------------------------------------------------------------------
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Finished Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 420.734 ; gain = 157.629
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Constraint Validation : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 420.734 ; gain = 157.629
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Loading Part and Timing Information
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---------------------------------------------------------------------------------
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Loading part: xc7k160tifbg484-2L
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INFO: [Device 21-403] Loading part xc7k160tifbg484-2L
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---------------------------------------------------------------------------------
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Finished Loading Part and Timing Information : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 420.734 ; gain = 157.629
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 420.734 ; gain = 157.629
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---------------------------------------------------------------------------------
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Report RTL Partitions:
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+-+--------------+------------+----------+
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| |RTL Partition |Replication |Instances |
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+-+--------------+------------+----------+
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+-+--------------+------------+----------+
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No constraint files found.
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---------------------------------------------------------------------------------
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Start RTL Component Statistics
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---------------------------------------------------------------------------------
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Detailed RTL Component Info :
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+---Registers :
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9 Bit Registers := 4
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+---Muxes :
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2 Input 9 Bit Muxes := 4
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5 Input 9 Bit Muxes := 2
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---------------------------------------------------------------------------------
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Finished RTL Component Statistics
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start RTL Hierarchical Component Statistics
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---------------------------------------------------------------------------------
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Hierarchical RTL Component report
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Module register
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Detailed RTL Component Info :
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+---Registers :
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9 Bit Registers := 1
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+---Muxes :
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2 Input 9 Bit Muxes := 1
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Module mux
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Detailed RTL Component Info :
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+---Muxes :
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5 Input 9 Bit Muxes := 1
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---------------------------------------------------------------------------------
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Finished RTL Hierarchical Component Statistics
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Part Resource Summary
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---------------------------------------------------------------------------------
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Part Resources:
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DSPs: 600 (col length:100)
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BRAMs: 650 (col length: RAMB18 100 RAMB36 50)
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---------------------------------------------------------------------------------
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Finished Part Resource Summary
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---------------------------------------------------------------------------------
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No constraint files found.
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---------------------------------------------------------------------------------
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Start Cross Boundary and Area Optimization
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---------------------------------------------------------------------------------
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Warning: Parallel synthesis criteria is not met
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WARNING: [Synth 8-3330] design RegFile has an empty top module
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WARNING: [Synth 8-3331] design RegFile has unconnected port op0[8]
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WARNING: [Synth 8-3331] design RegFile has unconnected port op0[7]
|
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WARNING: [Synth 8-3331] design RegFile has unconnected port op0[6]
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WARNING: [Synth 8-3331] design RegFile has unconnected port op0[5]
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WARNING: [Synth 8-3331] design RegFile has unconnected port op0[4]
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||||
WARNING: [Synth 8-3331] design RegFile has unconnected port op0[3]
|
||||
WARNING: [Synth 8-3331] design RegFile has unconnected port op0[2]
|
||||
WARNING: [Synth 8-3331] design RegFile has unconnected port op0[1]
|
||||
WARNING: [Synth 8-3331] design RegFile has unconnected port op0[0]
|
||||
WARNING: [Synth 8-3331] design RegFile has unconnected port op1[8]
|
||||
WARNING: [Synth 8-3331] design RegFile has unconnected port op1[7]
|
||||
WARNING: [Synth 8-3331] design RegFile has unconnected port op1[6]
|
||||
WARNING: [Synth 8-3331] design RegFile has unconnected port op1[5]
|
||||
WARNING: [Synth 8-3331] design RegFile has unconnected port op1[4]
|
||||
WARNING: [Synth 8-3331] design RegFile has unconnected port op1[3]
|
||||
WARNING: [Synth 8-3331] design RegFile has unconnected port op1[2]
|
||||
WARNING: [Synth 8-3331] design RegFile has unconnected port op1[1]
|
||||
WARNING: [Synth 8-3331] design RegFile has unconnected port op1[0]
|
||||
WARNING: [Synth 8-3331] design RegFile has unconnected port clk
|
||||
WARNING: [Synth 8-3331] design RegFile has unconnected port reset
|
||||
WARNING: [Synth 8-3331] design RegFile has unconnected port write_index[1]
|
||||
WARNING: [Synth 8-3331] design RegFile has unconnected port write_index[0]
|
||||
WARNING: [Synth 8-3331] design RegFile has unconnected port op0_idx[1]
|
||||
WARNING: [Synth 8-3331] design RegFile has unconnected port op0_idx[0]
|
||||
WARNING: [Synth 8-3331] design RegFile has unconnected port op1_idx[1]
|
||||
WARNING: [Synth 8-3331] design RegFile has unconnected port op1_idx[0]
|
||||
WARNING: [Synth 8-3331] design RegFile has unconnected port write_data[8]
|
||||
WARNING: [Synth 8-3331] design RegFile has unconnected port write_data[7]
|
||||
WARNING: [Synth 8-3331] design RegFile has unconnected port write_data[6]
|
||||
WARNING: [Synth 8-3331] design RegFile has unconnected port write_data[5]
|
||||
WARNING: [Synth 8-3331] design RegFile has unconnected port write_data[4]
|
||||
WARNING: [Synth 8-3331] design RegFile has unconnected port write_data[3]
|
||||
WARNING: [Synth 8-3331] design RegFile has unconnected port write_data[2]
|
||||
WARNING: [Synth 8-3331] design RegFile has unconnected port write_data[1]
|
||||
WARNING: [Synth 8-3331] design RegFile has unconnected port write_data[0]
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 558.852 ; gain = 295.746
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
No constraint files found.
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 558.852 ; gain = 295.746
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 567.527 ; gain = 304.422
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 567.527 ; gain = 304.422
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 567.527 ; gain = 304.422
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 567.527 ; gain = 304.422
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 567.527 ; gain = 304.422
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 567.527 ; gain = 304.422
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 567.527 ; gain = 304.422
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report BlackBoxes:
|
||||
+-+--------------+----------+
|
||||
| |BlackBox name |Instances |
|
||||
+-+--------------+----------+
|
||||
+-+--------------+----------+
|
||||
|
||||
Report Cell Usage:
|
||||
+------+------+------+
|
||||
| |Cell |Count |
|
||||
+------+------+------+
|
||||
|1 |OBUFT | 18|
|
||||
+------+------+------+
|
||||
|
||||
Report Instance Areas:
|
||||
+------+---------+-------+------+
|
||||
| |Instance |Module |Cells |
|
||||
+------+---------+-------+------+
|
||||
|1 |top | | 18|
|
||||
+------+---------+-------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 567.527 ; gain = 304.422
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 60 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 567.527 ; gain = 304.422
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 567.527 ; gain = 304.422
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 674.148 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
13 Infos, 60 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 674.148 ; gain = 424.316
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 674.148 ; gain = 0.000
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint 'C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1/RegFile.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file RegFile_utilization_synth.rpt -pb RegFile_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Fri Feb 15 12:30:22 2019...
|
||||
Binary file not shown.
@@ -1,173 +0,0 @@
|
||||
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
|
||||
| Date : Fri Feb 15 12:30:22 2019
|
||||
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
|
||||
| Command : report_utilization -file RegFile_utilization_synth.rpt -pb RegFile_utilization_synth.pb
|
||||
| Design : RegFile
|
||||
| Device : 7k160tifbg484-2L
|
||||
| Design State : Synthesized
|
||||
---------------------------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Slice Logic
|
||||
1.1 Summary of Registers by Type
|
||||
2. Memory
|
||||
3. DSP
|
||||
4. IO and GT Specific
|
||||
5. Clocking
|
||||
6. Specific Feature
|
||||
7. Primitives
|
||||
8. Black Boxes
|
||||
9. Instantiated Netlists
|
||||
|
||||
1. Slice Logic
|
||||
--------------
|
||||
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Slice LUTs* | 0 | 0 | 101400 | 0.00 |
|
||||
| LUT as Logic | 0 | 0 | 101400 | 0.00 |
|
||||
| LUT as Memory | 0 | 0 | 35000 | 0.00 |
|
||||
| Slice Registers | 0 | 0 | 202800 | 0.00 |
|
||||
| Register as Flip Flop | 0 | 0 | 202800 | 0.00 |
|
||||
| Register as Latch | 0 | 0 | 202800 | 0.00 |
|
||||
| F7 Muxes | 0 | 0 | 50700 | 0.00 |
|
||||
| F8 Muxes | 0 | 0 | 25350 | 0.00 |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
|
||||
|
||||
|
||||
1.1 Summary of Registers by Type
|
||||
--------------------------------
|
||||
|
||||
+-------+--------------+-------------+--------------+
|
||||
| Total | Clock Enable | Synchronous | Asynchronous |
|
||||
+-------+--------------+-------------+--------------+
|
||||
| 0 | _ | - | - |
|
||||
| 0 | _ | - | Set |
|
||||
| 0 | _ | - | Reset |
|
||||
| 0 | _ | Set | - |
|
||||
| 0 | _ | Reset | - |
|
||||
| 0 | Yes | - | - |
|
||||
| 0 | Yes | - | Set |
|
||||
| 0 | Yes | - | Reset |
|
||||
| 0 | Yes | Set | - |
|
||||
| 0 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
2. Memory
|
||||
---------
|
||||
|
||||
+----------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
| Block RAM Tile | 0 | 0 | 325 | 0.00 |
|
||||
| RAMB36/FIFO* | 0 | 0 | 325 | 0.00 |
|
||||
| RAMB18 | 0 | 0 | 650 | 0.00 |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
|
||||
|
||||
|
||||
3. DSP
|
||||
------
|
||||
|
||||
+-----------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------+------+-------+-----------+-------+
|
||||
| DSPs | 0 | 0 | 600 | 0.00 |
|
||||
+-----------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
4. IO and GT Specific
|
||||
---------------------
|
||||
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Bonded IOB | 18 | 0 | 285 | 6.32 |
|
||||
| Bonded IPADs | 0 | 0 | 14 | 0.00 |
|
||||
| Bonded OPADs | 0 | 0 | 8 | 0.00 |
|
||||
| PHY_CONTROL | 0 | 0 | 8 | 0.00 |
|
||||
| PHASER_REF | 0 | 0 | 8 | 0.00 |
|
||||
| OUT_FIFO | 0 | 0 | 32 | 0.00 |
|
||||
| IN_FIFO | 0 | 0 | 32 | 0.00 |
|
||||
| IDELAYCTRL | 0 | 0 | 8 | 0.00 |
|
||||
| IBUFDS | 0 | 0 | 275 | 0.00 |
|
||||
| GTXE2_COMMON | 0 | 0 | 1 | 0.00 |
|
||||
| GTXE2_CHANNEL | 0 | 0 | 4 | 0.00 |
|
||||
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 32 | 0.00 |
|
||||
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 32 | 0.00 |
|
||||
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 400 | 0.00 |
|
||||
| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 |
|
||||
| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 |
|
||||
| ILOGIC | 0 | 0 | 285 | 0.00 |
|
||||
| OLOGIC | 0 | 0 | 285 | 0.00 |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
5. Clocking
|
||||
-----------
|
||||
|
||||
+------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+------------+------+-------+-----------+-------+
|
||||
| BUFGCTRL | 0 | 0 | 32 | 0.00 |
|
||||
| BUFIO | 0 | 0 | 32 | 0.00 |
|
||||
| MMCME2_ADV | 0 | 0 | 8 | 0.00 |
|
||||
| PLLE2_ADV | 0 | 0 | 8 | 0.00 |
|
||||
| BUFMRCE | 0 | 0 | 16 | 0.00 |
|
||||
| BUFHCE | 0 | 0 | 120 | 0.00 |
|
||||
| BUFR | 0 | 0 | 32 | 0.00 |
|
||||
+------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
6. Specific Feature
|
||||
-------------------
|
||||
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| BSCANE2 | 0 | 0 | 4 | 0.00 |
|
||||
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
|
||||
| DNA_PORT | 0 | 0 | 1 | 0.00 |
|
||||
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
|
||||
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
|
||||
| ICAPE2 | 0 | 0 | 2 | 0.00 |
|
||||
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
|
||||
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
|
||||
| XADC | 0 | 0 | 1 | 0.00 |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
7. Primitives
|
||||
-------------
|
||||
|
||||
+----------+------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+----------+------+---------------------+
|
||||
| OBUFT | 18 | IO |
|
||||
+----------+------+---------------------+
|
||||
|
||||
|
||||
8. Black Boxes
|
||||
--------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
9. Instantiated Netlists
|
||||
------------------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
@@ -1,14 +1,14 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="synth_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1550251794">
|
||||
<File Type="PA-TCL" Name="RegFile.tcl"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="RegFile_drc_synth.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="RegFile_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="RegFile.vds"/>
|
||||
<File Type="RDS-UTIL" Name="RegFile_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="RegFile_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="RegFile.dcp"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="RegFile_timing_summary_synth.rpt"/>
|
||||
<File Type="VDS-TIMING-PB" Name="RegFile_timing_summary_synth.pb"/>
|
||||
<GenRun Id="synth_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1550339368">
|
||||
<File Type="PA-TCL" Name="ALU.tcl"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="ALU_drc_synth.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="ALU_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="ALU.vds"/>
|
||||
<File Type="RDS-UTIL" Name="ALU_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="ALU_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="ALU.dcp"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="ALU_timing_summary_synth.rpt"/>
|
||||
<File Type="VDS-TIMING-PB" Name="ALU_timing_summary_synth.pb"/>
|
||||
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/new/BasicModules.v">
|
||||
@@ -18,8 +18,16 @@
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/ALU.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/RegFile.v">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
@@ -35,8 +43,7 @@
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="RegFile"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TopModule" Val="ALU"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
|
||||
@@ -6,4 +6,4 @@ REM to be invoked for Vivado to track run status.
|
||||
REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
|
||||
REM
|
||||
|
||||
vivado -log RegFile.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source RegFile.tcl
|
||||
vivado -log ALU.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source ALU.tcl
|
||||
|
||||
@@ -2,11 +2,11 @@
|
||||
# Vivado v2018.3 (64-bit)
|
||||
# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018
|
||||
# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018
|
||||
# Start of session at: Fri Feb 15 12:29:57 2019
|
||||
# Process ID: 16780
|
||||
# Start of session at: Sat Feb 16 12:49:31 2019
|
||||
# Process ID: 18228
|
||||
# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1
|
||||
# Command line: vivado.exe -log RegFile.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source RegFile.tcl
|
||||
# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1/RegFile.vds
|
||||
# Command line: vivado.exe -log ALU.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source ALU.tcl
|
||||
# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1/ALU.vds
|
||||
# Journal file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source RegFile.tcl -notrace
|
||||
source ALU.tcl -notrace
|
||||
|
||||
Binary file not shown.
Reference in New Issue
Block a user