William/WMU-ECE-3570-Lab
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Erased weird numbers

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This commit is contained in:
jose.rodriguezlabra
2019-02-16 12:50:02 -05:00
parent d60aa9d1e8
commit 0d9cc2b890
52 changed files with 157 additions and 2661 deletions
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31
lab2CA.runs/synth_1/gen_run.xml
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@@ -1,14 +1,14 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="synth_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1550251794">
<File Type="PA-TCL" Name="RegFile.tcl"/>
<File Type="RDS-PROPCONSTRS" Name="RegFile_drc_synth.rpt"/>
<File Type="REPORTS-TCL" Name="RegFile_reports.tcl"/>
<File Type="RDS-RDS" Name="RegFile.vds"/>
<File Type="RDS-UTIL" Name="RegFile_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="RegFile_utilization_synth.pb"/>
<File Type="RDS-DCP" Name="RegFile.dcp"/>
<File Type="VDS-TIMINGSUMMARY" Name="RegFile_timing_summary_synth.rpt"/>
<File Type="VDS-TIMING-PB" Name="RegFile_timing_summary_synth.pb"/>
<GenRun Id="synth_1" LaunchPart="xc7k160tifbg484-2L" LaunchTime="1550339368">
<File Type="PA-TCL" Name="ALU.tcl"/>
<File Type="RDS-PROPCONSTRS" Name="ALU_drc_synth.rpt"/>
<File Type="REPORTS-TCL" Name="ALU_reports.tcl"/>
<File Type="RDS-RDS" Name="ALU.vds"/>
<File Type="RDS-UTIL" Name="ALU_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="ALU_utilization_synth.pb"/>
<File Type="RDS-DCP" Name="ALU.dcp"/>
<File Type="VDS-TIMINGSUMMARY" Name="ALU_timing_summary_synth.rpt"/>
<File Type="VDS-TIMING-PB" Name="ALU_timing_summary_synth.pb"/>
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/new/BasicModules.v">
@@ -18,8 +18,16 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/ALU.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/RegFile.v">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
@@ -35,8 +43,7 @@
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="RegFile"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TopModule" Val="ALU"/>
</Config>
</FileSet>
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">