Erased weird numbers

lab2CA.srcs/sources_1/new/BasicModules.v

@@ -164,11 +164,9 @@ module gen_clock();
     end
 endmodule
 
-<<<<<<< HEAD
-<<<<<<< HEAD
+
 //To enable register, input 00 to En, register is always outputting contents
-=======
-=======
+
 module mux_2_1(input wire switch,
            input wire [8:0] A,B,
            output reg [8:0] out);
@@ -183,7 +181,6 @@ module mux_2_1(input wire switch,
 
 endmodule
 
->>>>>>> b2eb0da26cf8a205e02981e2a7c6a774e8d18e02
 module mux_4_1(input wire [1:0] switch,
            input wire [8:0] A,B,C,D,
            output reg [8:0] out);
@@ -422,7 +419,6 @@ module or_9bit(
 
 endmodule
 
->>>>>>> 5458d273919a21255992a22a8e59ccb89544f780
 module register(input wire clk, reset,
                 input wire [1:0] En,
                 input wire [8:0] Din,
@@ -442,7 +438,6 @@ module register(input wire clk, reset,
 
 endmodule
 
-<<<<<<< HEAD
 //Mux follows intuitive switching
 module mux(input wire [1:0] switch,
            input wire [8:0] A,B,C,D,
@@ -465,13 +460,13 @@ module mux(input wire [1:0] switch,
             out = "ZZZZZZZZZ";
         end
     end
-=======
+endmodule    
+    
 module shift_logical_left(
     input wire [8:0] A,
     output wire [8:0] B);
     
     assign B = {A[7:0],A[8]};
->>>>>>> 5458d273919a21255992a22a8e59ccb89544f780
 
 endmodule
 
@@ -483,6 +478,8 @@ module shift_logical_right(
 
 endmodule
 
+
+// No D instance, fix
 module sub_9bit(
     input wire [8:0] A,
     input wire [8:0] B,

lab2CA.srcs/sources_1/new/FetchUnit.v

@@ -1,6 +1,5 @@
 `timescale 1ns / 1ps
 
-
 module FetchUnit(input wire clk, reset, op_idx,
                  input wire [1:0] write_index,
                  input wire [8:0] AddrIn,