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Computer works (kinda)

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jose.rodriguezlabra
2019-03-13 12:51:44 -04:00
parent 026eb65861
commit 11a1d99e92
64 changed files with 809 additions and 422 deletions
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lab2CA.runs/impl_1/CPU9bits_power_routed.rpt
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@@ -1,7 +1,7 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
| Date : Wed Mar 13 11:13:48 2019
| Date : Wed Mar 13 12:46:34 2019
| Host : DESKTOP-CSFKQTV running 64-bit major release (build 9200)
| Command : report_power -file CPU9bits_power_routed.rpt -pb CPU9bits_power_summary_routed.pb -rpx CPU9bits_power_routed.rpx
| Design : CPU9bits
@@ -30,15 +30,15 @@ Table of Contents
----------
+--------------------------+--------------+
| Total On-Chip Power (W) | 0.084 |
| Total On-Chip Power (W) | 0.476 |
| Design Power Budget (W) | Unspecified* |
| Power Budget Margin (W) | NA |
| Dynamic (W) | 0.000 |
| Device Static (W) | 0.084 |
| Dynamic (W) | 0.389 |
| Device Static (W) | 0.087 |
| Effective TJA (C/W) | 2.5 |
| Max Ambient (C) | 99.8 |
| Junction Temperature (C) | 25.2 |
| Confidence Level | High |
| Max Ambient (C) | 98.8 |
| Junction Temperature (C) | 26.2 |
| Confidence Level | Low |
| Setting File | --- |
| Simulation Activity File | --- |
| Design Nets Matched | NA |
@@ -49,15 +49,16 @@ Table of Contents
1.1 On-Chip Components
----------------------
+--------------+-----------+----------+-----------+-----------------+
| On-Chip | Power (W) | Used | Available | Utilization (%) |
+--------------+-----------+----------+-----------+-----------------+
| Slice Logic | 0.000 | 1 | --- | --- |
| Others | 0.000 | 1 | --- | --- |
| I/O | 0.000 | 1 | 285 | 0.35 |
| Static Power | 0.084 | | | |
| Total | 0.084 | | | |
+--------------+-----------+----------+-----------+-----------------+
+----------------+-----------+----------+-----------+-----------------+
| On-Chip | Power (W) | Used | Available | Utilization (%) |
+----------------+-----------+----------+-----------+-----------------+
| Slice Logic | 0.003 | 1 | --- | --- |
| LUT as Logic | 0.003 | 1 | 101400 | <0.01 |
| Signals | 0.013 | 5 | --- | --- |
| I/O | 0.373 | 5 | 285 | 1.75 |
| Static Power | 0.087 | | | |
| Total | 0.476 | | | |
+----------------+-----------+----------+-----------+-----------------+
1.2 Power Supply Summary
@@ -66,11 +67,11 @@ Table of Contents
+-----------+-------------+-----------+-------------+------------+
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
+-----------+-------------+-----------+-------------+------------+
| Vccint | 0.950 | 0.023 | 0.000 | 0.023 |
| Vccaux | 1.800 | 0.016 | 0.000 | 0.016 |
| Vccint | 0.950 | 0.056 | 0.032 | 0.024 |
| Vccaux | 1.800 | 0.046 | 0.029 | 0.016 |
| Vcco33 | 3.300 | 0.000 | 0.000 | 0.000 |
| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 |
| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 |
| Vcco18 | 1.800 | 0.171 | 0.170 | 0.001 |
| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 |
| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 |
| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 |
@@ -86,17 +87,17 @@ Table of Contents
1.3 Confidence Level
--------------------
+-----------------------------+------------+------------------------------------------------+--------+
| User Input Data | Confidence | Details | Action |
+-----------------------------+------------+------------------------------------------------+--------+
| Design implementation state | High | Design is routed | |
| Clock nodes activity | High | User specified more than 95% of clocks | |
| I/O nodes activity | High | User specified more than 95% of inputs | |
| Internal nodes activity | High | User specified more than 25% of internal nodes | |
| Device models | High | Device models are Production | |
| | | | |
| Overall confidence level | High | | |
+-----------------------------+------------+------------------------------------------------+--------+
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| User Input Data | Confidence | Details | Action |
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| Design implementation state | High | Design is routed | |
| Clock nodes activity | High | User specified more than 95% of clocks | |
| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
| Device models | High | Device models are Production | |
| | | | |
| Overall confidence level | Low | | |
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
2. Settings
@@ -131,8 +132,11 @@ Table of Contents
3.1 By Hierarchy
----------------
+------+-----------+
| Name | Power (W) |
+------+-----------+
+----------+-----------+
| Name | Power (W) |
+----------+-----------+
| CPU9bits | 0.389 |
| CU | 0.007 |
+----------+-----------+