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Computer works (kinda)

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jose.rodriguezlabra
2019-03-13 12:51:44 -04:00
parent 026eb65861
commit 11a1d99e92
64 changed files with 809 additions and 422 deletions
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lab2CA.sim/sim_1/behav/xsim/CPU9bits_tb_vlog.prj Normal file
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# compile verilog/system verilog design source files
verilog xil_defaultlib \
"../../../../lab2CA.srcs/sources_1/new/ALU.v" \
"../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \
"../../../../lab2CA.srcs/sources_1/new/ControlUnit.v" \
"../../../../lab2CA.srcs/sources_1/new/FetchUnit.v" \
"../../../../lab2CA.srcs/sources_1/new/RegFile.v" \
"../../../../lab2CA.srcs/sources_1/new/CPU9bits.v" \
# compile glbl module
verilog xil_defaultlib "glbl.v"
# Do not sort compile order
nosort