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Computer works (kinda)

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jose.rodriguezlabra
2019-03-13 12:51:44 -04:00
parent 026eb65861
commit 11a1d99e92
64 changed files with 809 additions and 422 deletions
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17
lab2CA.srcs/sources_1/new/BasicModules.v
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@@ -264,14 +264,17 @@ module decoder (
output reg [3:0] regOut);
always @(en, index)begin
if(en == 1)begin
if(en == 0)begin
case(index)
2'b00: regOut <= 4'b0001;
2'b01: regOut <= 4'b0010;
2'b10: regOut <= 4'b0100;
2'b11: regOut <= 4'b1000;
default: regOut <= 4'b0000;
endcase
2'b00: regOut <= 4'b1110;
2'b01: regOut <= 4'b1101;
2'b10: regOut <= 4'b1011;
2'b11: regOut <= 4'b0111;
default: regOut <= 4'b1111;
endcase
end
else begin
regOut <= 4'b1111;
end
end
endmodule