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Computer works (kinda)

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jose.rodriguezlabra
2019-03-13 12:51:44 -04:00
parent 026eb65861
commit 11a1d99e92
64 changed files with 809 additions and 422 deletions
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68
lab2CA.srcs/sources_1/new/ControlUnit.v
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@@ -16,81 +16,133 @@ module ControlUnit(
if(functBit == 1) begin
aluOut <= 4'b0001; //sub
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
FU <= 3'b001;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
end
else begin
aluOut <= 4'b0000; //Add
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
end
4'b1101: begin
aluOut <= 4'b0011; //nor
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
end
4'b1110:
if(functBit == 1) begin
aluOut <= 4'b0100; //and
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
end
else begin
aluOut <= 4'b0010; //or
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
end
4'b1111:
if(functBit == 1) begin
aluOut <= 4'b0110; //srl
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
end
else begin
aluOut <= 4'b0101; //shift left
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
end
4'b0111: begin
aluOut <= 4'b1001; //Less than
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
end
4'b0110: begin
aluOut <= 4'b0000;
addi <= 1'b1; // addi
RegEn <= 1'b0;
RegEn <= 1'b1;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
mem <= 1'b0;
end
4'b1001: begin //We got it wrong, first bit must always be zero whenever branching happens. Fixed
//FU <= 3'b010; // jump
aluOut <= 4'b0000;
FU <= 3'b010; // jump
RegEn <= 1'b1;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
end
4'b1010: begin
//FU <= 3'b011; // branch
aluOut <= 4'b0000;
FU <= 3'b110; // branch
RegEn <= 1'b1;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
end
4'b1000: begin
//FU <= 3'b001; // jumpreg
aluOut <= 4'b0000;
FU <= 3'b000; // jumpreg
RegEn <= 1'b1;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
end
4'b0001: begin
mem <= 1'b0; // load
aluOut <= 4'b0000;
mem <= 1'b1; // load
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
addi <= 1'b0;
halt <= 1'b0;
end
4'b0010: begin
mem <= 1'b1; // store
aluOut <= 4'b0000;
mem <= 1'b0; // store
RegEn <= 1'b1;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
addi <= 1'b0;
end
4'b0000: begin // regs should initialize at 0, so we shouldn't need to declare it everywhere
halt <= 1'b1; // halt
RegEn <= 1'b1;
FU <= 3'b001; // Disable Branching
addi <= 1'b0;
aluOut <= 4'b0000;
mem <= 1'b0;
end
default: aluOut <= 4'bxxxx;
default: begin
halt <= 1'b1;
RegEn <= 1'b1;
FU <= 3'b001;
addi <= 1'b0;
aluOut <= 4'b0000;
mem <= 1'b0;
end
endcase
end
endmodule