diff --git a/lab2CA.srcs/sources_1/new/ControlUnit.v b/lab2CA.srcs/sources_1/new/ControlUnit.v
index 4e77cc8..613709b 100644
--- a/lab2CA.srcs/sources_1/new/ControlUnit.v
+++ b/lab2CA.srcs/sources_1/new/ControlUnit.v
@@ -5,13 +5,8 @@ module ControlUnit(
     input wire functBit,
     output reg [3:0] aluOut,
     output reg [2:0] FU,
-    output reg addi,
-    output reg mem, dataMemEn,
-    output reg RegEn,
-    output reg halt,
-    output reg link,
     output reg [1:0] bank,
-    output reg js);
+    output reg addi, mem, dataMemEn, RegEn, halt, link, js);
     
         always @(instIn, functBit)begin
             case(instIn)
@@ -21,6 +16,7 @@ module ControlUnit(
                     RegEn <= 1'b1; 
                     FU <= 3'b001; // Disable Branching
                     addi <= 1'b0;
+                    dataMemEn <= 1'b0; // Disabled
                     aluOut <= 4'b0000;
                     mem <= 1'b0;
                     link <= 1'b0;
@@ -31,7 +27,7 @@ module ControlUnit(
                 begin
                     aluOut <= 4'b0000;
                     mem <= 1'b1;
-                    dataMemEn <= 1'b0;
+                    dataMemEn <= 1'b0; // Disabled
                     RegEn <= 1'b0;
                     FU <= 3'b001; // Disable Branching
                     addi <= 1'b0;
@@ -44,7 +40,7 @@ module ControlUnit(
                 begin
                     aluOut <= 4'b0000;
                     mem <= 1'b0;
-                    dataMemEn <= 1'b1;
+                    dataMemEn <= 1'b1; // Enabled
                     RegEn <= 1'b1;
                     FU <= 3'b001; // Disable Branching
                     halt <= 1'b0;
@@ -61,7 +57,7 @@ module ControlUnit(
                     addi <= 1'b0;
                     aluOut <= 4'b0000;
                     mem <= 1'b0;
-                    dataMemEn <= 1'b0;
+                    dataMemEn <= 1'b0; // Disabled
                     link <= 1'b1;
                     bank <= 2'b10;
                     js <= 1'b0;
@@ -74,7 +70,7 @@ module ControlUnit(
                     halt <= 1'b0;
                     addi <= 1'b0;
                     mem <= 1'b0;
-                    dataMemEn <= 1'b0;
+                    dataMemEn <= 1'b0; // Disabled
                     link <= 1'b0;
                     bank <= 2'b10;
                     js <= 1'b0;
@@ -87,7 +83,7 @@ module ControlUnit(
                     halt <= 1'b0;
                     addi <= 1'b0;
                     mem <= 1'b0;
-                    dataMemEn <= 1'b0;
+                    dataMemEn <= 1'b0; // Disabled
                     link <= 1'b0;
                     bank <= 2'b10;
                     js <= 1'b0;
@@ -99,7 +95,7 @@ module ControlUnit(
                     halt <= 1'b0;
                     addi <= 1'b0;
                     mem <= 1'b0;
-                    dataMemEn <= 1'b0;
+                    dataMemEn <= 1'b0; // Disabled
                     link <= 1'b0;
                     bank <= 2'b10;
                     js <= 1'b0;
@@ -112,7 +108,7 @@ module ControlUnit(
                     FU <= 3'b001; // Disable Branching
                     halt <= 1'b0;
                     mem <= 1'b0;
-                    dataMemEn <= 1'b0;
+                    dataMemEn <= 1'b0; // Disabled
                     link <= 1'b0;
                     bank <= 2'b10;
                     js <= 1'b0;
@@ -125,7 +121,7 @@ module ControlUnit(
                     halt <= 1'b0;
                     addi <= 1'b0;
                     mem <= 1'b0;
-                    dataMemEn <= 1'b0;
+                    dataMemEn <= 1'b0; // Disabled
                     link <= 1'b0;
                     bank <= 2'b10;
                     js <= 1'b0;
@@ -138,7 +134,7 @@ module ControlUnit(
                     halt <= 1'b0;
                     addi <= 1'b0;
                     mem <= 1'b0;
-                    dataMemEn <= 1'b0;
+                    dataMemEn <= 1'b0; // Disabled
                     link <= 1'b0;
                     bank <= 2'b10;
                     js <= 1'b0;
@@ -151,7 +147,7 @@ module ControlUnit(
                     halt <= 1'b0;
                     addi <= 1'b0;
                     mem <= 1'b0;
-                    dataMemEn <= 1'b0;
+                    dataMemEn <= 1'b0; // Disabled
                     link <= 1'b0;
                     bank <= 2'b10;
                     js <= 1'b0;
@@ -163,6 +159,7 @@ module ControlUnit(
                     FU <= 3'b001; // Disable Branching
                     addi <= 1'b0;
                     aluOut <= 4'b0000;
+                    dataMemEn <= 1'b0; // Disabled
                     mem <= 1'b0;
                     link <= 1'b0;
                     bank <= {functBit,functBit};
@@ -176,7 +173,7 @@ module ControlUnit(
                     halt <= 1'b0;
                     addi <= 1'b0;
                     mem <= 1'b0;
-                    dataMemEn <= 1'b0;
+                    dataMemEn <= 1'b0; // Disabled
                     link <= 1'b0;
                     bank <= 2'b10;
                     js <= 1'b1;
@@ -189,7 +186,7 @@ module ControlUnit(
                     halt <= 1'b0;
                     addi <= 1'b0;
                     mem <= 1'b0;
-                    dataMemEn <= 1'b0;
+                    dataMemEn <= 1'b0; // Disabled
                     link <= 1'b0;
                     bank <= 2'b10;
                     js <= 1'b0;
@@ -202,7 +199,7 @@ module ControlUnit(
                     halt <= 1'b0;
                     addi <= 1'b0;
                     mem <= 1'b0;
-                    dataMemEn <= 1'b0;
+                    dataMemEn <= 1'b0; // Disabled
                     link <= 1'b0;
                     bank <= 2'b10;
                     js <= 1'b0;
@@ -216,7 +213,7 @@ module ControlUnit(
                     halt <= 1'b0;
                     addi <= 1'b0;
                     mem <= 1'b0;
-                    dataMemEn <= 1'b0;
+                    dataMemEn <= 1'b0; // Disabled
                     link <= 1'b0;
                     bank <= 2'b10;
                     js <= 1'b0;
@@ -229,7 +226,7 @@ module ControlUnit(
                     halt <= 1'b0;
                     addi <= 1'b0;
                     mem <= 1'b0;
-                    dataMemEn <= 1'b0;
+                    dataMemEn <= 1'b0; // Disabled
                     link <= 1'b0;
                     bank <= 2'b10;
                     js <= 1'b0;
@@ -243,7 +240,7 @@ module ControlUnit(
                     halt <= 1'b0;
                     addi <= 1'b0;
                     mem <= 1'b0;
-                    dataMemEn <= 1'b0;
+                    dataMemEn <= 1'b0; // Disabled
                     link <= 1'b0;
                     bank <= 2'b10;
                     js <= 1'b0;
@@ -256,7 +253,7 @@ module ControlUnit(
                     halt <= 1'b0;
                     addi <= 1'b0;
                     mem <= 1'b0;
-                    dataMemEn <= 1'b0;
+                    dataMemEn <= 1'b0; // Disabled
                     link <= 1'b0;
                     bank <= 2'b10;
                     js <= 1'b0;
@@ -265,7 +262,8 @@ module ControlUnit(
                 begin
                     halt <= 1'b1;
                     RegEn <= 1'b1; 
-                    FU <= 3'b001; 
+                    FU <= 3'b001;
+                    dataMemEn <= 1'b0; // Disabled
                     addi <= 1'b0;
                     aluOut <= 4'b0000;
                     mem <= 1'b0;