diff --git a/CPU9bits_tb_behav.wcfg b/CPU9bits_tb_behav.wcfg index d0808e6..56a2585 100644 --- a/CPU9bits_tb_behav.wcfg +++ b/CPU9bits_tb_behav.wcfg @@ -11,19 +11,18 @@ - - - + + + - - + + - + Program Counter label - clk clk @@ -51,14 +50,6 @@ Fetch Unit label - - clk - clk - - - reset - reset - op_idx op_idx @@ -66,11 +57,12 @@ AddrIn[8:0] AddrIn[8:0] - + UNSIGNEDDECRADIX AddrOut[8:0] AddrOut[8:0] + UNSIGNEDDECRADIX progC_out[8:0] @@ -88,7 +80,6 @@ Control Unit label - instIn[3:0] instIn[3:0] @@ -104,7 +95,6 @@ FU[2:0] FU[2:0] - bank[1:0] @@ -139,6 +129,125 @@ js + + Registers + label + + En + En + + + write_index[1:0] + write_index[1:0] + UNSIGNEDDECRADIX + + + op0_idx[1:0] + op0_idx[1:0] + UNSIGNEDDECRADIX + + + op1_idx[1:0] + op1_idx[1:0] + UNSIGNEDDECRADIX + + + write_data[8:0] + write_data[8:0] + UNSIGNEDDECRADIX + + + op0[8:0] + op0[8:0] + UNSIGNEDDECRADIX + + + op1[8:0] + op1[8:0] + UNSIGNEDDECRADIX + + + decOut[3:0] + decOut[3:0] + UNSIGNEDDECRADIX + + + r0_out[8:0] + r0_out[8:0] + SIGNEDDECRADIX + + + r1_out[8:0] + r1_out[8:0] + SIGNEDDECRADIX + + + r2_out[8:0] + r2_out[8:0] + SIGNEDDECRADIX + + + r3_out[8:0] + r3_out[8:0] + SIGNEDDECRADIX + + + + Banks + label + + En + En + + + write_index[1:0] + write_index[1:0] + + + op0_idx[1:0] + op0_idx[1:0] + + + op1_idx[1:0] + op1_idx[1:0] + + + write_data[8:0] + write_data[8:0] + + + op0[8:0] + op0[8:0] + + + op1[8:0] + op1[8:0] + + + decOut[3:0] + decOut[3:0] + + + r0_out[8:0] + r0_out[8:0] + SIGNEDDECRADIX + + + r1_out[8:0] + r1_out[8:0] + SIGNEDDECRADIX + + + r2_out[8:0] + r2_out[8:0] + SIGNEDDECRADIX + + + r3_out[8:0] + r3_out[8:0] + SIGNEDDECRADIX + + Divider label @@ -146,7 +255,6 @@ Instruction Memory label - address[8:0] address[8:0] @@ -208,12 +316,135 @@ Din[50:0] Din[50:0] - Dout[50:0] Dout[50:0] - + + + + Data Memory + label + + clk + clk + + + writeEnable + writeEnable + + + address[8:0] + address[8:0] + UNSIGNEDDECRADIX + + + writeData[8:0] + writeData[8:0] + + + readData[8:0] + readData[8:0] + + + memory[100:0][8:0] + memory[100:0][8:0] + + + + Divider + label + + + Mux 3 + label + + switch + switch + + + A[8:0] + A[8:0] + SIGNEDDECRADIX + + + B[8:0] + B[8:0] + SIGNEDDECRADIX + + + out[8:0] + out[8:0] + SIGNEDDECRADIX + + + + Mux 4 + label + + switch + switch + + + A[8:0] + A[8:0] + SIGNEDDECRADIX + + + B[8:0] + B[8:0] + SIGNEDDECRADIX + + + out[8:0] + out[8:0] + SIGNEDDECRADIX + + + + Mux 5 + label + + switch + switch + + + A[8:0] + A[8:0] + SIGNEDDECRADIX + + + B[8:0] + B[8:0] + SIGNEDDECRADIX + + + out[8:0] + out[8:0] + SIGNEDDECRADIX + + + + Mux 6 + label + + switch + switch + + + A[8:0] + A[8:0] + SIGNEDDECRADIX + + + B[8:0] + B[8:0] + SIGNEDDECRADIX + + + out[8:0] + out[8:0] + SIGNEDDECRADIX diff --git a/lab2CA.cache/wt/webtalk_pa.xml b/lab2CA.cache/wt/webtalk_pa.xml index 9fe1c1e..bd50188 100644 --- a/lab2CA.cache/wt/webtalk_pa.xml +++ b/lab2CA.cache/wt/webtalk_pa.xml @@ -3,10 +3,10 @@ - +
- +
@@ -18,12 +18,11 @@ This means code written to parse this file will need to be revisited each subseq - - + + - - - + + @@ -31,38 +30,37 @@ This means code written to parse this file will need to be revisited each subseq - + - - - - - - - - + + + + + + + + + - - + + - + - - - - - - + + + + - + - + - +
diff --git a/lab2CA.runs/impl_1/gen_run.xml b/lab2CA.runs/impl_1/gen_run.xml index 43818c5..dd35d50 100644 --- a/lab2CA.runs/impl_1/gen_run.xml +++ b/lab2CA.runs/impl_1/gen_run.xml @@ -1,5 +1,5 @@ - + diff --git a/lab2CA.sim/sim_1/behav/xsim/xelab.pb b/lab2CA.sim/sim_1/behav/xsim/xelab.pb index d5273eb..a1ea57e 100644 Binary files a/lab2CA.sim/sim_1/behav/xsim/xelab.pb and b/lab2CA.sim/sim_1/behav/xsim/xelab.pb differ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl index edbea6d..66eb116 100644 --- a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl @@ -1,10 +1,10 @@ -webtalk_init -webtalk_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/ +webtalk_init -webtalk_dir C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/ webtalk_register_client -client project -webtalk_add_data -client project -key date_generated -value "Thu Apr 11 21:53:39 2019" -context "software_version_and_target_device" +webtalk_add_data -client project -key date_generated -value "Thu Apr 11 21:13:26 2019" -context "software_version_and_target_device" webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device" webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device" webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" -webtalk_add_data -client project -key registration_id -value "174150793_174150794_210688225_140" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" @@ -12,21 +12,21 @@ webtalk_add_data -client project -key target_family -value "not_applicable" -con webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" -webtalk_add_data -client project -key random_id -value "4e917e26-7591-4435-9135-15bd446b0238" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "17336daf-0d92-4f07-b4a4-ff1c52043edb" -context "software_version_and_target_device" webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device" -webtalk_add_data -client project -key project_iteration -value "176" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "153" -context "software_version_and_target_device" webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" -webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) CPU E5-1620 v3 @ 3.50GHz" -context "user_environment" -webtalk_add_data -client project -key cpu_speed -value "3492 MHz" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i5-3230M CPU @ 2.60GHz" -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "2594 MHz" -context "user_environment" webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" -webtalk_add_data -client project -key system_ram -value "34.000 GB" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "8.000 GB" -context "user_environment" webtalk_register_client -client xsim webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" -webtalk_add_data -client xsim -key runtime -value "115 ns" -context "xsim\\usage" +webtalk_add_data -client xsim -key runtime -value "315 ns" -context "xsim\\usage" webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage" -webtalk_add_data -client xsim -key Simulation_Time -value "0.12_sec" -context "xsim\\usage" -webtalk_add_data -client xsim -key Simulation_Memory -value "6588_KB" -context "xsim\\usage" -webtalk_transmit -clientid 428585050 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_add_data -client xsim -key Simulation_Time -value "0.06_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Memory -value "5980_KB" -context "xsim\\usage" +webtalk_transmit -clientid 4273905684 -regid "" -xml C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" webtalk_terminate diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem index 3d74600..25b0fbb 100644 Binary files a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem and b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem differ diff --git a/lab2CA.sim/sim_1/behav/xsim/xvlog.pb b/lab2CA.sim/sim_1/behav/xsim/xvlog.pb index b155e40..d512677 100644 Binary files a/lab2CA.sim/sim_1/behav/xsim/xvlog.pb and b/lab2CA.sim/sim_1/behav/xsim/xvlog.pb differ diff --git a/lab2CA.srcs/sources_1/new/ControlUnit.v b/lab2CA.srcs/sources_1/new/ControlUnit.v index 93f605d..7e17462 100644 --- a/lab2CA.srcs/sources_1/new/ControlUnit.v +++ b/lab2CA.srcs/sources_1/new/ControlUnit.v @@ -7,7 +7,7 @@ module ControlUnit( output reg [2:0] FU, output reg [1:0] bank, output reg addi, mem, dataMemEn, RegEn, halt, link, js, compare0, compare1 - ); + ); always @(instIn, functBit) begin diff --git a/lab2CA.srcs/sources_1/new/instructionMemory.v b/lab2CA.srcs/sources_1/new/instructionMemory.v index a5e9600..e9f16a1 100644 --- a/lab2CA.srcs/sources_1/new/instructionMemory.v +++ b/lab2CA.srcs/sources_1/new/instructionMemory.v @@ -5,18 +5,20 @@ module instructionMemory( output reg [8:0] readData ); - reg [8:0] memory [6:0]; // Maximum of 512 memory locations + reg [8:0] memory [8:0]; // Maximum of 512 memory locations // Vivado will give warnings of unconnected ports on the "address" bus if they are unused initial begin //Equation Solver - memory[0] <= 9'b000000000; - memory[1] <= 9'b000100000; //load - memory[2] <= 9'b000101000; //load - memory[3] <= 9'b010100010; //add - memory[4] <= 9'b111100000; //shift left - memory[5] <= 9'b000000001; //NOP - memory[6] <= 9'b111100000; //shift left + memory[0] <= 9'b000000000; //Stall + memory[1] <= 9'b000000000; //Stall + memory[2] <= 9'b011000000; //addi + memory[3] <= 9'b011001001; //addi + memory[4] <= 9'b000100000; //load + memory[5] <= 9'b000101010; //load + memory[6] <= 9'b010100010; //add + memory[7] <= 9'b111100000; //shift left + memory[8] <= 9'b111100000; //shift left // //Testing all instructions // memory[6] <= 9'b010100011; //sub diff --git a/lab2CA.xpr b/lab2CA.xpr index 6d02ab8..f36c02f 100644 --- a/lab2CA.xpr +++ b/lab2CA.xpr @@ -3,7 +3,7 @@ - +