diff --git a/README.md b/README.md
index b485079..d4c4a24 100644
--- a/README.md
+++ b/README.md
@@ -10,8 +10,7 @@
* Need to allow for signed numbers
* Remove subtraction from ALU
* Have arithmetic shift left and right
-* Uncomment all testbenches
- * We can have multiple testbenches active at once
+* Uncomment all testbenches (We can have multiple testbenches active at once)
* Bitwise operations do not need a 1-bit implementation, modify 9-bit and keep it only
* Comparator needed
* Make subtraction more efficient
diff --git a/lab2CA.srcs/sources_1/new/ALU.v b/lab2CA.srcs/sources_1/new/ALU.v
index 06c12db..664cd6e 100644
--- a/lab2CA.srcs/sources_1/new/ALU.v
+++ b/lab2CA.srcs/sources_1/new/ALU.v
@@ -62,47 +62,47 @@ module ALU(
endmodule
-testbench
+//testbench
module alu_tb();
-reg [8:0] a;
-reg [8:0] b;
-reg [2:0] c;
-wire [8:0] d;
+ reg [8:0] a;
+ reg [8:0] b;
+ reg [2:0] c;
+ wire [8:0] d;
-ALU alu0(
-.operand0(a),
-.operand1(b),
-.opcode(c),
-.result(d));
+ ALU alu0(
+ .operand0(a),
+ .operand1(b),
+ .opcode(c),
+ .result(d));
- initial begin
- a = 9'b000000111;
- b = 9'b000111000;
- c = 3'b000;
- #5
- a = 9'b000011000;
- b = 9'b000011000;
- c = 3'b001;
- #5
- a = 9'b101010100;
- b = 9'b010101011;
- c = 3'b010;
- #5
- a = 9'b101010100;
- b = 9'b010101000;
- c = 3'b011;
- #5
- a = 9'b000110000;
- b = 9'b000111000;
- c = 3'b100;
- #5
- a = 9'b01011000;
- c = 3'b101;
- #5
- a = 9'b00001010;
- c = 3'b110;
- #5
- #5 $finish;
+ initial begin
+ a = 9'b000000111;
+ b = 9'b000111000;
+ c = 3'b000;
+ #5
+ a = 9'b000011000;
+ b = 9'b000011000;
+ c = 3'b001;
+ #5
+ a = 9'b101010100;
+ b = 9'b010101011;
+ c = 3'b010;
+ #5
+ a = 9'b101010100;
+ b = 9'b010101000;
+ c = 3'b011;
+ #5
+ a = 9'b000110000;
+ b = 9'b000111000;
+ c = 3'b100;
+ #5
+ a = 9'b01011000;
+ c = 3'b101;
+ #5
+ a = 9'b00001010;
+ c = 3'b110;
+ #5
+ $finish;
- end
+ end
endmodule
diff --git a/lab2CA.srcs/sources_1/new/BasicModules.v b/lab2CA.srcs/sources_1/new/BasicModules.v
index 1dee8a1..9e3a5d7 100644
--- a/lab2CA.srcs/sources_1/new/BasicModules.v
+++ b/lab2CA.srcs/sources_1/new/BasicModules.v
@@ -14,40 +14,43 @@ endmodule
//testbench
module add1bit_tb();
-reg v;
-reg w;
-reg x;
-wire y;
-wire z;
+ reg v;
+ reg w;
+ reg x;
+ wire y;
+ wire z;
-add_1bit add0(
- .A(v),
- .B(w),
- .Cin(x),
- .S(y),
- .Cout(z));
-
- initial begin
- v = 0;
- w = 0;
- x = 0;
- #5
- v = 0;
- w = 1;
- x = 0;
- #5
- v = 0;
- w = 0;
- x = 1;
- #5
- v = 1;
- w = 1;
- x = 0;
- #5
- v = 1;
- w = 1;
- x = 1;
- end
+ add_1bit tb0(
+ .A(v),
+ .B(w),
+ .Cin(x),
+ .S(y),
+ .Cout(z));
+
+ initial begin
+ v = 0;
+ w = 0;
+ x = 0;
+ #5
+ v = 0;
+ w = 1;
+ x = 0;
+ #5
+ v = 0;
+ w = 0;
+ x = 1;
+ #5
+ v = 1;
+ w = 1;
+ x = 0;
+ #5
+ v = 1;
+ w = 1;
+ x = 1;
+ #5
+ $finish;
+
+ end
endmodule
module add_9bit(
@@ -133,41 +136,40 @@ endmodule
//testbench
module add9bit_tb();
-reg [8:0] a;
-reg [8:0] b;
-reg cin;
-wire [8:0] s;
-wire cout;
+ reg [8:0] a,b;
+ reg cin;
+ wire [8:0] s;
+ wire cout;
-add_9bit add0(
- .A(a),
- .B(b),
- .Cin(cin),
- .Sum(s),
- .Cout(cout));
+ add_9bit tb0(
+ .A(a),
+ .B(b),
+ .Cin(cin),
+ .Sum(s),
+ .Cout(cout));
- initial begin
- a = 9'b000000000;
- b = 9'b000000000;
- cin = 0;
- #5
- a = 9'b000000001;
- b = 9'b000000000;
- cin = 0;
- #5
- a = 9'b000000000;
- b = 9'b000000001;
- cin = 1;
- #5
- a = 9'b000000001;
- b = 9'b000000001;
- cin = 0;
- #5
- a = 9'b000001000;
- b = 9'b000000001;
- cin = 1;
- end
+ initial begin
+ a = 9'b000000000;
+ b = 9'b000000000;
+ cin = 0;
+ #5
+ a = 9'b000000001;
+ b = 9'b000000000;
+ cin = 0;
+ #5
+ a = 9'b000000000;
+ b = 9'b000000001;
+ cin = 1;
+ #5
+ a = 9'b000000001;
+ b = 9'b000000001;
+ cin = 0;
+ #5
+ a = 9'b000001000;
+ b = 9'b000000001;
+ cin = 1;
+ end
endmodule
module and_1bit(
@@ -181,30 +183,30 @@ endmodule
//testbench
module and1bit_tb();
-reg a;
-reg b;
-wire c;
+ reg a,b;
+ wire c;
-and_1bit and0(
-.A(a),
-.B(b),
-.C(c));
+ and_1bit and0(
+ .A(a),
+ .B(b),
+ .C(c));
- initial begin
- a = 0;
- b = 0;
- #5
- a = 0;
- b = 1;
- #5
- a = 1;
- b = 0;
- #5
- a = 1;
- b = 1;
- #5 $finish;
+ initial begin
+ a = 0;
+ b = 0;
+ #5
+ a = 0;
+ b = 1;
+ #5
+ a = 1;
+ b = 0;
+ #5
+ a = 1;
+ b = 1;
+ #5
+ $finish;
- end
+ end
endmodule
module and_9bit(
@@ -261,36 +263,36 @@ endmodule
//testbench
module and9bit_tb();
-reg [8:0] a;
-reg [8:0] b;
-wire [8:0] c;
+ reg [8:0] a,b;
+ wire [8:0] c;
-and_9bit and0(
-.A(a),
-.B(b),
-.C(c));
+ and_9bit and0(
+ .A(a),
+ .B(b),
+ .C(c));
- initial begin
- a = 9'b000000000;
- b = 9'b000000000;
- #5
- a = 9'b000000000;
- b = 9'b000000001;
- #5
- a = 9'b000000001;
- b = 9'b000000000;
- #5
- a = 9'b000000001;
- b = 9'b000000001;
- #5
- a = 9'b000100001;
- b = 9'b000000001;
- #5
- a = 9'b000100001;
- b = 9'b000100001;
- #5 $finish;
+ initial begin
+ a = 9'b000000000;
+ b = 9'b000000000;
+ #5
+ a = 9'b000000000;
+ b = 9'b000000001;
+ #5
+ a = 9'b000000001;
+ b = 9'b000000000;
+ #5
+ a = 9'b000000001;
+ b = 9'b000000001;
+ #5
+ a = 9'b000100001;
+ b = 9'b000000001;
+ #5
+ a = 9'b000100001;
+ b = 9'b000100001;
+ #5
+ $finish;
- end
+ end
endmodule
module gen_clock();
@@ -303,15 +305,15 @@ module gen_clock();
end
endmodule
-testbench
+//testbench
module gen_clock_tb();
-
-reg clk;
+ reg clk;
gen
-module mux_2_1(input wire switch,
- input wire [8:0] A,B,
- output reg [8:0] out);
+module mux_2_1 tb0(
+ input wire switch,
+ input wire [8:0] A,B,
+ output reg [8:0] out);
always @(A,B,switch) begin
case (switch)
@@ -320,49 +322,48 @@ module mux_2_1(input wire switch,
default : out = 9'bxxxxxxxxx;
endcase
end
-
endmodule
//testbench
module mux_2_1_tb();
-reg s;
-reg [8:0] a;
-reg [8:0] b;
-wire [8:0] c;
+ reg s;
+ reg [8:0] a,b;
+ wire [8:0] c;
-mux_2_1 mux0(
-.switch(s),
-.A(a),
-.B(b),
-.out(c));
+ mux_2_1 tb0(
+ .switch(s),
+ .A(a),
+ .B(b),
+ .out(c));
- initial begin
- s = 0;
- a = 9'b000000101;
- b = 9'b000000000;
- #5
- s = 1;
- a = 9'b000000001;
- b = 9'b000100001;
- #5
- s = 0;
- a = 9'b000000000;
- b = 9'b000000001;
- #5
- s = 1;
- a = 9'b000000001;
- b = 9'b000000001;
- #5
- s = 0;
- a = 9'b000010001;
- b = 9'b000000001;
- #5
- s = 1;
- a = 9'b000010001;
- b = 9'b000010111;
- #5 $finish;
+ initial begin
+ s = 0;
+ a = 9'b000000101;
+ b = 9'b000000000;
+ #5
+ s = 1;
+ a = 9'b000000001;
+ b = 9'b000100001;
+ #5
+ s = 0;
+ a = 9'b000000000;
+ b = 9'b000000001;
+ #5
+ s = 1;
+ a = 9'b000000001;
+ b = 9'b000000001;
+ #5
+ s = 0;
+ a = 9'b000010001;
+ b = 9'b000000001;
+ #5
+ s = 1;
+ a = 9'b000010001;
+ b = 9'b000010111;
+ #5
+ $finish;
- end
+ end
endmodule
module mux_4_1(input wire [1:0] switch,
@@ -383,48 +384,46 @@ endmodule
//testbench
module mux_4_1_tb();
-reg [1:0] s;
-reg [8:0] a;
-reg [8:0] b;
-reg [8:0] c;
-reg [8:0] d;
-wire [8:0] e;
+ reg [1:0] s;
+ reg [8:0] a,b,c,d;
+ wire [8:0] e;
-mux_4_1 mux1(
-.switch(s),
-.A(a),
-.B(b),
-.C(c),
-.D(d),
-.out(e));
+ mux_4_1 tb0(
+ .switch(s),
+ .A(a),
+ .B(b),
+ .C(c),
+ .D(d),
+ .out(e));
- initial begin
- s = 2'b00;
- a = 9'b000000101;
- b = 9'b000111100;
- c = 9'b001001001;
- d = 9'b100000000;
- #5
- s = 2'b01;
- a = 9'b000000101;
- b = 9'b000111100;
- c = 9'b001001001;
- d = 9'b100000000;
- #5
- s = 2'b10;
- a = 9'b000000101;
- b = 9'b000111100;
- c = 9'b001001001;
- d = 9'b100000000;
- #5
- s = 2'b11;
- a = 9'b000000101;
- b = 9'b000111100;
- c = 9'b001001001;
- d = 9'b100000000;
- #5 $finish;
+ initial begin
+ s = 2'b00;
+ a = 9'b000000101;
+ b = 9'b000111100;
+ c = 9'b001001001;
+ d = 9'b100000000;
+ #5
+ s = 2'b01;
+ a = 9'b000000101;
+ b = 9'b000111100;
+ c = 9'b001001001;
+ d = 9'b100000000;
+ #5
+ s = 2'b10;
+ a = 9'b000000101;
+ b = 9'b000111100;
+ c = 9'b001001001;
+ d = 9'b100000000;
+ #5
+ s = 2'b11;
+ a = 9'b000000101;
+ b = 9'b000111100;
+ c = 9'b001001001;
+ d = 9'b100000000;
+ #5
+ $finish;
- end
+ end
endmodule
module mux_8_1(
@@ -445,61 +444,54 @@ module mux_8_1(
default : out = 9'bxxxxxxxxx;
endcase
end
-
endmodule
//testbench
module mux_8_1_tb();
-reg [2:0] s;
-reg [8:0] a;
-reg [8:0] b;
-reg [8:0] c;
-reg [8:0] d;
-reg [8:0] e;
-reg [8:0] f;
-reg [8:0] g;
-reg [8:0] h;
-wire [8:0] out;
+ reg [2:0] s;
+ reg [8:0] a,b,c,d,e,f,g,h;
+ wire [8:0] out;
-mux_8_1 mux1(
-.switch(s),
-.A(a),
-.B(b),
-.C(c),
-.D(d),
-.E(e),
-.F(f),
-.G(g),
-.H(h),
-.out(out));
+ mux_8_1 tb0(
+ .switch(s),
+ .A(a),
+ .B(b),
+ .C(c),
+ .D(d),
+ .E(e),
+ .F(f),
+ .G(g),
+ .H(h),
+ .out(out));
- initial begin
- s = 3'b000;
- a = 9'b000000101;
- b = 9'b000111100;
- c = 9'b001001001;
- d = 9'b100110000;
- e = 9'b010000101;
- f = 9'b010111100;
- g = 9'b011001001;
- h = 9'b111000000;
- #5
- s = 3'b001;
- #5
- s = 3'b010;
- #5
- s = 3'b011;
- #5
- s = 3'b100;
- #5
- s = 3'b101;
- #5
- s = 3'b110;
- #5
- s = 3'b111;
- #5 $finish;
+ initial begin
+ s = 3'b000;
+ a = 9'b000000101;
+ b = 9'b000111100;
+ c = 9'b001001001;
+ d = 9'b100110000;
+ e = 9'b010000101;
+ f = 9'b010111100;
+ g = 9'b011001001;
+ h = 9'b111000000;
+ #5
+ s = 3'b001;
+ #5
+ s = 3'b010;
+ #5
+ s = 3'b011;
+ #5
+ s = 3'b100;
+ #5
+ s = 3'b101;
+ #5
+ s = 3'b110;
+ #5
+ s = 3'b111;
+ #5
+ $finish;
- end
+ end
endmodule
module mux_16_1(
@@ -543,30 +535,31 @@ endmodule
//testbench
module nor_1bit_tb();
-reg a;
-reg b;
-wire c;
+ reg a;
+ reg b;
+ wire c;
-nor_1bit nor0(
-.A(a),
-.B(b),
-.C(c));
+ nor_1bit nor0(
+ .A(a),
+ .B(b),
+ .C(c));
- initial begin
- a = 0;
- b = 0;
- #5
- a = 0;
- b = 1;
- #5
- a = 1;
- b = 0;
- #5
- a = 1;
- b = 1;
- #5 $finish;
+ initial begin
+ a = 0;
+ b = 0;
+ #5
+ a = 0;
+ b = 1;
+ #5
+ a = 1;
+ b = 0;
+ #5
+ a = 1;
+ b = 1;
+ #5
+ $finish;
- end
+ end
endmodule
module nor_9bit(
@@ -623,36 +616,37 @@ endmodule
//testbench
module nor_9bit_tb();
-reg [8:0] a;
-reg [8:0] b;
-wire [8:0] c;
+ reg [8:0] a;
+ reg [8:0] b;
+ wire [8:0] c;
-nor_9bit nor0(
-.A(a),
-.B(b),
-.C(c));
+ nor_9bit nor0(
+ .A(a),
+ .B(b),
+ .C(c));
- initial begin
- a = 9'b000000000;
- b = 9'b000000000;
- #5
- a = 9'b000000000;
- b = 9'b000000001;
- #5
- a = 9'b000000001;
- b = 9'b000000000;
- #5
- a = 9'b000000001;
- b = 9'b000000001;
- #5
- a = 9'b000100001;
- b = 9'b000000001;
- #5
- a = 9'b000100001;
- b = 9'b000100001;
- #5 $finish;
+ initial begin
+ a = 9'b000000000;
+ b = 9'b000000000;
+ #5
+ a = 9'b000000000;
+ b = 9'b000000001;
+ #5
+ a = 9'b000000001;
+ b = 9'b000000000;
+ #5
+ a = 9'b000000001;
+ b = 9'b000000001;
+ #5
+ a = 9'b000100001;
+ b = 9'b000000001;
+ #5
+ a = 9'b000100001;
+ b = 9'b000100001;
+ #5
+ $finish;
- end
+ end
endmodule
@@ -666,20 +660,21 @@ endmodule
//testbench
module not_1bit_tb();
-reg a;
-wire b;
+ reg a;
+ wire b;
-not_1bit not0(
-.A(a),
-.B(b));
-
- initial begin
- a = 0;
- #5
- a = 1;
- #5 $finish;
+ not_1bit not0(
+ .A(a),
+ .B(b));
+
+ initial begin
+ a = 0;
+ #5
+ a = 1;
+ #5
+ $finish;
- end
+ end
endmodule
module not_9bit(
@@ -726,31 +721,31 @@ endmodule
//testbench
module not_9bit_tb();
-reg [8:0] a;
-wire [8:0] b;
+ reg [8:0] a;
+ wire [8:0] b;
- not_9bit not0(
- .A(a),
- .B(b));
+ not_9bit not0(
+ .A(a),
+ .B(b));
- initial begin
- a = 9'b000000000;
- #5
- a = 9'b000000001;
- #5
- a = 9'b000111000;
- #5
- a = 9'b010101010;
- #5
- a = 9'b101010101;
- #5
- a = 9'b111111111;
- #5
- a = 9'b100000001;
- #5 $finish;
-
- end
+ initial begin
+ a = 9'b000000000;
+ #5
+ a = 9'b000000001;
+ #5
+ a = 9'b000111000;
+ #5
+ a = 9'b010101010;
+ #5
+ a = 9'b101010101;
+ #5
+ a = 9'b111111111;
+ #5
+ a = 9'b100000001;
+ #5
+ $finish;
+ end
endmodule
module or_1bit(
@@ -764,31 +759,31 @@ endmodule
//testbench
module or_1bit_tb();
-reg a;
-reg b;
-wire c;
+ reg a;
+ reg b;
+ wire c;
- or_1bit or0(
- .A(a),
- .B(b),
- .C(c));
+ or_1bit or0(
+ .A(a),
+ .B(b),
+ .C(c));
- initial begin
- a = 0;
- b = 0;
- #5
- a = 0;
- b = 1;
- #5
- a = 1;
- b = 0;
- #5
- a = 1;
- b = 1;
- #5 $finish;
-
- end
+ initial begin
+ a = 0;
+ b = 0;
+ #5
+ a = 0;
+ b = 1;
+ #5
+ a = 1;
+ b = 0;
+ #5
+ a = 1;
+ b = 1;
+ #5
+ $finish;
+ end
endmodule
module or_9bit(
@@ -845,52 +840,53 @@ endmodule
//testbench
module or_9bit_tb();
-reg [8:0] a;
-reg [8:0] b;
-wire [8:0] c;
+ reg [8:0] a;
+ reg [8:0] b;
+ wire [8:0] c;
- or_9bit tb0(
- .A(a),
- .B(b),
- .C(c));
+ or_9bit tb0(
+ .A(a),
+ .B(b),
+ .C(c));
- initial begin
- a = 9'b000000000;
- b = 9'b000000000;
- #5
- a = 9'b111111111;
- b = 9'b111111111;
- #5
- a = 9'b111111111;
- b = 9'b000000000;
- #5
- a = 9'b000000000;
- b = 9'b111111111;
- #5
- a = 9'b000000000;
- b = 9'b111111111;
- #5
- a = 9'b010101010;
- b = 9'b111111111;
- #5
- a = 9'b010101010;
- b = 9'b101010101;
- #5
- a = 9'b000011111;
- b = 9'b111111111;
- #5
- a = 9'b000000000;
- b = 9'b000010000;
- #5 $finish;
-
- end
+ initial begin
+ a = 9'b000000000;
+ b = 9'b000000000;
+ #5
+ a = 9'b111111111;
+ b = 9'b111111111;
+ #5
+ a = 9'b111111111;
+ b = 9'b000000000;
+ #5
+ a = 9'b000000000;
+ b = 9'b111111111;
+ #5
+ a = 9'b000000000;
+ b = 9'b111111111;
+ #5
+ a = 9'b010101010;
+ b = 9'b111111111;
+ #5
+ a = 9'b010101010;
+ b = 9'b101010101;
+ #5
+ a = 9'b000011111;
+ b = 9'b111111111;
+ #5
+ a = 9'b000000000;
+ b = 9'b000010000;
+ #5
+ $finish;
+ end
endmodule
-module register(input wire clk, reset,
- input wire [1:0] En,
- input wire [8:0] Din,
- output reg [8:0] Dout);
+module register(
+ input wire clk, reset,
+ input wire [1:0] En,
+ input wire [8:0] Din,
+ output reg [8:0] Dout);
always @(posedge clk) begin
if (reset == 1'b1) begin
@@ -903,64 +899,63 @@ module register(input wire clk, reset,
Dout = Dout;
end
end
-
endmodule
//testbench
module register_tb();
-reg clk,reset;
-reg [1:0] En;
-reg [8:0] Din;
-wire [8:0] Dout;
+ reg clk,reset;
+ reg [1:0] En;
+ reg [8:0] Din;
+ wire [8:0] Dout;
- register tb0(
- .clk(clk),
- .reset(reset),
- .En(En),
- .Din(Din),
- .Dout(Dout));
+ register tb0(
+ .clk(clk),
+ .reset(reset),
+ .En(En),
+ .Din(Din),
+ .Dout(Dout));
- initial begin
- clk = 0;
- reset = 0;
- En = 2'b00;
- Din = 9'b000000000;
- #5
- clk = 1;
- #5
- clk = 0;
- reset = 0;
- En = 2'b00;
- Din = 9'b010101010;
- #5
- clk = 1;
- #5
- clk = 0;
- reset = 1;
- En = 2'b00;
- Din = 9'b010101010;
- #5
- clk = 1;
- #5
- clk = 0;
- reset = 0;
- En = 2'b01;
- Din = 9'b101010101;
- #5
- clk = 1;
- #5
- clk = 0;
- reset = 0;
- En = 2'b00;
- Din = 9'b000011111;
- #5
- clk = 1;
- #5
- clk = 0;
- #5 $finish;
-
- end
+ initial begin
+ clk = 0;
+ reset = 0;
+ En = 2'b00;
+ Din = 9'b000000000;
+ #5
+ clk = 1;
+ #5
+ clk = 0;
+ reset = 0;
+ En = 2'b00;
+ Din = 9'b010101010;
+ #5
+ clk = 1;
+ #5
+ clk = 0;
+ reset = 1;
+ En = 2'b00;
+ Din = 9'b010101010;
+ #5
+ clk = 1;
+ #5
+ clk = 0;
+ reset = 0;
+ En = 2'b01;
+ Din = 9'b101010101;
+ #5
+ clk = 1;
+ #5
+ clk = 0;
+ reset = 0;
+ En = 2'b00;
+ Din = 9'b000011111;
+ #5
+ clk = 1;
+ #5
+ clk = 0;
+ #5
+ $finish;
+ end
endmodule
module shift_logical_left(
@@ -973,31 +968,31 @@ endmodule
//testbench
module shift_logical_left_tb();
-reg [8:0] a;
-wire [8:0] b;
+ reg [8:0] a;
+ wire [8:0] b;
- shift_logical_left tb0(
- .A(a),
- .B(b));
+ shift_logical_left tb0(
+ .A(a),
+ .B(b));
- initial begin
- a = 9'b000000000;
- #5
- a = 9'b000000001;
- #5
- a = 9'b000111000;
- #5
- a = 9'b010101010;
- #5
- a = 9'b101010101;
- #5
- a = 9'b111111111;
- #5
- a = 9'b100000001;
- #5 $finish;
-
- end
+ initial begin
+ a = 9'b000000000;
+ #5
+ a = 9'b000000001;
+ #5
+ a = 9'b000111000;
+ #5
+ a = 9'b010101010;
+ #5
+ a = 9'b101010101;
+ #5
+ a = 9'b111111111;
+ #5
+ a = 9'b100000001;
+ #5
+ $finish;
+ end
endmodule
module shift_logical_right(
@@ -1010,31 +1005,31 @@ endmodule
//testbench
module shift_logical_right_tb();
-reg [8:0] a;
-wire [8:0] b;
+ reg [8:0] a;
+ wire [8:0] b;
- shift_logical_right tb0(
- .A(a),
- .B(b));
-
- initial begin
- a = 9'b000000000;
- #5
- a = 9'b000000001;
- #5
- a = 9'b000111000;
- #5
- a = 9'b010101010;
- #5
- a = 9'b101010101;
- #5
- a = 9'b111111111;
- #5
- a = 9'b100000001;
- #5 $finish;
+ shift_logical_right tb0(
+ .A(a),
+ .B(b));
- end
+ initial begin
+ a = 9'b000000000;
+ #5
+ a = 9'b000000001;
+ #5
+ a = 9'b000111000;
+ #5
+ a = 9'b010101010;
+ #5
+ a = 9'b101010101;
+ #5
+ a = 9'b111111111;
+ #5
+ a = 9'b100000001;
+ #5
+ $finish;
+ end
endmodule
module sub_9bit(
@@ -1058,47 +1053,46 @@ endmodule
//testbench
module sub_9bit_tb();
-reg [8:0] a;
-reg [8:0] b;
-wire [8:0] c;
+ reg [8:0] a;
+ reg [8:0] b;
+ wire [8:0] c;
- sub_9bit tb0(
- .A(a),
- .B(b),
- .C(c));
+ sub_9bit tb0(
+ .A(a),
+ .B(b),
+ .C(c));
- initial begin
- a = 9'b000000000;
- b = 9'b000000000;
- #5
- a = 9'b111111111;
- b = 9'b111111111;
- #5
- a = 9'b111111111;
- b = 9'b000000000;
- #5
- a = 9'b000000000;
- b = 9'b111111111;
- #5
- a = 9'b000000000;
- b = 9'b111111111;
- #5
- a = 9'b010101010;
- b = 9'b111111111;
- #5
- a = 9'b010101010;
- b = 9'b101010101;
- #5
- a = 9'b000011111;
- b = 9'b111111111;
- #5
- a = 9'b000000000;
- b = 9'b000010000;
- #5
- $finish;
-
- end
+ initial begin
+ a = 9'b000000000;
+ b = 9'b000000000;
+ #5
+ a = 9'b111111111;
+ b = 9'b111111111;
+ #5
+ a = 9'b111111111;
+ b = 9'b000000000;
+ #5
+ a = 9'b000000000;
+ b = 9'b111111111;
+ #5
+ a = 9'b000000000;
+ b = 9'b111111111;
+ #5
+ a = 9'b010101010;
+ b = 9'b111111111;
+ #5
+ a = 9'b010101010;
+ b = 9'b101010101;
+ #5
+ a = 9'b000011111;
+ b = 9'b111111111;
+ #5
+ a = 9'b000000000;
+ b = 9'b000010000;
+ #5
+ $finish;
+ end
endmodule
module twos_compliment_9bit(
@@ -1121,30 +1115,29 @@ endmodule
//testbench
module twos_compliment_tb();
-reg [8:0] a;
-wire [8:0] b;
+ reg [8:0] a;
+ wire [8:0] b;
- twos_compliment_9bit tb0(
- .A(a),
- .B(b));
+ twos_compliment_9bit tb0(
+ .A(a),
+ .B(b));
- initial begin
- a = 9'b000000000;
- #5
- a = 9'b000000001;
- #5
- a = 9'b000111000;
- #5
- a = 9'b010101010;
- #5
- a = 9'b101010101;
- #5
- a = 9'b111111111;
- #5
- a = 9'b100000001;
- #5
- $finish;
-
- end
+ initial begin
+ a = 9'b000000000;
+ #5
+ a = 9'b000000001;
+ #5
+ a = 9'b000111000;
+ #5
+ a = 9'b010101010;
+ #5
+ a = 9'b101010101;
+ #5
+ a = 9'b111111111;
+ #5
+ a = 9'b100000001;
+ #5
+ $finish;
+ end
endmodule
\ No newline at end of file
diff --git a/lab2CA.srcs/sources_1/new/FetchUnit.v b/lab2CA.srcs/sources_1/new/FetchUnit.v
index a7ccaf9..ac6899c 100644
--- a/lab2CA.srcs/sources_1/new/FetchUnit.v
+++ b/lab2CA.srcs/sources_1/new/FetchUnit.v
@@ -32,12 +32,10 @@ endmodule
//testbench
module fetchUnit_tb();
-reg [8:0] addr_in;
-reg opidx;
-reg reset;
-wire [8:0] addr_out;
+ reg [8:0] addr_in;
+ reg opidx,reset,clk;
+ wire [8:0] addr_out;
- reg clk;
initial begin
clk = 1'b0;
end
@@ -45,48 +43,48 @@ wire [8:0] addr_out;
#5 clk = ~clk; // Period to be determined
end
-FetchUnit fetchUnit0(
-.clk(clk),
-.reset(reset),
-.op_idx(opidx),
-.AddrIn(addr_in),
-.AddrOut(addr_out));
+ FetchUnit tb0(
+ .clk(clk),
+ .reset(reset),
+ .op_idx(opidx),
+ .AddrIn(addr_in),
+ .AddrOut(addr_out));
initial begin
- reset = 0;
- opidx = 1'b1;
- addr_in = 0'b000000000;
- #5
- reset = 1;
- #5
- reset = 0;
- opidx = 1'b0;
- addr_in = 9'b000001111;
- #5
- #5
- addr_in = 9'b011000011;
- #5
- #5
- opidx = 1'b1;
- #5
- #5
- #5
- #5
- opidx = 1'b0;
- addr_in = 9'b000001111;
- #5
- #5
- addr_in = 9'b010010011;
- #5
- opidx = 1'b1;
- #5
- #5
- #5
- #5
- #5
- $finish;
+ reset = 0;
+ opidx = 1'b1;
+ addr_in = 0'b000000000;
+ #5
+ reset = 1;
+ #5
+ reset = 0;
+ opidx = 1'b0;
+ addr_in = 9'b000001111;
+ #5
+ #5
+ addr_in = 9'b011000011;
+ #5
+ #5
+ opidx = 1'b1;
+ #5
+ #5
+ #5
+ #5
+ opidx = 1'b0;
+ addr_in = 9'b000001111;
+ #5
+ #5
+ addr_in = 9'b010010011;
+ #5
+ opidx = 1'b1;
+ #5
+ #5
+ #5
+ #5
+ #5
+ $finish;
end
endmodule
\ No newline at end of file
diff --git a/lab2CA.srcs/sources_1/new/RegFile.v b/lab2CA.srcs/sources_1/new/RegFile.v
index c61c879..fa040dd 100644
--- a/lab2CA.srcs/sources_1/new/RegFile.v
+++ b/lab2CA.srcs/sources_1/new/RegFile.v
@@ -57,12 +57,11 @@ endmodule
//testbench
module regFile_tb();
-reg [8:0] write_d;
-reg [1:0] w_idx, op0_idx, op1_idx;
-reg reset;
-wire [8:0] op0,op1;
+ reg [8:0] write_d;
+ reg [1:0] w_idx, op0_idx, op1_idx;
+ reg reset,clk;
+ wire [8:0] op0,op1;
- reg clk;
initial begin
clk = 1'b0;
end
@@ -70,66 +69,67 @@ wire [8:0] op0,op1;
#5 clk = ~clk; // Period to be determined
end
-RegFile regFile0(
-.clk(clk),
-.reset(reset),
-.write_index(w_idx),
-.op0_idx(op0_idx),
-.op1_idx(op1_idx),
-.write_data(write_d),
-.op0(op0),
-.op1(op1));
+ RegFile regFile0(
+ .clk(clk),
+ .reset(reset),
+ .write_index(w_idx),
+ .op0_idx(op0_idx),
+ .op1_idx(op1_idx),
+ .write_data(write_d),
+ .op0(op0),
+ .op1(op1));
initial begin
- reset = 0;
- #5
- reset = 1;
- #5
- reset = 0;
- w_idx = 2'b00;
- op0_idx = 2'b00;
- op1_idx = 2'b00;
- write_d = 9'b000000011;
- #5
- w_idx = 2'b01;
- #5
- w_idx = 2'b10;
- #5
- w_idx = 2'b11;
- #5
- reset = 0;
- w_idx = 2'b00;
- op0_idx = 2'b10;
- op1_idx = 2'b11;
- write_d = 9'b001111000;
- #5
- reset = 0;
- w_idx = 2'b01;
- op0_idx = 2'b00;
- op1_idx = 2'b01;
- write_d = 9'b000001111;
- #5
- reset = 0;
- w_idx = 2'b10;
- op0_idx = 2'b00;
- op1_idx = 2'b10;
- write_d = 9'b111000001;
- #5
- reset = 0;
- w_idx = 2'b11;
- op0_idx = 2'b11;
- op1_idx = 2'b10;
- write_d = 9'b100110001;
- #5
- reset = 1;
- w_idx = 2'b00;
- #5
- w_idx = 2'b10;
- #5
- w_idx = 2'b01;
- #5
- w_idx = 2'b11;
- #5 $finish;
+ reset = 0;
+ #5
+ reset = 1;
+ #5
+ reset = 0;
+ w_idx = 2'b00;
+ op0_idx = 2'b00;
+ op1_idx = 2'b00;
+ write_d = 9'b000000011;
+ #5
+ w_idx = 2'b01;
+ #5
+ w_idx = 2'b10;
+ #5
+ w_idx = 2'b11;
+ #5
+ reset = 0;
+ w_idx = 2'b00;
+ op0_idx = 2'b10;
+ op1_idx = 2'b11;
+ write_d = 9'b001111000;
+ #5
+ reset = 0;
+ w_idx = 2'b01;
+ op0_idx = 2'b00;
+ op1_idx = 2'b01;
+ write_d = 9'b000001111;
+ #5
+ reset = 0;
+ w_idx = 2'b10;
+ op0_idx = 2'b00;
+ op1_idx = 2'b10;
+ write_d = 9'b111000001;
+ #5
+ reset = 0;
+ w_idx = 2'b11;
+ op0_idx = 2'b11;
+ op1_idx = 2'b10;
+ write_d = 9'b100110001;
+ #5
+ reset = 1;
+ w_idx = 2'b00;
+ #5
+ w_idx = 2'b10;
+ #5
+ w_idx = 2'b01;
+ #5
+ w_idx = 2'b11;
+ #5
+ $finish;
end
endmodule
\ No newline at end of file