diff --git a/lab2CA.srcs/sources_1/new/BasicModules.v b/lab2CA.srcs/sources_1/new/BasicModules.v
index e9c85c5..d3660e4 100644
--- a/lab2CA.srcs/sources_1/new/BasicModules.v
+++ b/lab2CA.srcs/sources_1/new/BasicModules.v
@@ -1055,12 +1055,9 @@ endmodule
 
 module zero(
     input wire [8:0] A,
-    output reg [8:0] B);
+    output wire [8:0] B);
     
-    always @(A) begin
-        if(A == 9'b000000000)
-            B = 9'b000000001;  // 1 if A is zero
-        else
-            B = 9'b000000000;  // 0 if A is non-zero
-    end
+    assign B = {8'b00000000, A[8] | A[7] | A[6] | A[5] | A[4] | A[3] | A[2] | A[1] | A[0]};
+    // 0 if zero
+    // 1 if non-zero
 endmodule
\ No newline at end of file