From 21e846ab6291ba16015ddbba77fa9461f4eb5f10 Mon Sep 17 00:00:00 2001 From: Johannes Date: Sat, 16 Mar 2019 14:16:02 -0400 Subject: [PATCH] Instruction & Data Memory --- lab2CA.sim/sim_1/behav/xsim/dataMemory_tb.tcl | 11 ++ .../sim_1/behav/xsim/dataMemory_tb_vlog.prj | 9 ++ .../sim_1/behav/xsim/instructionMemory_tb.tcl | 11 ++ .../behav/xsim/instructionMemory_tb_vlog.prj | 9 ++ .../sim_1/behav/xsim/webtalk_11840.backup.jou | 12 -- .../sim_1/behav/xsim/webtalk_13852.backup.jou | 12 ++ .../sim_1/behav/xsim/webtalk_14548.backup.jou | 12 ++ .../sim_1/behav/xsim/webtalk_14664.backup.jou | 12 -- .../sim_1/behav/xsim/webtalk_17516.backup.jou | 12 -- .../sim_1/behav/xsim/webtalk_7732.backup.jou | 12 ++ lab2CA.sim/sim_1/behav/xsim/xelab.pb | Bin 4041 -> 1557 bytes .../dataMemory_tb_behav/Compile_Options.txt | 1 + .../TempBreakPointFile.txt | 1 + .../xsim.dir/dataMemory_tb_behav/obj/xsim_1.c | 113 ++++++++++++++++++ .../webtalk/usage_statistics_ext_xsim.xml | 44 +++++++ .../webtalk/xsim_webtalk.tcl | 42 +++++++ .../xsim.dir/dataMemory_tb_behav/xsim.mem | Bin 0 -> 3347 bytes .../Compile_Options.txt | 1 + .../TempBreakPointFile.txt | 1 + .../instructionMemory_tb_behav/obj/xsim_1.c | 111 +++++++++++++++++ .../webtalk/usage_statistics_ext_xsim.xml | 44 +++++++ .../webtalk/xsim_webtalk.tcl | 32 +++++ .../instructionMemory_tb_behav/xsim.mem | Bin 0 -> 3086 bytes lab2CA.sim/sim_1/behav/xsim/xvlog.pb | Bin 6158 -> 444 bytes lab2CA.srcs/sources_1/new/dataMemory.v | 89 ++++++++++++++ lab2CA.srcs/sources_1/new/instructionMemory.v | 64 ++++++++++ lab2CA.xpr | 28 +++-- 27 files changed, 638 insertions(+), 45 deletions(-) create mode 100644 lab2CA.sim/sim_1/behav/xsim/dataMemory_tb.tcl create mode 100644 lab2CA.sim/sim_1/behav/xsim/dataMemory_tb_vlog.prj create mode 100644 lab2CA.sim/sim_1/behav/xsim/instructionMemory_tb.tcl create mode 100644 lab2CA.sim/sim_1/behav/xsim/instructionMemory_tb_vlog.prj delete mode 100644 lab2CA.sim/sim_1/behav/xsim/webtalk_11840.backup.jou create mode 100644 lab2CA.sim/sim_1/behav/xsim/webtalk_13852.backup.jou create mode 100644 lab2CA.sim/sim_1/behav/xsim/webtalk_14548.backup.jou delete mode 100644 lab2CA.sim/sim_1/behav/xsim/webtalk_14664.backup.jou delete mode 100644 lab2CA.sim/sim_1/behav/xsim/webtalk_17516.backup.jou create mode 100644 lab2CA.sim/sim_1/behav/xsim/webtalk_7732.backup.jou create mode 100644 lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/Compile_Options.txt create mode 100644 lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/TempBreakPointFile.txt create mode 100644 lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/obj/xsim_1.c create mode 100644 lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/usage_statistics_ext_xsim.xml create mode 100644 lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/xsim_webtalk.tcl create mode 100644 lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/xsim.mem create mode 100644 lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/Compile_Options.txt create mode 100644 lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/TempBreakPointFile.txt create mode 100644 lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/obj/xsim_1.c create mode 100644 lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/usage_statistics_ext_xsim.xml create mode 100644 lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/xsim_webtalk.tcl create mode 100644 lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/xsim.mem create mode 100644 lab2CA.srcs/sources_1/new/dataMemory.v create mode 100644 lab2CA.srcs/sources_1/new/instructionMemory.v diff --git a/lab2CA.sim/sim_1/behav/xsim/dataMemory_tb.tcl b/lab2CA.sim/sim_1/behav/xsim/dataMemory_tb.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/dataMemory_tb.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/lab2CA.sim/sim_1/behav/xsim/dataMemory_tb_vlog.prj b/lab2CA.sim/sim_1/behav/xsim/dataMemory_tb_vlog.prj new file mode 100644 index 0000000..6ce9816 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/dataMemory_tb_vlog.prj @@ -0,0 +1,9 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../lab2CA.srcs/sources_1/new/dataMemory.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/lab2CA.sim/sim_1/behav/xsim/instructionMemory_tb.tcl b/lab2CA.sim/sim_1/behav/xsim/instructionMemory_tb.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/instructionMemory_tb.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/lab2CA.sim/sim_1/behav/xsim/instructionMemory_tb_vlog.prj b/lab2CA.sim/sim_1/behav/xsim/instructionMemory_tb_vlog.prj new file mode 100644 index 0000000..39dded0 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/instructionMemory_tb_vlog.prj @@ -0,0 +1,9 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../lab2CA.srcs/sources_1/new/instructionMemory.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_11840.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_11840.backup.jou deleted file mode 100644 index 9701998..0000000 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk_11840.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Wed Mar 13 11:21:51 2019 -# Process ID: 11840 -# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim -# Command line: wbtcv.exe -mode batch -source C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log -# Journal file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou -#----------------------------------------------------------- -source C:/Users/JoseIgnacio/CA -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_13852.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_13852.backup.jou new file mode 100644 index 0000000..4baee94 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk_13852.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.3 (64-bit) +# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 +# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 +# Start of session at: Sat Mar 16 14:03:44 2019 +# Process ID: 13852 +# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_14548.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_14548.backup.jou new file mode 100644 index 0000000..39026d0 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk_14548.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.3 (64-bit) +# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 +# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 +# Start of session at: Sat Mar 16 13:13:49 2019 +# Process ID: 14548 +# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_14664.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_14664.backup.jou deleted file mode 100644 index eb52ade..0000000 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk_14664.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Thu Mar 14 14:24:20 2019 -# Process ID: 14664 -# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim -# Command line: wbtcv.exe -mode batch -source C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log -# Journal file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou -#----------------------------------------------------------- -source C:/Users/JoseIgnacio/CA -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_17516.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_17516.backup.jou deleted file mode 100644 index 44e0014..0000000 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk_17516.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Thu Mar 14 14:23:56 2019 -# Process ID: 17516 -# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim -# Command line: wbtcv.exe -mode batch -source C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log -# Journal file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou -#----------------------------------------------------------- -source C:/Users/JoseIgnacio/CA -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_7732.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_7732.backup.jou new file mode 100644 index 0000000..3049660 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk_7732.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.3 (64-bit) +# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 +# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 +# Start of session at: Sat Mar 16 13:12:04 2019 +# Process ID: 7732 +# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/xelab.pb b/lab2CA.sim/sim_1/behav/xsim/xelab.pb index be22fea731f7e0551095817b1e5107eb32b7e994..6257e152722a69e8fd79468b839a1b46e56825e2 100644 GIT binary patch delta 148 zcmX>pKb2>~3&yV#Un;R2VB%UmnV<0rS4v_@qHk($eo^J**Nl>U2yT2ylEP#`e&Nl^ zOxjG74Y;h4l`iDbV9c5PkwZh?kW02AGbcVJH7&6;rz9scNe{({$v~BppYo*xRr~TA P@v3tPBcvyH@!JCcv0OBf literal 4041 zcmcgv?QYvP6m34xqC`<-=!SGz3lLbd7F%rV%eItXYm62c&<$If6vO@qltf$XXi_67 z+j)z=#a?1B)i)UBuQE!#(GZYdG9~$(d(OSQx&#c|J(loTf`k2|y})(8zc0zSq)2h$ zJp%{t$OL5^zFptDm*F8QsXAT#@Q%P;&vC=H@2zgFpZ#$!@LPV=@8@@l{n`G9ojV7+ z;4iQ@r!$!@z>fo7TnRGD6?CJp*K(sMI)R?!xUC8u{!S=ivlI9eOWW`zrSQCZSHg2F zv6$ejeUsfJ{kRJroR^FdHacCY^?l!r;h$ab_wL}dvta5hly?@=ItgK&l1&9F3Y>MO zg!O_p@60eoNgK~FY)uu14(f)EkB1owg23q}i5DixFz^%Pc{p@J*lH1$3Vq3NQjVay zDoBc`UJDI0)7P(S|GD?V&u}b0u=V($xZyPVvAB||D!=rozE2Uf@h1=EYrrC>B2SH@IegO_I zrM6r<4kbks3{@^L$`;k;_xq;*Ux6KOBW~oIxM$$WTZM$Gprt~Jr0e(yXY*3_1J3|o zM%N8ZlmU1;;NyZ~g|kgCUTE%!1&kl{Oqid+^H0Gn_K6MxW=J78qf95!e4Bdj04Iq91k55HoOmLB_b+ES#3A3U9~-T<-L0N!C5U4*~E8d4>hp#1wU}RlvxW=>$Bk zF$p{(QrS~A5H&7maS*$r`%sp}uI?wdL{+seTdD^BRhjbaGnLzx zUkiL)E5FxRrTHbZSJfa_jH`GX1EsC35In2NQd2JDv}&ii(Xj1k8z_`zvX#OHCBns4 zObtY_+oM7(+e#I&t&lc2s#S>0$xy`<53TpJuqEq*Z$C>mpC@BIuvBA~Z5JtRSx>=t z|G|m`QTZ6_*~FH(K~tev>iI55%$6&$75N-Is);;%^_wkAgFR3+WVdJEksAnl`R3AA z(0g0kI^dg{Z3E7f;B=eL|EDdR1D@2_^jFi3xBRFz$kyrzaT`8 +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_2(char*, char *); +extern void execute_3(char*, char *); +extern void execute_7(char*, char *); +extern void execute_12(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void execute_15(char*, char *); +extern void execute_16(char*, char *); +extern void execute_5(char*, char *); +extern void execute_6(char*, char *); +extern void execute_9(char*, char *); +extern void execute_10(char*, char *); +extern void execute_11(char*, char *); +extern void execute_17(char*, char *); +extern void execute_18(char*, char *); +extern void execute_19(char*, char *); +extern void execute_20(char*, char *); +extern void execute_21(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[19] = {(funcp)execute_2, (funcp)execute_3, (funcp)execute_7, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)execute_5, (funcp)execute_6, (funcp)execute_9, (funcp)execute_10, (funcp)execute_11, (funcp)execute_17, (funcp)execute_18, (funcp)execute_19, (funcp)execute_20, (funcp)execute_21, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 19; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/dataMemory_tb_behav/xsim.reloc", (void **)funcTab, 19); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/dataMemory_tb_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/dataMemory_tb_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/dataMemory_tb_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/dataMemory_tb_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/dataMemory_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/usage_statistics_ext_xsim.xml b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000..97e005a --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,44 @@ + + +
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+ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/xsim_webtalk.tcl b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/xsim_webtalk.tcl new file mode 100644 index 0000000..d0ac3c8 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/xsim_webtalk.tcl @@ -0,0 +1,42 @@ +webtalk_init -webtalk_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/ +webtalk_register_client -client project +webtalk_add_data -client project -key date_generated -value "Sat Mar 16 14:13:55 2019" -context "software_version_and_target_device" +webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device" +webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "174150793_174150794_210688225_140" -context "software_version_and_target_device" +webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" +webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "4e917e26-7591-4435-9135-15bd446b0238" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "18" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" +webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) CPU E5-1620 v3 @ 3.50GHz" -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "3492 MHz" -context "user_environment" +webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "34.000 GB" -context "user_environment" +webtalk_register_client -client xsim +webtalk_add_data -client xsim -key File_Counter -value "2" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key Command -value "xelab" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key Vhdl2008 -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key GenDLL -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key SDFModeling -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key HWCosim -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key DPI_Used -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key Debug -value "typical" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key Simulation_Image_Code -value "69 KB" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Image_Data -value "3 KB" -context "xsim\\usage" +webtalk_add_data -client xsim -key Total_Nets -value "0" -context "xsim\\usage" +webtalk_add_data -client xsim -key Total_Processes -value "24" -context "xsim\\usage" +webtalk_add_data -client xsim -key Total_Instances -value "3" -context "xsim\\usage" +webtalk_add_data -client xsim -key Xilinx_HDL_Libraries_Used -value "secureip unimacro_ver unisims_ver " -context "xsim\\usage" +webtalk_add_data -client xsim -key Compiler_Time -value "0.73_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Compiler_Memory -value "38176_KB" -context "xsim\\usage" +webtalk_transmit -clientid 198226099 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_terminate diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/xsim.mem b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/xsim.mem new file mode 100644 index 0000000000000000000000000000000000000000..709b631a8947bc691c12e6d17db3518853986daf GIT binary patch literal 3347 zcmeH{cTm&W7RQld6cn&g6mVG>Sc3{Epa>)@DDd!&Q9|1wMByoxeIin%CJ+!Th)7YC z@&l132?!ySAStu}0+Av}4NdYOgb+eYNXQGT&b)p9>_7XbcjnAF=iYP9-1*+mTq&tP zuaCce&0D_tNb5hJ|HytQ@I!$g3j9#u?^Pf}EEaFt_o>p~gKu70UrGujiB%=G^gng~ zSN4}_%(wqsRWdAi3mf77`(9@?NJYTKiwd4xPc8<-o(u4mJL|Bm@Zsm{6S?Y@0q_Iv zDzzVubiIKsUfY%0Y%kpfTBe$CTlG(KRrcVx(t>N@<7JkKm&2)IfQPOX@2CyP#wX2Y z{3~>WPvQu9ndr{;&bhv{bGMkzJvv(q^%5tGi;%j~v%6-sqtqtp$w^iGN(4kc;ON*w zYh3+!A=%;9fhM(5nrZjhro^XVR$GJj0PnDIvR?7xs)(a0Jgvn6m0vugHGA;`0-?pH z%NJw|pTCek0_tRvf%aKm_4Q{p&R-|o@GuZ%-H1Z6tsLU{{-w*5}zq8u%@48z&85y-0g!vlhz$s zoO9tScc9&@WUc%cCQzH_R3g(abnepRD{f2wf8O)b?oTH(U>^&!cqr)UlER4IP(4Vl zv&l^>rNV%KZsvQFfYHY^;qSO4WtNe1VdNzQC2KmuV2B z2QxpF@_GKoII^le9ly}Oc_FO!L2pc@S+c_nou`B%1U6DBRL((oAh|*JEq|ZJWqGOYbAXES*;XOkryEr|~sQBmFsltV3#yu~RmA zNY6a048Wf&nvdH?%rb)*+TKx|ycNDmc%p;SvtFO3jR~Y^r%-06Ep~TDd22#-vf0~b zC}p>|pXpVK2^e!L5EuD5+k+AU1yvcmaGbWbVK z=r*RUx`Z22Rxb_TgX+DXUJy-@irdm+{vnqnuPcFX0a{Gy>K7J74Pv2e!gyyDd)*nB zIR+><(w~qV7X~BUFoOl5sT; za@sxp2CTK1h<>004223TmOvW9d?f_gd@<~KFbcVZmrwBHEV~%}Q)o!=&Z~7KM1{-i3}!wn$KcASe^|%I zK9i*Cl754l<2MYwW9>k8)Gv#kihdB*mt8(#b(lB)hmg&d@V5}x{YPEEIt>$1{! z{;W>#kb8z@PRl%SUl_&=RCI=r9QT)=%wy+uO=ROkdZzzbk~oig +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_2(char*, char *); +extern void execute_3(char*, char *); +extern void execute_7(char*, char *); +extern void execute_12(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void execute_5(char*, char *); +extern void execute_6(char*, char *); +extern void execute_9(char*, char *); +extern void execute_10(char*, char *); +extern void execute_11(char*, char *); +extern void execute_15(char*, char *); +extern void execute_16(char*, char *); +extern void execute_17(char*, char *); +extern void execute_18(char*, char *); +extern void execute_19(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[17] = {(funcp)execute_2, (funcp)execute_3, (funcp)execute_7, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)execute_5, (funcp)execute_6, (funcp)execute_9, (funcp)execute_10, (funcp)execute_11, (funcp)execute_15, (funcp)execute_16, (funcp)execute_17, (funcp)execute_18, (funcp)execute_19, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 17; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/instructionMemory_tb_behav/xsim.reloc", (void **)funcTab, 17); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/instructionMemory_tb_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/instructionMemory_tb_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/instructionMemory_tb_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/instructionMemory_tb_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/instructionMemory_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/usage_statistics_ext_xsim.xml b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000..0922624 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,44 @@ + + +
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+ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/xsim_webtalk.tcl b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/xsim_webtalk.tcl new file mode 100644 index 0000000..b491427 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/xsim_webtalk.tcl @@ -0,0 +1,32 @@ +webtalk_init -webtalk_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/ +webtalk_register_client -client project +webtalk_add_data -client project -key date_generated -value "Sat Mar 16 13:18:24 2019" -context "software_version_and_target_device" +webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device" +webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "174150793_174150794_210688225_140" -context "software_version_and_target_device" +webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" +webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "4e917e26-7591-4435-9135-15bd446b0238" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "4" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" +webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) CPU E5-1620 v3 @ 3.50GHz" -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "3492 MHz" -context "user_environment" +webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "34.000 GB" -context "user_environment" +webtalk_register_client -client xsim +webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" +webtalk_add_data -client xsim -key runtime -value "40 ns" -context "xsim\\usage" +webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Time -value "0.06_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Memory -value "6108_KB" -context "xsim\\usage" +webtalk_transmit -clientid 3866550317 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


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+ + reg [8:0] memory [15:0]; + + initial begin + memory[0] <= 9'b000000000; + memory[1] <= 9'b000000000; + memory[2] <= 9'b000000000; + memory[3] <= 9'b000000000; + memory[4] <= 9'b000000000; + memory[5] <= 9'b000000000; + memory[6] <= 9'b000000000; + memory[7] <= 9'b000000000; + memory[8] <= 9'b000000000; + memory[9] <= 9'b000000000; + memory[10] <= 9'b000000000; + memory[11] <= 9'b000000000; + memory[12] <= 9'b000000000; + memory[13] <= 9'b000000000; + memory[14] <= 9'b000000000; + memory[15] <= 9'b000000000; + end + + always@(address, posedge clk)begin + if(clk == 1'b1)begin + readData <= memory[address]; + if(writeEnable == 1'b1)begin + memory[address] <= writeData; + end + else begin + memory[address] <= memory[address]; + end + end + end +endmodule + +module dataMemory_tb(); + reg clk, writeEnable; + reg [8:0] address, writeData; + wire [8:0] readData; + + initial begin + clk = 1'b0; + end + always begin + #5 clk = ~clk; // Period to be determined + end + + dataMemory dM0( + .clk(clk), + .writeEnable(writeEnable), + .writeData(writeData), + .address(address), + .readData(readData) + ); + + initial begin + writeEnable = 1'b0; + address = 9'b000000000; + writeData = 9'b010101010; + #5 + address = 9'b000000100; + writeData = 9'b010101010; + #10 + writeEnable = 1'b1; + address = 9'b000000000; + writeData = 9'b010101010; + #10 + address = 9'b000000001; + writeData = 9'b000001111; + #10 + address = 9'b000000010; + writeData = 9'b000000101; + #10 + address = 9'b000000011; + writeData = 9'b000000011; + #10 + address = 9'b00000010; + writeData = 9'b000001101; + #5 + $finish; + end +endmodule \ No newline at end of file diff --git a/lab2CA.srcs/sources_1/new/instructionMemory.v b/lab2CA.srcs/sources_1/new/instructionMemory.v new file mode 100644 index 0000000..a766dce --- /dev/null +++ b/lab2CA.srcs/sources_1/new/instructionMemory.v @@ -0,0 +1,64 @@ +`timescale 1ns / 1ps + +module instructionMemory( + input wire clk, + input wire [8:0] address, + output reg [8:0] readData + ); + + reg [8:0] memory [512:0]; + + initial begin + //Equation Solver + memory[0] <= 9'b000100000; + memory[1] <= 9'b000101000; + memory[2] <= 9'b010100010; + memory[3] <= 9'b111100000; + memory[4] <= 9'b111100000; + memory[5] <= 9'b000000000; + end + + + always@(address, posedge clk)begin + readData <= memory[address]; + end +endmodule + + +module instructionMemory_tb(); + reg clk; + reg [8:0] address; + wire [8:0] readData; + + initial begin + clk = 1'b0; + end + always begin + #5 clk = ~clk; // Period to be determined + end + + instructionMemory iM0( + .clk(clk), + .address(address), + .readData(readData) + ); + + initial begin + #10 + address = 9'b000000000; + #5 + address = 9'b000000001; + #5 + address = 9'b000000010; + #5 + address = 9'b000000011; + #5 + address = 9'b000000100; + #5 + address = 9'b000000101; + #5 + address = 9'b000000111; + #5 + $finish; + end +endmodule \ No newline at end of file diff --git a/lab2CA.xpr b/lab2CA.xpr index 7550d07..9a01217 100644 --- a/lab2CA.xpr +++ b/lab2CA.xpr @@ -3,7 +3,7 @@ - +