Merge branch 'master' of https://git.williammiceli.systems/williammiceli-wmu/ece3570-lab2

# Conflicts:
#	lab2CA.cache/wt/webtalk_pa.xml
#	lab2CA.srcs/sources_1/new/BasicModules.v

lab2CA.srcs/sources_1/new/BasicModules.v

@@ -164,9 +164,26 @@ module gen_clock();
     end
 endmodule
 
+<<<<<<< HEAD
 <<<<<<< HEAD
 //To enable register, input 00 to En, register is always outputting contents
 =======
+=======
+module mux_2_1(input wire switch,
+           input wire [8:0] A,B,
+           output reg [8:0] out);
+           
+    always @(A,B,switch) begin
+        case (switch)
+            2'b00 : out = A;
+            2'b01 : out = B;
+            default : out = 9'bxxxxxxxxx;
+        endcase
+    end
+
+endmodule
+
+>>>>>>> b2eb0da26cf8a205e02981e2a7c6a774e8d18e02
 module mux_4_1(input wire [1:0] switch,
            input wire [8:0] A,B,C,D,
            output reg [8:0] out);