Formatted things to look a little nicer

lab2CA.srcs/sources_1/new/CPU9bits.v

@@ -14,7 +14,7 @@ module CPU9bits(
     instructionMemory iM(
         .address(PCout),
         .readData(instr)
-        );
+    );
     
     dataMemory dM(
         .clk(clk),
@@ -22,7 +22,7 @@ module CPU9bits(
         .writeData(op0),
         .address(op1),
         .readData(dataMemOut)
-        );    
+    );    
           
     RegFile RF(
         .clk(clk),
@@ -54,16 +54,16 @@ module CPU9bits(
         .op_idx(fetchBranch),
         .AddrIn(FUAddr),
         .AddrOut(PCout)
-     );
+    );
      
-     ALU alu(
+    ALU alu(
         .opcode(aluOp),
         .operand0(op0),
         .operand1(op1),
         .result(AluOut)     
-     );
+    );
      
-     ControlUnit CU(
+    ControlUnit CU(
         .instIn(instr[8:5]),
         .functBit(instr[0]),
         .aluOut(aluOp),
@@ -76,50 +76,56 @@ module CPU9bits(
         .link(link),
         .bank(bankS),
         .js(js)
-     );
+    );
      
      
      //-----------------------Fetch Unit Stuff
      
-     add_9bit JBAdder(
+    add_9bit JBAdder(
         .A(PCout),
         .B(JBRes),
         .Cin(1'b0),
         .Sum(FUJB),
-        .Cout(cout0));
+        .Cout(cout0)
+    );
         
     mux_2_1 mux0(
         .A(op0),
         .B(FUJB),
         .out(FUAddr),
-        .switch(FU[1]));
+        .switch(FU[1])
+    );
         
-   twos_compliment_9bit two_comp0(
+    twos_compliment_9bit two_comp0(
         .A({4'b0000,instr[4:0]}),
-        .B(jumpNeg));
+        .B(jumpNeg)
+    );
     
     mux_2_1 mux1(
         .A({4'b0000,instr[4:0]}),
         .B(jumpNeg),
         .out(SE2N),
-        .switch(js));
+        .switch(js)
-        
+    );
         
     mux_2_1 mux2(
         .A(SE2N), //Jump -- Change with signer module!
         .B(SE1N),//Branch -- Change with signer module!
         .out(JBRes),
-        .switch(FU[2]));
+        .switch(FU[2])
+    );
         
     sign_extend_3bit SE1(
         .A(instr[2:0]),
-        .B(SE1N));
+        .B(SE1N)
+    );
             
     bit1_mux_2_1 BranMux( // BEQ MUX
         .A(FU[0]),
         .B(AluOut[0]),
         .out(fetchBranch),
-        .switch(FU[2])); // FU[2] only goes high when BEQ
+        .switch(FU[2]) // FU[2] only goes high when BEQ
+    );
         
     ///--------------------------Addi Stuff
         
@@ -128,26 +134,29 @@ module CPU9bits(
         .B(op0),
         .Cin(1'b0),
         .Sum(AddiOut),
-        .Cout(cout1));
+        .Cout(cout1)
+    );
     
     sign_extend_3bit SE3(
         .A(instr[2:0]),
-        .B(SE3N));
+        .B(SE3N)
+    );
         
     mux_2_1 mux3(
         .A(AluOut),
         .B(AddiOut),
         .out(loadMux),
-        .switch(addiS));
+        .switch(addiS)
-        
+    );
-        
+    
     ///--------------------------Mem stuff
-        
+
     mux_2_1 mux4(
         .A(linkData),
         .B(dataMemOut), // This is DATA MEM
         .out(bankData),
-        .switch(loadS));
+        .switch(loadS)
+    );
         
     ///--------------------------Bank stuff
         
@@ -155,7 +164,8 @@ module CPU9bits(
         .A(bankData),
         .B(bankOP), 
         .out(RFIn),
-        .switch(bankS[0]));
+        .switch(bankS[0])
+    );
         
     ///--------------------------Link Stuff
     
@@ -163,7 +173,8 @@ module CPU9bits(
         .A(loadMux),
         .B(PCout),
         .out(linkData),
-        .switch(link));
+        .switch(link)
+    );
      
          
 endmodule
@@ -171,13 +182,9 @@ endmodule
 module CPU9bits_tb();
     reg clk, reset;
     wire done;
-    
+
-    initial begin
+    always
-        clk = 1'b0;
-    end
-    always begin
         #5 clk = ~clk; // Period to be determined
-    end
 
     CPU9bits CPU9bits0(
         .reset(reset),
@@ -185,6 +192,7 @@ module CPU9bits_tb();
         .done(done));
         
     initial begin
+        clk = 1'b0;
         #5
         reset = 1'b1;
         #10