From 2a84458894cf530bf3e7f064ab7cff486a2f516b Mon Sep 17 00:00:00 2001 From: WilliamMiceli Date: Fri, 15 Feb 2019 15:07:25 -0500 Subject: [PATCH] Added 9-bit adder --- lab2CA.srcs/sources_1/new/BasicModules.v | 81 ++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/lab2CA.srcs/sources_1/new/BasicModules.v b/lab2CA.srcs/sources_1/new/BasicModules.v index a4bed4b..4997250 100644 --- a/lab2CA.srcs/sources_1/new/BasicModules.v +++ b/lab2CA.srcs/sources_1/new/BasicModules.v @@ -12,6 +12,87 @@ module adder_1bit( endmodule +module adder_9bit( + input wire [8:0] A, + input wire [8:0] B, + input wire Cin, + output wire [8:0] Sum, + output wire Cout); + + wire C_add0; + wire C_add1; + wire C_add2; + wire C_add3; + wire C_add4; + wire C_add5; + wire C_add6; + wire C_add7; + + adder_1bit add0( + .A(A[0]) + .B(B[0]) + .Cin(Cin) + .S(Sum[0]) + .Cout(C_add0)); + + adder_1bit add1( + .A(A[0]) + .B(B[0]) + .Cin(C_add0) + .S(Sum[0]) + .Cout(C_add1)); + + adder_1bit add2( + .A(A[0]) + .B(B[0]) + .Cin(C_add1) + .S(Sum[0]) + .Cout(C_add2)); + + adder_1bit add3( + .A(A[0]) + .B(B[0]) + .Cin(C_add2) + .S(Sum[0]) + .Cout(C_add3)); + + adder_1bit add4( + .A(A[0]) + .B(B[0]) + .Cin(C_add3) + .S(Sum[0]) + .Cout(C_add4)); + + adder_1bit add5( + .A(A[0]) + .B(B[0]) + .Cin(C_add4) + .S(Sum[0]) + .Cout(C_add5)); + + adder_1bit add6( + .A(A[0]) + .B(B[0]) + .Cin(C_add5) + .S(Sum[0]) + .Cout(C_add6)); + + adder_1bit add7( + .A(A[0]) + .B(B[0]) + .Cin(C_add6) + .S(Sum[0]) + .Cout(C_add7)); + + adder_1bit add8( + .A(A[0]) + .B(B[0]) + .Cin(C_add7) + .S(Sum[0]) + .Cout(Cout)); + +endmodule + module and_gate( input wire A, input wire B,