diff --git a/Bank_behav1.wcfg b/Bank_behav1.wcfg index 234d01c..123f0ad 100644 --- a/Bank_behav1.wcfg +++ b/Bank_behav1.wcfg @@ -11,13 +11,13 @@ - - - + + + - + diff --git a/lab2CA.runs/impl_1/gen_run.xml b/lab2CA.runs/impl_1/gen_run.xml index 2c0c43a..063b89e 100644 --- a/lab2CA.runs/impl_1/gen_run.xml +++ b/lab2CA.runs/impl_1/gen_run.xml @@ -1,14 +1,14 @@ + - + - - + @@ -18,12 +18,12 @@ - - + - + + @@ -31,8 +31,8 @@ - + diff --git a/lab2CA.sim/sim_1/behav/xsim/xelab.pb b/lab2CA.sim/sim_1/behav/xsim/xelab.pb index 175ab93..3887e53 100644 Binary files a/lab2CA.sim/sim_1/behav/xsim/xelab.pb and b/lab2CA.sim/sim_1/behav/xsim/xelab.pb differ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl index 41c6e18..ce99532 100644 --- a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl @@ -1,10 +1,10 @@ -webtalk_init -webtalk_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/ +webtalk_init -webtalk_dir C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/ webtalk_register_client -client project -webtalk_add_data -client project -key date_generated -value "Sun Mar 24 16:09:25 2019" -context "software_version_and_target_device" +webtalk_add_data -client project -key date_generated -value "Sun Mar 24 16:34:26 2019" -context "software_version_and_target_device" webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device" webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device" webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" -webtalk_add_data -client project -key registration_id -value "174150793_174150794_210688225_140" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" @@ -12,21 +12,31 @@ webtalk_add_data -client project -key target_family -value "not_applicable" -con webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" -webtalk_add_data -client project -key random_id -value "4e917e26-7591-4435-9135-15bd446b0238" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "17336daf-0d92-4f07-b4a4-ff1c52043edb" -context "software_version_and_target_device" webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device" -webtalk_add_data -client project -key project_iteration -value "97" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "82" -context "software_version_and_target_device" webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" -webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) CPU E5-1620 v3 @ 3.50GHz" -context "user_environment" -webtalk_add_data -client project -key cpu_speed -value "3492 MHz" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i5-3230M CPU @ 2.60GHz" -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "2594 MHz" -context "user_environment" webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" -webtalk_add_data -client project -key system_ram -value "34.000 GB" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "8.000 GB" -context "user_environment" webtalk_register_client -client xsim -webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" -webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" -webtalk_add_data -client xsim -key runtime -value "520 ns" -context "xsim\\usage" -webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage" -webtalk_add_data -client xsim -key Simulation_Time -value "0.03_sec" -context "xsim\\usage" -webtalk_add_data -client xsim -key Simulation_Memory -value "6444_KB" -context "xsim\\usage" -webtalk_transmit -clientid 1317412355 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_add_data -client xsim -key File_Counter -value "9" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key Command -value "xelab" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key Vhdl2008 -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key GenDLL -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key SDFModeling -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key HWCosim -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key DPI_Used -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key Debug -value "typical" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key Simulation_Image_Code -value "109 KB" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Image_Data -value "19 KB" -context "xsim\\usage" +webtalk_add_data -client xsim -key Total_Nets -value "0" -context "xsim\\usage" +webtalk_add_data -client xsim -key Total_Processes -value "281" -context "xsim\\usage" +webtalk_add_data -client xsim -key Total_Instances -value "144" -context "xsim\\usage" +webtalk_add_data -client xsim -key Xilinx_HDL_Libraries_Used -value "secureip unimacro_ver unisims_ver " -context "xsim\\usage" +webtalk_add_data -client xsim -key Compiler_Time -value "1.19_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Compiler_Memory -value "49056_KB" -context "xsim\\usage" +webtalk_transmit -clientid 4125363012 -regid "" -xml C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" webtalk_terminate diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem index 32c1368..e0224a8 100644 Binary files a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem and b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem differ diff --git a/lab2CA.sim/sim_1/behav/xsim/xvlog.pb b/lab2CA.sim/sim_1/behav/xsim/xvlog.pb index e201557..b4146de 100644 Binary files a/lab2CA.sim/sim_1/behav/xsim/xvlog.pb and b/lab2CA.sim/sim_1/behav/xsim/xvlog.pb differ diff --git a/lab2CA.srcs/sources_1/new/dataMemory.v b/lab2CA.srcs/sources_1/new/dataMemory.v index b9c116e..d88881c 100644 --- a/lab2CA.srcs/sources_1/new/dataMemory.v +++ b/lab2CA.srcs/sources_1/new/dataMemory.v @@ -9,23 +9,46 @@ module dataMemory( reg [8:0] memory [15:0]; initial begin - // String Compare Memory - memory[0] <= 9'b000000100; - memory[1] <= 9'b000001000; - memory[2] <= 9'b000001100; - memory[3] <= 9'b010101010; - memory[4] <= 9'b000001111; - memory[5] <= 9'b000000100; - memory[6] <= 9'b000000011; - memory[7] <= 9'b000000000; - memory[8] <= 9'b000001111; - memory[9] <= 9'b000000100; - memory[10] <= 9'b000000010; - memory[11] <= 9'b000000000; - memory[12] <= 9'b000000000; - memory[13] <= 9'b000000000; - memory[14] <= 9'b000000000; - memory[15] <= 9'b000000000; +// // String Compare Memory +// memory[0] <= 9'b000000100; +// memory[1] <= 9'b000001000; +// memory[2] <= 9'b000001100; +// memory[3] <= 9'b010101010; +// memory[4] <= 9'b000001111; +// memory[5] <= 9'b000000100; +// memory[6] <= 9'b000000011; +// memory[7] <= 9'b000000000; +// memory[8] <= 9'b000001111; +// memory[9] <= 9'b000000100; +// memory[10] <= 9'b000000010; +// memory[11] <= 9'b000000000; +// memory[12] <= 9'b000000000; +// memory[13] <= 9'b000000000; +// memory[14] <= 9'b000000000; +// memory[15] <= 9'b000000000; + + // Binary Search Memory + memory[0] <= 9'b000000000; + memory[1] <= 9'b000000111; + memory[2] <= 9'b000000001; + memory[3] <= 9'b000000010; + memory[4] <= 9'b000000011; + memory[5] <= 9'b000000100; + memory[6] <= 9'b000000101; + memory[7] <= 9'b000000110; + memory[8] <= 9'b000000111; + memory[9] <= 9'b000001000; + memory[10] <= 9'b000001001; + memory[11] <= 9'b000001010; + memory[12] <= 9'b000001011; + memory[13] <= 9'b000001100; + memory[14] <= 9'b000001101; + memory[15] <= 9'b000001110; + memory[16] <= 9'b000001111; + memory[17] <= 9'b000010000; + memory[18] <= 9'b000010001; + memory[19] <= 9'b000010010; + end always@(address, clk, memory)begin diff --git a/lab2CA.srcs/sources_1/new/instructionMemory.v b/lab2CA.srcs/sources_1/new/instructionMemory.v index 7347372..e6210eb 100644 --- a/lab2CA.srcs/sources_1/new/instructionMemory.v +++ b/lab2CA.srcs/sources_1/new/instructionMemory.v @@ -34,51 +34,117 @@ module instructionMemory( //String Compare - memory[0] <= 9'b000000000; - memory[1] <= 9'b010000000; - memory[2] <= 9'b010001000; - memory[3] <= 9'b010010000; - memory[4] <= 9'b010011000; - memory[5] <= 9'b000100000; - memory[6] <= 9'b011001001; - memory[7] <= 9'b000101010; - memory[8] <= 9'b011010010; - memory[9] <= 9'b000110100; - memory[10] <= 9'b011011011; - memory[11] <= 9'b000111110; - memory[12] <= 9'b101010000; - memory[13] <= 9'b101000010; - memory[14] <= 9'b101001100; - memory[15] <= 9'b101011110; //ends initialization - memory[16] <= 9'b101000011; - memory[17] <= 9'b101001101; - memory[18] <= 9'b000110000; - memory[19] <= 9'b000111010; - memory[20] <= 9'b110010001; - memory[21] <= 9'b100100001; - memory[22] <= 9'b100110000; - memory[23] <= 9'b110011001; - memory[24] <= 9'b100100001; - memory[25] <= 9'b100101101; - memory[26] <= 9'b011000001; - memory[27] <= 9'b011001001; - memory[28] <= 9'b101000010; - memory[29] <= 9'b101001100; - memory[30] <= 9'b010110111; - memory[31] <= 9'b110010001; - memory[32] <= 9'b101110010; - memory[33] <= 9'b101000000; - memory[34] <= 9'b101001110; - memory[35] <= 9'b001001000; - memory[36] <= 9'b011000001; - memory[37] <= 9'b101000000; - memory[38] <= 9'b101111000; - memory[39] <= 9'b000000000; - +// memory[0] <= 9'b000000000; +// memory[1] <= 9'b010000000; +// memory[2] <= 9'b010001000; +// memory[3] <= 9'b010010000; +// memory[4] <= 9'b010011000; +// memory[5] <= 9'b000100000; +// memory[6] <= 9'b011001001; +// memory[7] <= 9'b000101010; +// memory[8] <= 9'b011010010; +// memory[9] <= 9'b000110100; +// memory[10] <= 9'b011011011; +// memory[11] <= 9'b000111110; +// memory[12] <= 9'b101010000; +// memory[13] <= 9'b101000010; +// memory[14] <= 9'b101001100; +// memory[15] <= 9'b101011110; //ends initialization +// memory[16] <= 9'b101000011; +// memory[17] <= 9'b101001101; +// memory[18] <= 9'b000110000; +// memory[19] <= 9'b000111010; +// memory[20] <= 9'b110010001; +// memory[21] <= 9'b100100001; +// memory[22] <= 9'b100110000; +// memory[23] <= 9'b110011001; +// memory[24] <= 9'b100100001; +// memory[25] <= 9'b100101101; +// memory[26] <= 9'b011000001; +// memory[27] <= 9'b011001001; +// memory[28] <= 9'b101000010; +// memory[29] <= 9'b101001100; +// memory[30] <= 9'b010110111; +// memory[31] <= 9'b110010001; +// memory[32] <= 9'b101110010; +// memory[33] <= 9'b101000000; +// memory[34] <= 9'b101001110; +// memory[35] <= 9'b001001000; +// memory[36] <= 9'b011000001; +// memory[37] <= 9'b101000000; +// memory[38] <= 9'b101111000; +// memory[39] <= 9'b000000000; + + // Binary Search + + memory[0] <= 9'b000000000; + memory[1] <= 9'b000000000; + memory[2] <= 9'b000000000; + memory[3] <= 9'b000000000; + memory[4] <= 9'b000000000; + memory[5] <= 9'b000000000; + memory[6] <= 9'b011001011; //addi R1, 3 (N = 3) + memory[7] <= 9'b011001011; //addi R1, 3 (N = 3) + memory[8] <= 9'b011001011; //addi R1, 3 (N = 3) + memory[9] <= 9'b011001011; //addi R1, 3 (N = 3) + memory[10] <= 9'b011001011; //addi R1, 3 (N = 3) + memory[11] <= 9'b011010010; //addi R2, 2 (inputAddr = 2) + memory[12] <= 9'b000111110; //lb R3, R3 + memory[13] <= 9'b101011010; //banks R3, 1 + memory[14] <= 9'b011001011; //addi R1, 3 (N = 3) + memory[15] <= 9'b101000000; //loop: banks R0, 0 + memory[16] <= 9'b011100010; //slt R0, R1 + memory[17] <= 9'b110000001; //beq R0, Exit + memory[18] <= 9'b100100001; //j Skip0 + memory[19] <= 9'b100101110; //Exit: j Loose + memory[20] <= 9'b010101000; //Skip0: add R2, R0 + memory[21] <= 9'b010101010; //add R2, R1 + memory[22] <= 9'b111110000; //sll R2 + memory[23] <= 9'b101011011; //bankl R3,1 + memory[24] <= 9'b010111100; //add R3, R2 + memory[25] <= 9'b101001100; //banks R1, 2 + memory[26] <= 9'b000100110; //lb R0, R3 + memory[27] <= 9'b010001000; //zero R1 + memory[28] <= 9'b011001010; //addi R1, 1 (numAddr = 1) + memory[29] <= 9'b000101010; //lb R1, R1 + memory[30] <= 9'b100100001; //j SkipU + memory[31] <= 9'b101110001; //j TransLoop + memory[32] <= 9'b101010110; //SkipU: banks R2, 3 + memory[33] <= 9'b100100001; //j SkipD + memory[34] <= 9'b100110111; //j TransLoose + memory[35] <= 9'b010010000; //SkipD: zero R2 + memory[36] <= 9'b010110010; //add R2, R1 + memory[37] <= 9'b010101001; //sub R1, R0 + memory[38] <= 9'b110001001; //beq R1, Go1 + memory[39] <= 9'b100100001; //j Skip1 + memory[40] <= 9'b100101001; //Go1: j Win + memory[41] <= 9'b010001000; //Skip1: zero R1 + memory[42] <= 9'b010101100; //add R1, R2 + memory[43] <= 9'b011100010; //slt R0, R1 + memory[44] <= 9'b110001001; //beq R1, Go2 + memory[45] <= 9'b100100110; //j Skip2 + memory[46] <= 9'b010000000; //Go2: zero R0 + memory[47] <= 9'b011000010; //addi R0, 1 + memory[48] <= 9'b101001111; //bankl R1,3 + memory[49] <= 9'b010100010; //add R0, R1 + memory[50] <= 9'b101001101; //bankl R1,2 + memory[51] <= 9'b101110101; //j loop + memory[52] <= 9'b010001000; //Skip2: zero R1 + memory[53] <= 9'b011001111; //addi R1, -1 + memory[54] <= 9'b101000111; //bankl R0, 3 + memory[55] <= 9'b010101000; //add R1, R0 + memory[56] <= 9'b101000001; //bankl R0,0 + memory[57] <= 9'b101111011; //j loop + memory[58] <= 9'b010000000; //Loose: zero R0 + memory[59] <= 9'b011000111; //addi R0, -1 + memory[60] <= 9'b101000110; //banks R0, 3 + memory[61] <= 9'b100100000; //j Win + memory[62] <= 9'b000000000; //Win: halt + + end - always@(address)begin readData <= memory[address]; end diff --git a/lab2CA.xpr b/lab2CA.xpr index d15e3f5..9a80179 100644 --- a/lab2CA.xpr +++ b/lab2CA.xpr @@ -3,7 +3,7 @@ - +