From 34376a588e9f3f6398219d42e4dc52faf85216ee Mon Sep 17 00:00:00 2001 From: goochey Date: Sat, 16 Feb 2019 12:28:49 -0500 Subject: [PATCH] fetch unit Should be done. also added 2 to 1 mux --- lab2CA.cache/wt/webtalk_pa.xml | 39 +++++++++++++++++++++++++ lab2CA.srcs/sources_1/new/lab2testing.v | 27 ++++++++++++++++- 2 files changed, 65 insertions(+), 1 deletion(-) diff --git a/lab2CA.cache/wt/webtalk_pa.xml b/lab2CA.cache/wt/webtalk_pa.xml index 9c07904..ce7ce88 100644 --- a/lab2CA.cache/wt/webtalk_pa.xml +++ b/lab2CA.cache/wt/webtalk_pa.xml @@ -3,7 +3,11 @@ +<<<<<<< Updated upstream +======= + +>>>>>>> Stashed changes
@@ -20,6 +24,7 @@ This means code written to parse this file will need to be revisited each subseq +<<<<<<< Updated upstream @@ -45,6 +50,34 @@ This means code written to parse this file will need to be revisited each subseq +======= + + + + + + + + + + + + + + + + + + + + + + + + + + +>>>>>>> Stashed changes @@ -68,9 +101,15 @@ This means code written to parse this file will need to be revisited each subseq +<<<<<<< Updated upstream +======= + + + +>>>>>>> Stashed changes
diff --git a/lab2CA.srcs/sources_1/new/lab2testing.v b/lab2CA.srcs/sources_1/new/lab2testing.v index f03b13a..7a439dc 100644 --- a/lab2CA.srcs/sources_1/new/lab2testing.v +++ b/lab2CA.srcs/sources_1/new/lab2testing.v @@ -56,4 +56,29 @@ module regFile(input wire clk, reset, .D(r3_out), .switch(op1_idx)); -endmodule \ No newline at end of file +<<<<<<< Updated upstream +endmodule +======= +endmodule + +module register(input wire clk, reset, + input wire [1:0] En, + input wire [7:0] Din, + output reg [7:0] Dout); + +endmodule + +module MUX(); + +endmodule + +module fetchUnit(input wire clk, reset, write_en); + register progcount( + .clk(clk), + .reset(reset), + .En(), + .Din(), + .Dout()); + +endmodule +>>>>>>> Stashed changes