From 352aeefd1b640bbf589588a3b53f9239356b2cbb Mon Sep 17 00:00:00 2001 From: WilliamMiceli Date: Fri, 29 Mar 2019 16:13:50 -0400 Subject: [PATCH] Made to write only once on positive edge of clock, Vivado now recognizes it as RTL_RAM --- lab2CA.srcs/sources_1/new/dataMemory.v | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/lab2CA.srcs/sources_1/new/dataMemory.v b/lab2CA.srcs/sources_1/new/dataMemory.v index 05c4b77..a39032f 100644 --- a/lab2CA.srcs/sources_1/new/dataMemory.v +++ b/lab2CA.srcs/sources_1/new/dataMemory.v @@ -239,14 +239,12 @@ module dataMemory( end - always @ (address, clk, memory) begin - if(clk == 1'b1)begin + always @ (posedge clk) + begin + if(writeEnable == 1'b1) + memory[address] <= writeData; + else readData <= memory[address]; - if(writeEnable == 1'b1) - memory[address] <= writeData; - else - memory[address] <= memory[address]; - end end endmodule