diff --git a/lab2CA.srcs/sources_1/new/BasicModules.v b/lab2CA.srcs/sources_1/new/BasicModules.v
index 7354732..e493548 100644
--- a/lab2CA.srcs/sources_1/new/BasicModules.v
+++ b/lab2CA.srcs/sources_1/new/BasicModules.v
@@ -222,6 +222,58 @@ module nor_1bit(
 
 endmodule
 
+module nor_9bit(
+    input wire [8:0] A,
+    input wire [8:0] B,
+    output wire [8:0] C);
+    
+    nor_1bit nor0(
+        .A(A[0]),
+        .B(B[0]),
+        .C(C[0]));
+        
+    nor_1bit nor1(
+        .A(A[1]),
+        .B(B[1]),
+        .C(C[1]));
+        
+    nor_1bit nor2(
+        .A(A[2]),
+        .B(B[2]),
+        .C(C[2]));
+        
+    nor_1bit nor3(
+        .A(A[3]),
+        .B(B[3]),
+        .C(C[3]));
+        
+    nor_1bit nor4(
+        .A(A[4]),
+        .B(B[4]),
+        .C(C[4]));
+        
+    nor_1bit nor5(
+        .A(A[5]),
+        .B(B[5]),
+        .C(C[5]));
+        
+    nor_1bit nor6(
+        .A(A[6]),
+        .B(B[6]),
+        .C(C[6]));
+        
+    nor_1bit nor7(
+        .A(A[7]),
+        .B(B[7]),
+        .C(C[7]));
+        
+    nor_1bit nor8(
+        .A(A[8]),
+        .B(B[8]),
+        .C(C[8]));
+
+endmodule
+
 module not_1bit(
     input wire A,
     output wire B);
@@ -272,6 +324,67 @@ module not_9bit(
 
 endmodule
 
+module or_1bit(
+    input wire A,
+    input wire B,
+    output wire C);
+    
+    assign C = A | B;
+
+endmodule
+
+module or_9bit(
+    input wire [8:0] A,
+    input wire [8:0] B,
+    output wire [8:0] C);
+    
+    or_1bit or0(
+        .A(A[0]),
+        .B(B[0]),
+        .C(C[0]));
+        
+    or_1bit or1(
+        .A(A[1]),
+        .B(B[1]),
+        .C(C[1]));
+        
+    or_1bit or2(
+        .A(A[2]),
+        .B(B[2]),
+        .C(C[2]));
+        
+    or_1bit or3(
+        .A(A[3]),
+        .B(B[3]),
+        .C(C[3]));
+        
+    or_1bit or4(
+        .A(A[4]),
+        .B(B[4]),
+        .C(C[4]));
+        
+    or_1bit or5(
+        .A(A[5]),
+        .B(B[5]),
+        .C(C[5]));
+        
+    or_1bit or6(
+        .A(A[6]),
+        .B(B[6]),
+        .C(C[6]));
+        
+    or_1bit or7(
+        .A(A[7]),
+        .B(B[7]),
+        .C(C[7]));
+        
+    or_1bit or8(
+        .A(A[8]),
+        .B(B[8]),
+        .C(C[8]));
+
+endmodule
+
 module register(input wire clk, reset,
                 input wire [1:0] En,
                 input wire [8:0] Din,
diff --git a/lab2CA.xpr b/lab2CA.xpr
index 917a245..404364e 100644
--- a/lab2CA.xpr
+++ b/lab2CA.xpr
@@ -81,6 +81,14 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PSRCDIR/sources_1/new/ALU.v">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
         <Option Name="TopModule" Val="RegFile"/>
@@ -95,14 +103,6 @@
     </FileSet>
     <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
       <Filter Type="Srcs"/>
-      <File Path="$PSRCDIR/sim_1/new/ALU.v">
-        <FileInfo>
-          <Attr Name="AutoDisabled" Val="1"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="implementation"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
         <Option Name="TopModule" Val="RegFile"/>