diff --git a/lab2CA.cache/wt/webtalk_pa.xml b/lab2CA.cache/wt/webtalk_pa.xml index cd92fda..52d1275 100644 --- a/lab2CA.cache/wt/webtalk_pa.xml +++ b/lab2CA.cache/wt/webtalk_pa.xml @@ -3,7 +3,7 @@ - +
@@ -17,7 +17,7 @@ This means code written to parse this file will need to be revisited each subseq - + @@ -40,7 +40,7 @@ This means code written to parse this file will need to be revisited each subseq - + @@ -49,16 +49,16 @@ This means code written to parse this file will need to be revisited each subseq - + - + - + @@ -67,7 +67,7 @@ This means code written to parse this file will need to be revisited each subseq - + @@ -75,11 +75,11 @@ This means code written to parse this file will need to be revisited each subseq - + - + @@ -93,7 +93,7 @@ This means code written to parse this file will need to be revisited each subseq - + @@ -128,7 +128,7 @@ This means code written to parse this file will need to be revisited each subseq - + @@ -136,7 +136,7 @@ This means code written to parse this file will need to be revisited each subseq - + diff --git a/lab2CA.srcs/sources_1/new/ALU.v b/lab2CA.srcs/sources_1/new/ALU.v index 3ac2a6a..f1456e1 100644 --- a/lab2CA.srcs/sources_1/new/ALU.v +++ b/lab2CA.srcs/sources_1/new/ALU.v @@ -65,6 +65,8 @@ module ALU( .A(operand0), .B(result_K)); // L (1011) + // Will hacked in here + // M (1100) // N (1101) // O (1110) @@ -84,7 +86,7 @@ module ALU( .I(result_I), .J(result_J), .K(result_K), - .L(result_L), + .L(9'b000000000), .M(result_M), .N(result_N), .O(result_O), diff --git a/lab2CA.srcs/sources_1/new/BasicModules.v b/lab2CA.srcs/sources_1/new/BasicModules.v index 81904af..d033266 100644 --- a/lab2CA.srcs/sources_1/new/BasicModules.v +++ b/lab2CA.srcs/sources_1/new/BasicModules.v @@ -932,6 +932,7 @@ module shift_right_arithmetic( endmodule + //testbench module shift_right_arithmetic_tb(); reg [8:0] a; diff --git a/lab2CA.srcs/sources_1/new/ControlUnit.v b/lab2CA.srcs/sources_1/new/ControlUnit.v index 3722fe7..aff7adc 100644 --- a/lab2CA.srcs/sources_1/new/ControlUnit.v +++ b/lab2CA.srcs/sources_1/new/ControlUnit.v @@ -41,6 +41,15 @@ module ControlUnit( mem <= 1'b0; link <= 1'b0; end + 4'b0100: begin + aluOut <= 4'b1011; //zero + RegEn <= 1'b0; + FU <= 3'b001; // Disable Branching + halt <= 1'b0; + addi <= 1'b0; + mem <= 1'b0; + link <= 1'b0; + end 4'b1110: if(functBit == 1) begin aluOut <= 4'b0100; //and