From 3d8ae740f035629b3b1ead78c45438805a02e80a Mon Sep 17 00:00:00 2001 From: WilliamMiceli Date: Fri, 15 Feb 2019 14:55:11 -0500 Subject: [PATCH] Added 1-bit adder --- lab2CA.cache/wt/webtalk_pa.xml | 90 +++--------------------- lab2CA.srcs/sources_1/new/BasicModules.v | 14 ++++ 2 files changed, 23 insertions(+), 81 deletions(-) diff --git a/lab2CA.cache/wt/webtalk_pa.xml b/lab2CA.cache/wt/webtalk_pa.xml index ef11cd9..d858caf 100644 --- a/lab2CA.cache/wt/webtalk_pa.xml +++ b/lab2CA.cache/wt/webtalk_pa.xml @@ -3,13 +3,9 @@ -<<<<<<< Updated upstream - -======= - ->>>>>>> Stashed changes +
- +
@@ -21,87 +17,19 @@ This means code written to parse this file will need to be revisited each subseq -<<<<<<< Updated upstream - - - - -======= - - - ->>>>>>> Stashed changes - - + + -<<<<<<< Updated upstream - - -======= - - - - ->>>>>>> Stashed changes - - - - -<<<<<<< Updated upstream - - - -======= - - ->>>>>>> Stashed changes - - - - - - - - - - - - -<<<<<<< Updated upstream - -======= - - ->>>>>>> Stashed changes - + + + - - - - - - - -<<<<<<< Updated upstream - - - - + - -======= - - - - - - - - ->>>>>>> Stashed changes +
diff --git a/lab2CA.srcs/sources_1/new/BasicModules.v b/lab2CA.srcs/sources_1/new/BasicModules.v index bccd814..a433e4b 100644 --- a/lab2CA.srcs/sources_1/new/BasicModules.v +++ b/lab2CA.srcs/sources_1/new/BasicModules.v @@ -1,5 +1,17 @@ `timescale 1ns / 1ps +module adder_1bit( + input wire A, + input wire B, + input wire Cin, + output wire S, + output wire Cout); + + assign S = (A ^ B) ^ Cin; + assign Cout = ((A ^ B) & Cin) | (A & B); + +endmodule + module gen_clock(); reg clk; @@ -19,6 +31,7 @@ module inverter( output wire B); assign B = ~A; + endmodule module mux(input wire [1:0] switch, @@ -33,6 +46,7 @@ module mux(input wire [1:0] switch, default: out = D; endcase end + endmodule module register(input wire clk, reset,