diff --git a/lab2CA.runs/impl_1/gen_run.xml b/lab2CA.runs/impl_1/gen_run.xml index faca896..e16601e 100644 --- a/lab2CA.runs/impl_1/gen_run.xml +++ b/lab2CA.runs/impl_1/gen_run.xml @@ -1,14 +1,12 @@ - - - - + + - + @@ -18,11 +16,8 @@ - - - @@ -31,25 +26,8 @@ - - - - - - - - - - - - - - - - - diff --git a/lab2CA.runs/synth_1/gen_run.xml b/lab2CA.runs/synth_1/gen_run.xml index 60496de..afce82b 100644 --- a/lab2CA.runs/synth_1/gen_run.xml +++ b/lab2CA.runs/synth_1/gen_run.xml @@ -4,8 +4,6 @@ - - diff --git a/lab2CA.sim/sim_1/behav/xsim/slt_tb.tcl b/lab2CA.sim/sim_1/behav/xsim/slt_tb.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/slt_tb.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/lab2CA.sim/sim_1/behav/xsim/slt_tb_vlog.prj b/lab2CA.sim/sim_1/behav/xsim/slt_tb_vlog.prj new file mode 100644 index 0000000..c097ced --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/slt_tb_vlog.prj @@ -0,0 +1,9 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk.jou index dcabd11..22bd10f 100644 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk.jou +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk.jou @@ -2,11 +2,11 @@ # Webtalk v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Wed Feb 27 11:47:34 2019 -# Process ID: 6784 -# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim -# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log -# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou +# Start of session at: Tue Mar 12 19:46:24 2019 +# Process ID: 6512 +# Current directory: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim\webtalk.jou #----------------------------------------------------------- -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl -notrace +source C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_4236.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_4236.backup.jou new file mode 100644 index 0000000..d7df5f9 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk_4236.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.3 (64-bit) +# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 +# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 +# Start of session at: Tue Mar 12 19:44:30 2019 +# Process ID: 4236 +# Current directory: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_6516.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_6516.backup.jou deleted file mode 100644 index 4eb8fc3..0000000 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk_6516.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Thu Feb 21 14:24:16 2019 -# Process ID: 6516 -# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim -# Command line: wbtcv.exe -mode batch -source C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/regFile_tb_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log -# Journal file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou -#----------------------------------------------------------- -source C:/Users/JoseIgnacio/CA -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_7276.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_7276.backup.jou deleted file mode 100644 index bbb2a8d..0000000 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk_7276.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Wed Feb 27 11:36:59 2019 -# Process ID: 7276 -# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim -# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log -# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou -#----------------------------------------------------------- -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/decoder_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/xelab.pb b/lab2CA.sim/sim_1/behav/xsim/xelab.pb index 5862552..a500353 100644 Binary files a/lab2CA.sim/sim_1/behav/xsim/xelab.pb and b/lab2CA.sim/sim_1/behav/xsim/xelab.pb differ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/Compile_Options.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/Compile_Options.txt new file mode 100644 index 0000000..1e4d769 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "0a5803efda44405bb28bbf43ba22e808" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" -L "xpm" --snapshot "slt_tb_behav" "xil_defaultlib.slt_tb" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/TempBreakPointFile.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/obj/xsim_1.c b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/obj/xsim_1.c new file mode 100644 index 0000000..271491f --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/obj/xsim_1.c @@ -0,0 +1,109 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_4(char*, char *); +extern void execute_9(char*, char *); +extern void execute_10(char*, char *); +extern void execute_11(char*, char *); +extern void execute_12(char*, char *); +extern void execute_3(char*, char *); +extern void execute_6(char*, char *); +extern void execute_7(char*, char *); +extern void execute_8(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void execute_15(char*, char *); +extern void execute_16(char*, char *); +extern void execute_17(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[15] = {(funcp)execute_4, (funcp)execute_9, (funcp)execute_10, (funcp)execute_11, (funcp)execute_12, (funcp)execute_3, (funcp)execute_6, (funcp)execute_7, (funcp)execute_8, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)execute_17, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 15; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/slt_tb_behav/xsim.reloc", (void **)funcTab, 15); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/slt_tb_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/slt_tb_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/slt_tb_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/slt_tb_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/slt_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/usage_statistics_ext_xsim.xml b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000..f4f5b9a --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,43 @@ + + +
+
+ + + + + + + + + + + + + + + +
+
+ + + + + + +
+
+
+
+
+ +
+
+ + + + +
+
+
+ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/xsim_webtalk.tcl b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/xsim_webtalk.tcl new file mode 100644 index 0000000..3e10e0b --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/xsim_webtalk.tcl @@ -0,0 +1,42 @@ +webtalk_init -webtalk_dir C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/ +webtalk_register_client -client project +webtalk_add_data -client project -key date_generated -value "Tue Mar 12 19:48:08 2019" -context "software_version_and_target_device" +webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device" +webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" +webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" +webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "fe5d421c9f2b5ebc958da28a6d468b09" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "5" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" +webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i7-3770K CPU @ 3.50GHz" -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "3492 MHz" -context "user_environment" +webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "17.000 GB" -context "user_environment" +webtalk_register_client -client xsim +webtalk_add_data -client xsim -key File_Counter -value "2" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key Command -value "xelab" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key Vhdl2008 -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key GenDLL -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key SDFModeling -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key HWCosim -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key DPI_Used -value "false" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key Debug -value "typical" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key Simulation_Image_Code -value "65 KB" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Image_Data -value "2 KB" -context "xsim\\usage" +webtalk_add_data -client xsim -key Total_Nets -value "0" -context "xsim\\usage" +webtalk_add_data -client xsim -key Total_Processes -value "17" -context "xsim\\usage" +webtalk_add_data -client xsim -key Total_Instances -value "3" -context "xsim\\usage" +webtalk_add_data -client xsim -key Xilinx_HDL_Libraries_Used -value "secureip unimacro_ver unisims_ver " -context "xsim\\usage" +webtalk_add_data -client xsim -key Compiler_Time -value "0.62_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Compiler_Memory -value "36408_KB" -context "xsim\\usage" +webtalk_transmit -clientid 1095157529 -regid "" -xml C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/Johannes/ece3570-lab2/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_terminate diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/xsim.mem b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/xsim.mem new file mode 100644 index 0000000..61c7e52 Binary files /dev/null and b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/slt_tb_behav/xsim.mem differ diff --git a/lab2CA.sim/sim_1/behav/xsim/xvlog.pb b/lab2CA.sim/sim_1/behav/xsim/xvlog.pb index bf58768..b155e40 100644 Binary files a/lab2CA.sim/sim_1/behav/xsim/xvlog.pb and b/lab2CA.sim/sim_1/behav/xsim/xvlog.pb differ diff --git a/lab2CA.srcs/sources_1/bd/design_1/design_1.bd b/lab2CA.srcs/sources_1/bd/design_1/design_1.bd new file mode 100644 index 0000000..1eeb2fe --- /dev/null +++ b/lab2CA.srcs/sources_1/bd/design_1/design_1.bd @@ -0,0 +1,11 @@ +{ + "design": { + "design_info": { + "boundary_crc": "0x0", + "name": "design_1", + "synth_flow_mode": "Hierarchical", + "tool_version": "2018.3" + }, + "design_tree": {} + } +} \ No newline at end of file diff --git a/lab2CA.srcs/sources_1/new/BasicModules.v b/lab2CA.srcs/sources_1/new/BasicModules.v index 0f81f0b..f09edb7 100644 --- a/lab2CA.srcs/sources_1/new/BasicModules.v +++ b/lab2CA.srcs/sources_1/new/BasicModules.v @@ -884,6 +884,52 @@ module shift_right_arithmetic_tb(); end endmodule +module slt ( + input wire en, + input wire [8:0] inA, inB, + output reg outA); + + always @(inA, inB)begin + if (inA < inB) begin + outA = 1; + end + else begin + outA = 0; + end + end +endmodule + +//testbench +module slt_tb(); + reg enable; + reg [8:0] indexA; + reg [8:0] indexB; + wire outputA; + + slt slt0( + .en(enable), + .inA(indexA), + .inB(indexB), + .outA(outputA)); + + initial begin + enable = 0; + #5 + enable = 1; + #5 + indexA = 9'b000000000; + indexB = 9'b000000000; + #10 + indexA = 9'b000000000; + indexB = 9'b111100000; + #10 + indexA = 9'b000001111; + indexB = 9'b000000000; + #10 + $finish; + end +endmodule + module sub_9bit( input wire [8:0] A, input wire [8:0] B, diff --git a/lab2CA.xpr b/lab2CA.xpr index 5c02702..a533f61 100644 --- a/lab2CA.xpr +++ b/lab2CA.xpr @@ -3,7 +3,7 @@ - + + + + + + + + +