Fixed pip enables, fixed Nop/Halt

lab2CA.srcs/sources_1/new/CPU9bits.v

@@ -29,7 +29,7 @@ module CPU9bits(
      fDPipReg pipe1(
         .clk(clk), 
 	    .reset(reset), 
-	    .En(RegEn), 
+	    .En(1'b0), 
 	    .Din(FDOut), 
 	    .Dout(FDPipOut)
 	 );
@@ -44,7 +44,7 @@ module CPU9bits(
     eMPipReg pipe2(  
         .clk(clk), 
 	    .reset(reset), 
-	    .En(RegEn), 
+	    .En(1'b0), 
 	    .Din(EMOut), 
 	    .Dout(EMPipOut)
 	 );
@@ -72,13 +72,12 @@ module CPU9bits_tb();
     	#5 clk = ~clk; // Period to be determined
 	end
 
-
     CPU9bits CPU9bits0(
         .reset(reset),
         .clk(clk),
         .done(done),
         .result(result));
-        
+
     initial begin
     	#5
     	reset = 1'b1;

lab2CA.srcs/sources_1/new/ControlUnit.v

@@ -7,14 +7,14 @@ module ControlUnit(
     output reg [2:0] FU,
     output reg [1:0] bank,
     output reg addi, mem, dataMemEn, RegEn, halt, link, js
-        );
+    );
     
     always @(instIn, functBit)
     begin
         case(instIn)
         4'b0000: // Halt/NOP
             begin 
-            halt <= 1'b1;
+            halt <= functBit;
             RegEn <= 1'b1; 
             FU <= 3'b001; // Disable Branching
             addi <= 1'b0;