Reordered into alphabetical order

lab2CA.srcs/sources_1/new/BasicModules.v

@@ -1,8 +1,5 @@
 `timescale 1ns / 1ps
 
-module BasicModules();
-endmodule
-
 module gen_clock();
 
     reg clk;
@@ -17,6 +14,20 @@ module gen_clock();
 
 endmodule
 
+module mux(input wire [1:0] switch,
+           input wire [8:0] A,B,C,D,
+           output reg [8:0] out);
+           
+    always @(A,B,C,D,switch) begin
+        case (switch)
+            2'b00 : out = A;
+            2'b01 : out = B;
+            2'b10 : out = C;
+            default: out = D;
+        endcase
+    end
+endmodule
+
 module register(input wire clk, reset,
                 input wire [1:0] En,
                 input wire [8:0] Din,
@@ -34,19 +45,4 @@ module register(input wire clk, reset,
         end
     end
 
-endmodule
+endmodule
-
-module mux(input wire [1:0] switch,
-           input wire [8:0] A,B,C,D,
-           output reg [8:0] out);
-           
-    always @(A,B,C,D,switch) begin
-        case (switch)
-            2'b00 : out = A;
-            2'b01 : out = B;
-            2'b10 : out = C;
-            default: out = D;
-        endcase
-    end
-endmodule
-